From ccd7ac4f754221f443324fdf61e6f5fca10a58cd Mon Sep 17 00:00:00 2001 From: Anton Lydike Date: Tue, 10 Oct 2023 11:04:39 +0100 Subject: [PATCH] adding tests, fixing bugs --- riscemu/core/usermode_cpu.py | 4 +- snitch/__main__.py | 10 ++-- snitch/frep.py | 22 ++++++++- snitch/regs.py | 6 --- snitch/xssr.py | 2 +- test/filecheck/snitch/frep_only.asm | 17 +++++++ test/filecheck/snitch/xssr_only.asm | 69 +++++++++++++++++++++++++++ test/filecheck/snitch_simple.asm | 74 ----------------------------- 8 files changed, 115 insertions(+), 89 deletions(-) create mode 100644 test/filecheck/snitch/frep_only.asm create mode 100644 test/filecheck/snitch/xssr_only.asm delete mode 100644 test/filecheck/snitch_simple.asm diff --git a/riscemu/core/usermode_cpu.py b/riscemu/core/usermode_cpu.py index 8f1c83f..b792d9e 100644 --- a/riscemu/core/usermode_cpu.py +++ b/riscemu/core/usermode_cpu.py @@ -64,9 +64,7 @@ def step(self, verbose: bool = False): self.cycle += 1 ins = self.mmu.read_ins(self.pc) if verbose: - print( - FMT_CPU + " Running 0x{:08X}:{} {}".format(self.pc, FMT_NONE, ins) - ) + print(FMT_CPU + " 0x{:08X}:{} {}".format(self.pc, FMT_NONE, ins)) self.pc += self.INS_XLEN self.run_instruction(ins) except RiscemuBaseException as ex: diff --git a/snitch/__main__.py b/snitch/__main__.py index b0f28d5..4033caa 100644 --- a/snitch/__main__.py +++ b/snitch/__main__.py @@ -8,18 +8,20 @@ import sys from .regs import StreamingRegs -from .xssr import RV32_Xssr_pseudo +from .xssr import Xssr_pseudo +from .frep import FrepEnabledCpu, Xfrep from riscemu.riscemu_main import RiscemuMain class SnitchMain(RiscemuMain): - def configure_cpu(self): - super().configure_cpu() + def instantiate_cpu(self): + self.cpu = FrepEnabledCpu(self.selected_ins_sets, self.cfg) self.cpu.regs = StreamingRegs(self.cpu.mmu) + self.configure_cpu() def register_all_isas(self): super().register_all_isas() - self.available_ins_sets.update({"Xssr": RV32_Xssr_pseudo}) + self.available_ins_sets.update({"Xssr": Xssr_pseudo, "Xfrep": Xfrep}) if __name__ == "__main__": diff --git a/snitch/frep.py b/snitch/frep.py index 47c3c8c..876fc50 100644 --- a/snitch/frep.py +++ b/snitch/frep.py @@ -1,5 +1,6 @@ from typing import List, Type, Union, Set, Literal +from riscemu.colors import FMT_CPU, FMT_NONE from riscemu.config import RunConfig from riscemu.core import UserModeCPU from riscemu.instructions import InstructionSet, Instruction, RV32F @@ -27,7 +28,8 @@ def __init__(self, instruction_sets: List[Type["InstructionSet"]], conf: RunConf def step(self, verbose: bool = False): if self.repeats is None: - super().step() + super().step(verbose=verbose) + return # get the spec spec: FrepState = self.repeats self.repeats = None @@ -37,6 +39,22 @@ def step(self, verbose: bool = False): for i in range(spec.ins_count) ] + if verbose: + print( + FMT_CPU + + "┌────── floating point repetition ({}) {} times".format( + spec.mode, spec.rep_count + 1 + ) + ) + for i, ins in enumerate(instructions): + print( + FMT_CPU + + "│ 0x{:08X}:{} {}".format( + self.pc + i * self.INS_XLEN, FMT_NONE, ins + ) + ) + print(FMT_CPU + "└────── end of floating point repetition" + FMT_NONE) + pc = self.pc if spec.mode == "outer": for _ in range(spec.rep_count + 1): @@ -46,6 +64,8 @@ def step(self, verbose: bool = False): for ins in instructions: for _ in range(spec.rep_count + 1): self.run_instruction(ins) + else: + raise RuntimeError(f"Unknown frep mode: {spec.mode}") self.pc = pc + (spec.ins_count * self.INS_XLEN) diff --git a/snitch/regs.py b/snitch/regs.py index 0ec6f28..deae1b6 100644 --- a/snitch/regs.py +++ b/snitch/regs.py @@ -76,9 +76,6 @@ def get_f(self, reg, mark_read=True) -> "Float32": addr = stream.base + (stream.pos * stream.stride) val = self.mem.read_float(addr) # increment pos - print( - "stream: got val {} from addr 0x{:x}, stream {}".format(val, addr, stream) - ) stream.pos += 1 return val @@ -92,8 +89,5 @@ def set_f(self, reg, val: "Float32", mark_set=True) -> bool: addr = stream.base + (stream.pos * stream.stride) self.mem.write(addr, 4, bytearray(val.bytes)) - print( - "stream: wrote val {} into addr 0x{:x}, stream {}".format(val, addr, stream) - ) stream.pos += 1 return True diff --git a/snitch/xssr.py b/snitch/xssr.py index 1c90d1a..982af51 100644 --- a/snitch/xssr.py +++ b/snitch/xssr.py @@ -3,7 +3,7 @@ from .regs import StreamingRegs, StreamDef, StreamMode -class RV32_Xssr_pseudo(InstructionSet): +class Xssr_pseudo(InstructionSet): def instruction_ssr_enable(self, ins: Instruction): self._stream.enabled = True diff --git a/test/filecheck/snitch/frep_only.asm b/test/filecheck/snitch/frep_only.asm new file mode 100644 index 0000000..a79e7d2 --- /dev/null +++ b/test/filecheck/snitch/frep_only.asm @@ -0,0 +1,17 @@ +.text +.globl main +main: + li t0, 0 + fcvt.s.w ft0, t0 + li t0, 1 + fcvt.s.w ft1, t0 + + printf "ft0 = {}, ft1 = {}", ft0, ft1 + // repeat 100 times + li t0, 99 + frep.i t0, 1, 0, 0 + fadd.s ft0, ft0, ft1 // add one + printf "100 * 1 = {}", ft1 + + li a0, 0 + ret diff --git a/test/filecheck/snitch/xssr_only.asm b/test/filecheck/snitch/xssr_only.asm new file mode 100644 index 0000000..092f8be --- /dev/null +++ b/test/filecheck/snitch/xssr_only.asm @@ -0,0 +1,69 @@ +// RUN: python3 -m snitch %s -o libc | filecheck %s + +.data + +vec0: +.word 0x0, 0x3f800000, 0x40000000, 0x40400000, 0x40800000, 0x40a00000, 0x40c00000, 0x40e00000, 0x41000000, 0x41100000 +vec1: +.word 0x0, 0x3f800000, 0x40000000, 0x40400000, 0x40800000, 0x40a00000, 0x40c00000, 0x40e00000, 0x41000000, 0x41100000 +dest: +.space 40 + +.text +.globl main + +main: + // ssr config + ssr.configure 0, 10, 4 + ssr.configure 1, 10, 4 + ssr.configure 2, 10, 4 + + la a0, vec0 + ssr.read a0, 0, 0 + + la a0, vec1 + ssr.read a0, 1, 0 + + la a0, dest + ssr.write a0, 2, 0 + + ssr.enable + + // set up loop + li a0, 10 +loop: + fadd.s ft2, ft0, ft1 + + addi a0, a0, -1 + bne a0, zero, loop + + // end of loop: + ssr.disable + + // check values were written correctly: + la t0, vec0 + la t1, vec1 + li a0, 40 +loop2: + add s0, t0, a0 + add s1, t1, a0 + // load vec0 element + flw ft0, 0(s0) + // load vec1 element + flw ft1, 0(s1) + // assert ft1 - ft0 == ft0 + fsub.s ft2, ft1, ft0 + feq.s s0, ft2, ft0 + beq zero, s0, fail + + addi a0, a0, -4 + bne a0, zero, loop2 + + ret + +fail: + printf "failed {} != {} (at {})", ft0, ft1, a0 + li a0, -1 + ret + +// CHECK: [CPU] Program exited with code 0 diff --git a/test/filecheck/snitch_simple.asm b/test/filecheck/snitch_simple.asm deleted file mode 100644 index 3cdab19..0000000 --- a/test/filecheck/snitch_simple.asm +++ /dev/null @@ -1,74 +0,0 @@ -// RUN: python3 -m snitch %s -o libc | filecheck %s - -.data - -vec0: -.word 0x0, 0x3f800000, 0x40000000, 0x40400000, 0x40800000, 0x40a00000, 0x40c00000, 0x40e00000, 0x41000000, 0x41100000 -vec1: -.word 0x0, 0x3f800000, 0x40000000, 0x40400000, 0x40800000, 0x40a00000, 0x40c00000, 0x40e00000, 0x41000000, 0x41100000 -dest: -.space 40 - -.text -.globl main - -main: - // ssr config - ssr.configure 0, 10, 4 - ssr.configure 1, 10, 4 - ssr.configure 2, 10, 4 - - la a0, vec0 - ssr.read a0, 0, 0 - - la a0, vec1 - ssr.read a0, 1, 0 - - la a0, dest - ssr.write a0, 2, 0 - - ssr.enable - - // set up loop - li a0, 100 -loop: - fadd.s ft2, ft0, ft1 - - addi a0, a0, -1 - bne a0, zero, loop - - // end of loop: - ssr.disable - - ret - -//CHECK: stream: got val 0.0 from addr 0x80148, stream StreamDef(base=524616, bound=10, stride=4, mode=, dim=0, pos=0) -//CHECK_NEXT: stream: got val 0.0 from addr 0x80170, stream StreamDef(base=524656, bound=10, stride=4, mode=, dim=0, pos=0) -//CHECK_NEXT: stream: wrote val 0.0 into addr 0x80198, stream StreamDef(base=524696, bound=10, stride=4, mode=, dim=0, pos=0) -//CHECK_NEXT: stream: got val 1.0 from addr 0x8014c, stream StreamDef(base=524616, bound=10, stride=4, mode=, dim=0, pos=1) -//CHECK_NEXT: stream: got val 1.0 from addr 0x80174, stream StreamDef(base=524656, bound=10, stride=4, mode=, dim=0, pos=1) -//CHECK_NEXT: stream: wrote val 2.0 into addr 0x8019c, stream StreamDef(base=524696, bound=10, stride=4, mode=, dim=0, pos=1) -//CHECK_NEXT: stream: got val 2.0 from addr 0x80150, stream StreamDef(base=524616, bound=10, stride=4, mode=, dim=0, pos=2) -//CHECK_NEXT: stream: got val 2.0 from addr 0x80178, stream StreamDef(base=524656, bound=10, stride=4, mode=, dim=0, pos=2) -//CHECK_NEXT: stream: wrote val 4.0 into addr 0x801a0, stream StreamDef(base=524696, bound=10, stride=4, mode=, dim=0, pos=2) -//CHECK_NEXT: stream: got val 3.0 from addr 0x80154, stream StreamDef(base=524616, bound=10, stride=4, mode=, dim=0, pos=3) -//CHECK_NEXT: stream: got val 3.0 from addr 0x8017c, stream StreamDef(base=524656, bound=10, stride=4, mode=, dim=0, pos=3) -//CHECK_NEXT: stream: wrote val 6.0 into addr 0x801a4, stream StreamDef(base=524696, bound=10, stride=4, mode=, dim=0, pos=3) -//CHECK_NEXT: stream: got val 4.0 from addr 0x80158, stream StreamDef(base=524616, bound=10, stride=4, mode=, dim=0, pos=4) -//CHECK_NEXT: stream: got val 4.0 from addr 0x80180, stream StreamDef(base=524656, bound=10, stride=4, mode=, dim=0, pos=4) -//CHECK_NEXT: stream: wrote val 8.0 into addr 0x801a8, stream StreamDef(base=524696, bound=10, stride=4, mode=, dim=0, pos=4) -//CHECK_NEXT: stream: got val 5.0 from addr 0x8015c, stream StreamDef(base=524616, bound=10, stride=4, mode=, dim=0, pos=5) -//CHECK_NEXT: stream: got val 5.0 from addr 0x80184, stream StreamDef(base=524656, bound=10, stride=4, mode=, dim=0, pos=5) -//CHECK_NEXT: stream: wrote val 10.0 into addr 0x801ac, stream StreamDef(base=524696, bound=10, stride=4, mode=, dim=0, pos=5) -//CHECK_NEXT: stream: got val 6.0 from addr 0x80160, stream StreamDef(base=524616, bound=10, stride=4, mode=, dim=0, pos=6) -//CHECK_NEXT: stream: got val 6.0 from addr 0x80188, stream StreamDef(base=524656, bound=10, stride=4, mode=, dim=0, pos=6) -//CHECK_NEXT: stream: wrote val 12.0 into addr 0x801b0, stream StreamDef(base=524696, bound=10, stride=4, mode=, dim=0, pos=6) -//CHECK_NEXT: stream: got val 7.0 from addr 0x80164, stream StreamDef(base=524616, bound=10, stride=4, mode=, dim=0, pos=7) -//CHECK_NEXT: stream: got val 7.0 from addr 0x8018c, stream StreamDef(base=524656, bound=10, stride=4, mode=, dim=0, pos=7) -//CHECK_NEXT: stream: wrote val 14.0 into addr 0x801b4, stream StreamDef(base=524696, bound=10, stride=4, mode=, dim=0, pos=7) -//CHECK_NEXT: stream: got val 8.0 from addr 0x80168, stream StreamDef(base=524616, bound=10, stride=4, mode=, dim=0, pos=8) -//CHECK_NEXT: stream: got val 8.0 from addr 0x80190, stream StreamDef(base=524656, bound=10, stride=4, mode=, dim=0, pos=8) -//CHECK_NEXT: stream: wrote val 16.0 into addr 0x801b8, stream StreamDef(base=524696, bound=10, stride=4, mode=, dim=0, pos=8) -//CHECK_NEXT: stream: got val 9.0 from addr 0x8016c, stream StreamDef(base=524616, bound=10, stride=4, mode=, dim=0, pos=9) -//CHECK_NEXT: stream: got val 9.0 from addr 0x80194, stream StreamDef(base=524656, bound=10, stride=4, mode=, dim=0, pos=9) -//CHECK_NEXT: stream: wrote val 18.0 into addr 0x801bc, stream StreamDef(base=524696, bound=10, stride=4, mode=, dim=0, pos=9)