diff --git a/riscemu/core/registers.py b/riscemu/core/registers.py
index 7b34efd..3729f9b 100644
--- a/riscemu/core/registers.py
+++ b/riscemu/core/registers.py
@@ -5,7 +5,7 @@
 """
 
 from collections import defaultdict
-from typing import Union
+from typing import Union, Type
 
 from ..helpers import *
 
@@ -85,7 +85,7 @@ class Registers:
     }
 
     flen: int
-    _float_type: type[BaseFloat]
+    _float_type: Type[BaseFloat]
 
     def __init__(self, infinite_regs: bool = False, flen: int = 32):
         self.vals: dict[str, Int32] = defaultdict(UInt32)
diff --git a/riscemu/instructions/float_base.py b/riscemu/instructions/float_base.py
index f6b3b51..f2b9634 100644
--- a/riscemu/instructions/float_base.py
+++ b/riscemu/instructions/float_base.py
@@ -1,4 +1,4 @@
-from typing import ClassVar, Generic, TypeVar, Tuple, Iterable, Callable
+from typing import ClassVar, Generic, TypeVar, Tuple, Iterable, Callable, Type
 
 from .instruction_set import InstructionSet, Instruction
 from riscemu.core import BaseFloat, CPU, INS_NOT_IMPLEMENTED, UInt32
@@ -8,7 +8,7 @@
 
 class FloatArithBase(Generic[_FloatT], InstructionSet):
     flen: ClassVar[int]
-    _float_cls: ClassVar[type[BaseFloat]]
+    _float_cls: ClassVar[Type[BaseFloat]]
 
     def __init__(self, cpu: CPU):
         assert cpu.regs.flen >= self.flen, "{} implies cpu flen of at least {}".format(