- Synopsis
-
Load indexed unsigned half-word, increment address before loading.
- Mnemonic
-
th.lhuib rd, (rs1), imm5, imm2
- Encoding
{reg:[ { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x4, attr: ['Mem-Load'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 'imm5' }, { bits: 2, name: 'imm2' }, { bits: 5, name: 0x15 }, ]}
- Description
-
This instruction increments the value in rs1 by (sign_extend(imm5) << imm2) and writes the result back to rs1. After the increment of rs1, this instruction loads a zero extended 16-bit value into the GP register rd from the (incremented) address rs1.
The values of rd and rs1 must not be the same.
- Operation
rs1 := rs1 + (sign_extend(imm5) << imm2)
rd := zero_extend(mem[rs1+1:rs1])
- Permission
-
This instruction can be executed in all privilege levels.
- Exceptions
-
This instruction triggers the same exceptions that a corresponding
LHU
instruction would trigger. - Included in
Extension |
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XTheadMemIdx ([xtheadmemidx]) |