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lrhu.adoc

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th.lrhu

Synopsis

Load indexed unsigned half-word.

Mnemonic

th.lrhu rd, rs1, rs2, imm2

Encoding
{reg:[
    { bits:  7, name: 0xb, attr: ['custom-0, 32 bit'] },
    { bits:  5, name: 'rd' },
    { bits:  3, name: 0x4, attr: ['Mem-Load'] },
    { bits:  5, name: 'rs1' },
    { bits:  5, name: 'rs2' },
    { bits:  2, name: 'imm2' },
    { bits:  5, name: 0x14 },
]}
Description

This instruction loads a zero extended 16-bit value into the GP register rd from the address rs1 + (rs2 << imm2).

Operation
addr := rs1 + (rs2 << imm2)
rd := zero_extend(mem[addr+1:addr])
Permission

This instruction can be executed in all privilege levels.

Exceptions

This instruction triggers the same exceptions that a corresponding LHU instruction would trigger.

Included in
Extension

XTheadMemIdx ([xtheadmemidx])