- Synopsis
-
Store unsigned indexed half-word.
- Mnemonic
-
th.surh rd, rs1, rs2, imm2
- Encoding
{reg:[
{ bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] },
{ bits: 5, name: 'rd' },
{ bits: 3, name: 0x5, attr: ['Mem-Store'] },
{ bits: 5, name: 'rs1' },
{ bits: 5, name: 'rs2' },
{ bits: 2, name: 'imm2' },
{ bits: 5, name: 0x06 },
]}
- Description
-
This instruction stores a 16-bit value from the GP register rd to the address rs1 + (zero_extend(rs2) << imm2).
Note, that this instruction is equivalent to a zext.w rs2, rs2 followed by a th.srh with the same arguments.
- Operation
addr := rs1 + (zero_extend(rs2) << imm2)
mem[addr+1:addr] := rd- Permission
-
This instruction can be executed in all privilege levels.
- Exceptions
-
This instruction triggers the same exceptions that a corresponding
SHinstruction would trigger. - Included in
| Extension |
|---|
XTheadMemIdx ([xtheadmemidx]) |