diff --git a/src/uvmgen/templates/env_pkg/adapter.mako.sv b/src/uvmgen/templates/agt_pkg/reg_adapter.mako.sv
similarity index 51%
rename from src/uvmgen/templates/env_pkg/adapter.mako.sv
rename to src/uvmgen/templates/agt_pkg/reg_adapter.mako.sv
index 3ca86b6..28c8a22 100644
--- a/src/uvmgen/templates/env_pkg/adapter.mako.sv
+++ b/src/uvmgen/templates/agt_pkg/reg_adapter.mako.sv
@@ -1,18 +1,18 @@
-`ifndef ${adapter_name.upper()}__SV
-`define ${adapter_name.upper()}__SV
+`ifndef ${agent_name.upper()}_REG_ADAPTER__SV
+`define ${agent_name.upper()}_REG_ADAPTER__SV
 
-class ${adapter_name} extends uvm_reg_adapter;
+class ${agent_name}_reg_adapter extends uvm_reg_adapter;
 
-`uvm_object_utils(${adapter_name})
+`uvm_object_utils(${agent_name}_reg_adapter)
 
- function new (string name="");
+ function new (string name="${agent_name}_reg_adapter");
    super.new(name);
  endfunction: new
 
  virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
-  ${reg_tr_name} tr;
-  tr = ${reg_tr_name}::type_id::create("tr"); 
-  tr.kind = (rw.kind == UVM_READ) ? ${reg_tr_name}::READ : ${reg_tr_name}::WRITE; 
+  ${agent_name}_item tr;
+  tr = ${agent_name}_item::type_id::create("tr"); 
+  tr.kind = (rw.kind == UVM_READ) ? ${agent_name}_item::READ : ${agent_name}_item::WRITE; 
   //  tr.addr = rw.addr;
   //  tr.data = rw.data;
   return tr;
@@ -20,7 +20,7 @@ class ${adapter_name} extends uvm_reg_adapter;
 
  virtual function void bus2reg (uvm_sequence_item bus_item,
                                 ref uvm_reg_bus_op rw);
-  ${reg_tr_name} tr;
+  ${agent_name}_item tr;
   if (!$cast(tr, bus_item))
    `uvm_fatal("NOT_HOST_REG_TYPE", "bus_item is not correct type");
   rw.kind = tr.kind ? UVM_READ : UVM_WRITE;
@@ -29,6 +29,6 @@ class ${adapter_name} extends uvm_reg_adapter;
   //  rw.status = UVM_IS_OK;
  endfunction: bus2reg
 
-endclass: ${adapter_name}
+endclass: ${agent_name}_reg_adapter
 
-`endif // ${adapter_name.upper()}__SV
+`endif // ${agent_name.upper()}_REG_ADAPTER__SV
diff --git a/src/uvmgen/templates/env_pkg/env.mako.sv b/src/uvmgen/templates/env_pkg/env.mako.sv
index db1cda0..de13ab1 100644
--- a/src/uvmgen/templates/env_pkg/env.mako.sv
+++ b/src/uvmgen/templates/env_pkg/env.mako.sv
@@ -5,10 +5,10 @@ typedef class ${vsqr_name};
 // typedef class {reg_name};
 class ${env_name} extends uvm_env;
    ${scb_name} scb;
-% if has_regmodle:  
-   ral_block_VNAME regmodel;
+% if has_regmodel:  
+   ${ral_block_name} regmodel;
    reg_seq ral_sequence; 
-   REGTR regv 2host;
+   ${}_reg_adapter m_${}_reg_adapter;
 % endif
    ${vsqr_name} vsqr;
    // Declear agent
@@ -46,11 +46,9 @@ function void ${env_name}::build_phase(uvm_phase phase);
    vsqr = ${vsqr_name}::type_id::create("vsqr",this);
    //ToDo: Instantiate other components,callbacks and TLM ports if added by user  
 
-% if has_regmodle:  
    scb = ${scb_name}::type_id::create("scb",this);
-% endif
-% if has_regmodle:  
-   regmodel = ral_block_VNAME::type_id::create("regmodel",this);
+% if has_regmodel:  
+   regmodel = ${ral_block_name}::type_id::create("regmodel",this);
    regmodel.build();
    ral_sequence = reg_seq::type_id::create("ral_sequence");
    ral_sequence.model = regmodel; 
@@ -61,7 +59,7 @@ endfunction: build_phase
 function void ${env_name}::connect_phase(uvm_phase phase);
    super.connect_phase(phase);
 
-% if has_regmodle:  
+% if has_regmodel:  
    regmodel.default_map.set_sequencer(mast_seqr,reg2host);
    MULT_DRV_START
    regmodel.default_map.set_sequencer(mast_seqr_0,reg2host);
diff --git a/src/uvmgen/templates/env_pkg/vsqr.mako.sv b/src/uvmgen/templates/env_pkg/vsqr.mako.sv
index e6073f6..431814d 100644
--- a/src/uvmgen/templates/env_pkg/vsqr.mako.sv
+++ b/src/uvmgen/templates/env_pkg/vsqr.mako.sv
@@ -1,3 +1,6 @@
+`ifndef ${vsqr_name.upper()}__SV
+`define ${vsqr_name.upper()}__SV
+
 class ${vsqr_name} extends uvm_sequencer;
 % for child_name, child_type in env_childs.items():
     ${child_type[:-3]}sqr ${child_name[:-3]}sqr;
@@ -11,4 +14,5 @@ class ${vsqr_name} extends uvm_sequencer;
 
     `uvm_new_func
 
-endclass
\ No newline at end of file
+endclass
+`endif // ${vsqr_name.upper()}__SV
\ No newline at end of file
diff --git a/src/uvmgen/templates/ral_pkg/ral_pkg.mako.sv b/src/uvmgen/templates/ral_pkg/ral_pkg.mako.sv
new file mode 100644
index 0000000..0454e49
--- /dev/null
+++ b/src/uvmgen/templates/ral_pkg/ral_pkg.mako.sv
@@ -0,0 +1,16 @@
+// Please generate this file using the peakrdl-uvm tool.
+package ral_pkg;
+
+    `include "uvm_macros.svh"
+    import uvm_pkg::*;
+
+    class empty_reg_block extends uvm_reg_block;
+
+        `uvm_object_utils(empty_reg_block)
+        function new(string name = "empty_reg_block");
+            super.new(name); 
+        endfunction
+
+    endclass
+
+endpackage
diff --git a/src/uvmgen/templates/seq_lib_pkg/base_seq.mako.sv b/src/uvmgen/templates/seq_lib_pkg/base_seq.mako.sv
index 25358cf..354fc21 100644
--- a/src/uvmgen/templates/seq_lib_pkg/base_seq.mako.sv
+++ b/src/uvmgen/templates/seq_lib_pkg/base_seq.mako.sv
@@ -4,7 +4,7 @@
 class ${seq_lib_name}_base_seq extends uvm_sequence #(uvm_sequence_item);
 
     `uvm_object_utils(${seq_lib_name}_base_seq)
-    function new (string name);
+    function new (string name = "${seq_lib_name}_base_seq");
       super.new(name);
     endfunction : new
 
diff --git a/src/uvmgen/templates/seq_lib_pkg/seq.mako.sv b/src/uvmgen/templates/seq_lib_pkg/seq.mako.sv
index 24c5229..71b7aff 100644
--- a/src/uvmgen/templates/seq_lib_pkg/seq.mako.sv
+++ b/src/uvmgen/templates/seq_lib_pkg/seq.mako.sv
@@ -6,7 +6,7 @@ class ${seq_name} extends ${seq_lib_name}_base_seq;
   `uvm_object_utils(${seq_name})
   `uvm_add_to_seq_lib(${seq_name}, ${seq_lib_name})
 
-  function new(string name);
+  function new(string name = "${seq_name}");
     super.new(name);
   endfunction: new
 
diff --git a/src/uvmgen/templates/tb_lib/tb.mako.sv b/src/uvmgen/templates/tb_lib/tb.mako.sv
index 0c06f72..6fd04bd 100644
--- a/src/uvmgen/templates/tb_lib/tb.mako.sv
+++ b/src/uvmgen/templates/tb_lib/tb.mako.sv
@@ -8,27 +8,9 @@ module tb();
     import ${pkg}::*;
 % endfor
 
-    typedef virtual ${if_name} vif;
-    ${if_name} mst_if(clk, rst_n);
-    ${if_name} slv_if(clk, rst_n);
-    ${if_name} ctrl_if(clk, rst_n);
-
-    // ToDo: Include Dut instance here
-    // dut my_dut(.clk          (clk               ),
-    //        .rst_n        (rst_n             ),
-    //        .bus_cmd_valid(b_if.bus_cmd_valid), 
-    //        .bus_op       (b_if.bus_op       ), 
-    //        .bus_addr     (b_if.bus_addr     ), 
-    //        .bus_wr_data  (b_if.bus_wr_data  ), 
-    //        .bus_rd_data  (b_if.bus_rd_data  ), 
-    //        .rxd          (input_if.data     ),
-    //        .rx_dv        (input_if.valid    ),
-    //        .txd          (output_if.data    ),
-    //        .tx_en        (output_if.valid   ));
-
     // Clock Generation
     int period = 10;
-    logic clk = 1'b0;
+    reg clk = 1'b0;
     always begin
       uvm_config_db#(int)::wait_modified(null, "*","period");
       void'(uvm_config_db#(int)::get(null, "", "period", period));
@@ -37,13 +19,31 @@ module tb();
 
     // Reset Delay Parameter
     int rst_delay = 50;
-    logic rst_n = 1'b0;
+    reg rst_n = 1'b0;
     always begin
       uvm_config_db#(int)::wait_modified(null, "*","rst_delay");
       void'(uvm_config_db#(int)::get(null, "", "rst_delay", rst_delay));
     end
     initial #(rst_delay) rst_n = 1'b1;
 
+    // ToDo: Include Dut instance here
+    // dut my_dut(.clk          (clk               ),
+    //        .rst_n        (rst_n             ),
+    //        .bus_cmd_valid(b_if.bus_cmd_valid), 
+    //        .bus_op       (b_if.bus_op       ), 
+    //        .bus_addr     (b_if.bus_addr     ), 
+    //        .bus_wr_data  (b_if.bus_wr_data  ), 
+    //        .bus_rd_data  (b_if.bus_rd_data  ), 
+    //        .rxd          (input_if.data     ),
+    //        .rx_dv        (input_if.valid    ),
+    //        .txd          (output_if.data    ),
+    //        .tx_en        (output_if.valid   ));
+
+    typedef virtual ${if_name} vif;
+    ${if_name} mst_if(clk, rst_n);
+    ${if_name} slv_if(clk, rst_n);
+    ${if_name} ctrl_if(clk, rst_n);
+
     initial begin
         uvm_config_db# (vif)::set(null,"*","if",mst_if);
         run_test();
diff --git a/test/json/env.json b/test/json/env.json
index 231fa47..0cb300a 100644
--- a/test/json/env.json
+++ b/test/json/env.json
@@ -12,8 +12,6 @@
             "mst_action": "spi_item",
             "slv_action": "spi_item",
             "scb_item": "spi_item",
-            "adapter_name": "spi_adapter",
-            "reg_tr_name": "spi_item",
             "mon2cov_con_approach": "analysis_port"
         }
     }
diff --git a/test/json/ral.json b/test/json/ral.json
new file mode 100644
index 0000000..c4e28db
--- /dev/null
+++ b/test/json/ral.json
@@ -0,0 +1,9 @@
+{
+    "spi_ral_pkg": {
+        "description": "SPI ral package",
+        "type": "ral_pkg",
+        "vars": {
+            "pkg_name": "spi_ral_pkg"
+        }
+    }
+}
\ No newline at end of file
diff --git a/test/json/tb.json b/test/json/tb.json
index 1b98d09..f3c91d6 100644
--- a/test/json/tb.json
+++ b/test/json/tb.json
@@ -6,7 +6,7 @@
             "pkg_name": "spi_tb_lib",
             "import_pkgs":["spi_test_pkg"],
             "if_name": "spi_if",
-            "filelist_pkgs":["spi_agt_pkg", "spi_env_pkg", "spi_seq_lib_pkg", "spi_test_pkg", "spi_tb_lib"]
+            "filelist_pkgs":["spi_agt_pkg", "spi_ral_pkg", "spi_env_pkg", "spi_seq_lib_pkg", "spi_test_pkg", "spi_tb_lib"]
 
         }
     }
diff --git a/test/test_seq_lib.py b/test/test_base.py
similarity index 85%
rename from test/test_seq_lib.py
rename to test/test_base.py
index d89e426..7d24267 100644
--- a/test/test_seq_lib.py
+++ b/test/test_base.py
@@ -1,10 +1,13 @@
 from uvmgen.uvmgen import uvm_gen
 
+def test_agt():
+    uvm_gen().gen("test/json/agt.json")
+
 def test_seq_lib():
     uvm_gen().gen("test/json/seq_lib.json")
 
-def test_agt():
-    uvm_gen().gen("test/json/agt.json")
+def test_ral():
+    uvm_gen().gen("test/json/ral.json")
 
 def test_env():
     uvm_gen().gen("test/json/env.json")