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Cirrus.cpp
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Cirrus.cpp
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/* ES40 emulator.
* Copyright (C) 2007-2008 by the ES40 Emulator Project
*
* WWW : http://sourceforge.net/projects/es40
* E-mail : [email protected]
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*
* Although this is not required, the author would appreciate being notified of,
* and receiving any modifications you may make to the source code that might serve
* the general public.
*/
/**
* \file
* Contains the code for the emulated Cirrus CL GD-5434 Video Card device.
*
* $Id: Cirrus.cpp,v 1.14 2008/02/27 12:04:21 iamcamiel Exp $
*
* X-1.14 Brian Wheeler 27-FEB-2008
* Avoid compiler warnings.
*
* X-1.13 David Leonard 20-FEB-2008
* Shut down refresh thread when emulator exits.
*
* X-1.12 David Leonard 20-FEB-2008
* Avoid 'Xlib: unexpected async reply' errors on Linux/Unix/BSD's by
* adding some thread interlocking.
*
* X-1.11 Camiel Vanderhoeven 03-JAN-2008
* Attempt to get this working for big-endian host architectures.
*
* X-1.10 Camiel Vanderhoeven 02-JAN-2008
* Cleanup.
*
* X-1.9 Camiel Vanderhoeven 30-DEC-2007
* Print file id on initialization.
*
* X-1.8 Camiel Vanderhoeven 28-DEC-2007
* Throw exceptions rather than just exiting when errors occur.
*
* X-1.7 Camiel Vanderhoeven 28-DEC-2007
* Keep the compiler happy.
*
* X-1.6 Camiel Vanderhoeven 17-DEC-2007
* SaveState file format 2.1
*
* X-1.5 Camiel Vabderhoeven 11-DEC-2007
* Don't claim IO addresses 3d0..3d3, 3d6..3d9 and 3db..3df.
*
* X-1.4 Camiel Vabderhoeven 11-DEC-2007
* Don't claim IO addresses 3b0..3b3, 3b6..3b9 and 3bb.
*
* X-1.3 Brian Wheeler 10-DEC-2007
* Made refresh function name unique.
*
* X-1.2 Camiel Vanderhoeven 10-DEC-2007
* Don't decode IO addresses 3bc-3bf.
*
* X-1.1 Camiel Vanderhoeven 10-DEC-2007
* Initial version in CVS.
**/
#include "StdAfx.h"
#include "Cirrus.h"
#include "System.h"
#include "AliM1543C.h"
#include "gui/gui.h"
#define VGA_TRACE_FEATURE 1
unsigned old_iHeight = 0, old_iWidth = 0, old_MSL = 0;
static const u8 ccdat[16][4] = {
{ 0x00, 0x00, 0x00, 0x00 },
{ 0xff, 0x00, 0x00, 0x00 },
{ 0x00, 0xff, 0x00, 0x00 },
{ 0xff, 0xff, 0x00, 0x00 },
{ 0x00, 0x00, 0xff, 0x00 },
{ 0xff, 0x00, 0xff, 0x00 },
{ 0x00, 0xff, 0xff, 0x00 },
{ 0xff, 0xff, 0xff, 0x00 },
{ 0x00, 0x00, 0x00, 0xff },
{ 0xff, 0x00, 0x00, 0xff },
{ 0x00, 0xff, 0x00, 0xff },
{ 0xff, 0xff, 0x00, 0xff },
{ 0x00, 0x00, 0xff, 0xff },
{ 0xff, 0x00, 0xff, 0xff },
{ 0x00, 0xff, 0xff, 0xff },
{ 0xff, 0xff, 0xff, 0xff },
};
// Only reference the array if the tile numbers are within the bounds
// of the array. If out of bounds, do nothing.
#define SET_TILE_UPDATED(xtile,ytile,value) \
do { \
if (((xtile) < BX_NUM_X_TILES) && ((ytile) < BX_NUM_Y_TILES)) \
state.vga_tile_updated[(xtile)][(ytile)] = value; \
} while (0)
// Only reference the array if the tile numbers are within the bounds
// of the array. If out of bounds, return 0.
#define GET_TILE_UPDATED(xtile,ytile) \
((((xtile) < BX_NUM_X_TILES) && ((ytile) < BX_NUM_Y_TILES))? \
state.vga_tile_updated[(xtile)][(ytile)] \
: 0)
static volatile bool refresh_stopped = false;
#if defined(_WIN32)
static HANDLE screen_refresh_handle_cirrus;
static DWORD WINAPI refresh_proc_cirrus(LPVOID lpParam)
#else
pthread_t screen_refresh_handle_cirrus;
static void *refresh_proc_cirrus(void *lpParam)
#endif
{
CCirrus *c = (CCirrus *) lpParam;
while(1) {
bx_gui->lock();
if (refresh_stopped) {
bx_gui->unlock();
break;
}
c->update();
bx_gui->flush();
bx_gui->unlock();
sleep_ms(100); // 10 fps
}
return 0;
}
static void refresh_stop()
{
bx_gui->lock();
refresh_stopped = 1;
bx_gui->unlock();
}
static unsigned int rom_max;
static u8 option_rom[65536];
static u32 cirrus_cfg_data[64] = {
/*00*/ 0x00a81013, // CFID: vendor + device
/*04*/ 0x011f0000, // CFCS: command + status
/*08*/ 0x03000002, // CFRV: class + revision
/*0c*/ 0x00000000, // CFLT: latency timer + cache line size
/*10*/ 0xf8000000, // BAR0: FB
/*14*/ 0x00000000, // BAR1:
/*18*/ 0x00000000, // BAR2:
/*1c*/ 0x00000000, // BAR3:
/*20*/ 0x00000000, // BAR4:
/*24*/ 0x00000000, // BAR5:
/*28*/ 0x00000000, // CCIC: CardBus
/*2c*/ 0x00000000, // CSID: subsystem + vendor
/*30*/ 0x00000000, // BAR6: expansion rom base
/*34*/ 0x00000000, // CCAP: capabilities pointer
/*38*/ 0x00000000,
/*3c*/ 0x281401ff, // CFIT: interrupt configuration
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
};
static u32 cirrus_cfg_mask[64] = {
/*00*/ 0x00000000, // CFID: vendor + device
/*04*/ 0x0000ffff, // CFCS: command + status
/*08*/ 0x00000000, // CFRV: class + revision
/*0c*/ 0x0000ffff, // CFLT: latency timer + cache line size
/*10*/ 0xfc000000, // BAR0: FB
/*14*/ 0x00000000, // BAR1:
/*18*/ 0x00000000, // BAR2:
/*1c*/ 0x00000000, // BAR3:
/*20*/ 0x00000000, // BAR4:
/*24*/ 0x00000000, // BAR5:
/*28*/ 0x00000000, // CCIC: CardBus
/*2c*/ 0x00000000, // CSID: subsystem + vendor
/*30*/ 0x00000000, // BAR6: expansion rom base
/*34*/ 0x00000000, // CCAP: capabilities pointer
/*38*/ 0x00000000,
/*3c*/ 0x000000ff, // CFIT: interrupt configuration
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
};
/**
* Constructor.
**/
CCirrus::CCirrus(CConfigurator * cfg, CSystem * c, int pcibus, int pcidev): CVGA(cfg,c,pcibus,pcidev)
{
add_function(0,cirrus_cfg_data,cirrus_cfg_mask);
int i;
c->RegisterClock(this, true);
/* the VGA I/O ports are at 3b4, 3b5, 3ba and 3c0 -> 3cf, 3d4, 3d5, 3da */
add_legacy_io(1,0x3b4,2);
add_legacy_io(3,0x3ba,2);
add_legacy_io(2,0x3c0,16);
add_legacy_io(8,0x3d4,2);
add_legacy_io(9,0x3da,1);
/* we listen for messages from outer space (a.k.a. VGA bios) at port 500. */
add_legacy_io(7,0x500,1);
/* legacy video address space: A0000 -> bffff */
add_legacy_mem(4,0xa0000,128*1024);
ResetPCI();
bios_message_size = 0;
bios_message[0] = '\0';
// use a VGA rom from bochs
FILE *rom=fopen(myCfg->get_text_value("rom","vgabios.bin"),"rb");
if(!rom) {
printf("%%VGA-F-ROM: Cannot load rom '%s'\n",myCfg->get_text_value("rom","vgabios.bin"));
throw((int)1);
}
rom_max=(unsigned)fread(option_rom,1,65536,rom);
fclose(rom);
printf("%%VGA-I-ROMSIZE: ROM is %d bytes.\n",rom_max);
/* Option ROM address space: C0000 */
add_legacy_mem(5,0xc0000,rom_max);
state.vga_enabled = 1;
state.misc_output.color_emulation = 1;
state.misc_output.enable_ram = 1;
state.misc_output.clock_select = 0;
state.misc_output.select_high_bank = 0;
state.misc_output.horiz_sync_pol = 1;
state.misc_output.vert_sync_pol = 1;
state.attribute_ctrl.mode_ctrl.graphics_alpha = 0;
state.attribute_ctrl.mode_ctrl.display_type = 0;
state.attribute_ctrl.mode_ctrl.enable_line_graphics = 1;
state.attribute_ctrl.mode_ctrl.blink_intensity = 0;
state.attribute_ctrl.mode_ctrl.pixel_panning_compat = 0;
state.attribute_ctrl.mode_ctrl.pixel_clock_select = 0;
state.attribute_ctrl.mode_ctrl.internal_palette_size = 0;
state.line_offset=80;
state.line_compare=1023;
state.vertical_display_end=399;
for (i=0; i<=0x18; i++)
state.CRTC.reg[i] = 0;
state.CRTC.address = 0;
state.CRTC.write_protect = 0;
state.attribute_ctrl.flip_flop = 0;
state.attribute_ctrl.address = 0;
state.attribute_ctrl.video_enabled = 1;
for (i=0; i<16; i++)
state.attribute_ctrl.palette_reg[i] = 0;
state.attribute_ctrl.overscan_color = 0;
state.attribute_ctrl.color_plane_enable = 0x0f;
state.attribute_ctrl.horiz_pel_panning = 0;
state.attribute_ctrl.color_select = 0;
for (i=0; i<256; i++) {
state.pel.data[i].red = 0;
state.pel.data[i].green = 0;
state.pel.data[i].blue = 0;
}
state.pel.write_data_register = 0;
state.pel.write_data_cycle = 0;
state.pel.read_data_register = 0;
state.pel.read_data_cycle = 0;
state.pel.dac_state = 0x01;
state.pel.mask = 0xff;
state.graphics_ctrl.index = 0;
state.graphics_ctrl.set_reset = 0;
state.graphics_ctrl.enable_set_reset = 0;
state.graphics_ctrl.color_compare = 0;
state.graphics_ctrl.data_rotate = 0;
state.graphics_ctrl.raster_op = 0;
state.graphics_ctrl.read_map_select = 0;
state.graphics_ctrl.write_mode = 0;
state.graphics_ctrl.read_mode = 0;
state.graphics_ctrl.odd_even = 0;
state.graphics_ctrl.chain_odd_even = 0;
state.graphics_ctrl.shift_reg = 0;
state.graphics_ctrl.graphics_alpha = 0;
state.graphics_ctrl.memory_mapping = 2; // monochrome text mode
state.graphics_ctrl.color_dont_care = 0;
state.graphics_ctrl.bitmask = 0;
for (i=0; i<4; i++) {
state.graphics_ctrl.latch[i] = 0;
}
state.sequencer.index = 0;
state.sequencer.map_mask = 0;
state.sequencer.reset1 = 1;
state.sequencer.reset2 = 1;
state.sequencer.reg1 = 0;
state.sequencer.char_map_select = 0;
state.sequencer.extended_mem = 1; // display mem greater than 64K
state.sequencer.odd_even = 1; // use sequential addressing mode
state.sequencer.chain_four = 0; // use map mask & read map select
//extname = SIM->get_param_string(BXPN_VGA_EXTENSION)->getptr();
//if ((strlen(extname) == 0) || (!strcmp(extname, "none"))) {
state.memsize = 0x40000;
state.memory = new u8[state.memsize];
memset(state.memory, 0, state.memsize);
//}
state.vga_mem_updated = 0;
for (unsigned y=0; y<480/Y_TILESIZE; y++)
for (unsigned x=0; x<640/X_TILESIZE; x++)
SET_TILE_UPDATED (x, y, 0);
bx_gui->init(state.x_tilesize, state.y_tilesize);
#if !BX_SUPPORT_CLGD54XX
// this->init_systemtimer(timer_handler, vga_param_handler);
#endif // !BX_SUPPORT_CLGD54XX
state.charmap_address = 0;
state.x_dotclockdiv2 = 0;
state.y_doublescan = 0;
state.last_bpp = 8;
#if BX_SUPPORT_VBE
// The following is for the vbe display extension
state.vbe_enabled=0;
state.vbe_8bit_dac=0;
if (!strcmp(extname, "vbe")) {
for (addr=VBE_DISPI_IOPORT_INDEX; addr<=VBE_DISPI_IOPORT_DATA; addr++) {
DEV_register_ioread_handler(this, vbe_read_handler, addr, "vga video", 7);
DEV_register_iowrite_handler(this, vbe_write_handler, addr, "vga video", 7);
}
if (!BX_SUPPORT_PCIUSB || !SIM->get_param_bool(BXPN_USB1_ENABLED)->get()) {
for (addr=VBE_DISPI_IOPORT_INDEX_OLD; addr<=VBE_DISPI_IOPORT_DATA_OLD; addr++) {
DEV_register_ioread_handler(this, vbe_read_handler, addr, "vga video", 7);
DEV_register_iowrite_handler(this, vbe_write_handler, addr, "vga video", 7);
}
}
DEV_register_memory_handlers(theVga, mem_read_handler, mem_write_handler,
VBE_DISPI_LFB_PHYSICAL_ADDRESS,
VBE_DISPI_LFB_PHYSICAL_ADDRESS + VBE_DISPI_TOTAL_VIDEO_MEMORY_BYTES - 1);
if (state.memory == NULL)
state.memory = new u8[VBE_DISPI_TOTAL_VIDEO_MEMORY_BYTES];
memset(state.memory, 0, VBE_DISPI_TOTAL_VIDEO_MEMORY_BYTES);
state.memsize = VBE_DISPI_TOTAL_VIDEO_MEMORY_BYTES;
state.vbe_cur_dispi=VBE_DISPI_ID0;
state.vbe_xres=640;
state.vbe_yres=480;
state.vbe_bpp=8;
state.vbe_bank=0;
state.vbe_curindex=0;
state.vbe_offset_x=0;
state.vbe_offset_y=0;
state.vbe_virtual_xres=640;
state.vbe_virtual_yres=480;
state.vbe_bpp_multiplier=1;
state.vbe_virtual_start=0;
state.vbe_lfb_enabled=0;
state.vbe_get_capabilities=0;
bx_gui->get_capabilities(&max_xres, &max_yres,
&max_bpp);
if (max_xres > VBE_DISPI_MAX_XRES) {
state.vbe_max_xres=VBE_DISPI_MAX_XRES;
} else {
state.vbe_max_xres=max_xres;
}
if (max_yres > VBE_DISPI_MAX_YRES) {
state.vbe_max_yres=VBE_DISPI_MAX_YRES;
} else {
state.vbe_max_yres=max_yres;
}
if (max_bpp > VBE_DISPI_MAX_BPP) {
state.vbe_max_bpp=VBE_DISPI_MAX_BPP;
} else {
state.vbe_max_bpp=max_bpp;
}
this->extension_init = 1;
BX_INFO(("VBE Bochs Display Extension Enabled"));
}
#endif
state.CRTC.reg[0x09] = 16;
state.graphics_ctrl.memory_mapping = 3; // color text mode
state.vga_mem_updated = 1;
#if defined(_WIN32)
screen_refresh_handle_cirrus = CreateThread(NULL,0,refresh_proc_cirrus,this,0,NULL);
#else
pthread_create(&screen_refresh_handle_cirrus,NULL,refresh_proc_cirrus,this);
#endif
printf("%s: $Id: Cirrus.cpp,v 1.14 2008/02/27 12:04:21 iamcamiel Exp $\n",devid_string);
}
CCirrus::~CCirrus()
{
refresh_stop();
printf("%%VGA-I-SHUTDOWN: vga console has shut down.\n");
}
u32 CCirrus::ReadMem_Legacy(int index, u32 address, int dsize)
{
switch(index)
{
case 1: /* io ports */
return io_read(address+0x3b4, dsize);
case 2: /* io ports */
return io_read(address+0x3c0, dsize);
case 3: /* io ports */
return io_read(address+0x3ba, dsize);
case 4: /* legacy memory */
return legacy_read(address, dsize);
case 5: /* rom */
case 6:
return rom_read(address, dsize);
case 8: /* io ports */
return io_read(address+0x3d4, dsize);
case 9: /* io ports */
return io_read(address+0x3da, dsize);
}
return 0;
}
void CCirrus::WriteMem_Legacy(int index, u32 address, int dsize, u32 data)
{
switch(index)
{
case 1: /* io port */
io_write(address+0x3b4,dsize,data);
return;
case 2: /* io port */
io_write(address+0x3c0,dsize,data);
return;
case 3: /* io port */
io_write(address+0x3ba,dsize,data);
return;
case 4: /* legacy memory */
legacy_write(address,dsize,data);
return;
case 7: /* bios message */
bios_message[bios_message_size++] = (char) data & 0xff;
if (((data & 0xff) == 0x0a) || ((data &0xff) == 0x0d))
{
if (bios_message_size>1)
{
bios_message[bios_message_size-1] = '\0';
printf("%%VGA-I-BIOS: %s\n",bios_message);
}
bios_message_size = 0;
}
return;
case 8: /* io port */
io_write(address+0x3d4,dsize,data);
return;
case 9: /* io port */
io_write(address+0x3da,dsize,data);
return;
}
}
u32 CCirrus::ReadMem_Bar(int func, int bar, u32 address, int dsize)
{
switch(bar)
{
case 0: /* pci memory */
return mem_read(address, dsize);
}
return 0;
}
void CCirrus::WriteMem_Bar(int func, int bar, u32 address, int dsize, u32 data)
{
switch(bar)
{
case 0: /* pci memory */
mem_write(address,dsize,data);
return;
}
}
/**
* Redraw the screen.
**/
int CCirrus::DoClock()
{
return 0;
}
static u32 cirrus_magic1 = 0xC1AA4500;
static u32 cirrus_magic2 = 0x0054AA1C;
/**
* Save state to a Virtual Machine State file.
**/
int CCirrus::SaveState(FILE *f)
{
long ss = sizeof(state);
int res;
if (res = CPCIDevice::SaveState(f))
return res;
fwrite(&cirrus_magic1,sizeof(u32),1,f);
fwrite(&ss,sizeof(long),1,f);
fwrite(&state,sizeof(state),1,f);
fwrite(&cirrus_magic2,sizeof(u32),1,f);
printf("%s: %d bytes saved.\n",devid_string,(int)ss);
return 0;
}
/**
* Restore state from a Virtual Machine State file.
**/
int CCirrus::RestoreState(FILE *f)
{
long ss;
u32 m1;
u32 m2;
int res;
size_t r;
if (res = CPCIDevice::RestoreState(f))
return res;
r = fread(&m1,sizeof(u32),1,f);
if (r!=1)
{
printf("%s: unexpected end of file!\n",devid_string);
return -1;
}
if (m1 != cirrus_magic1)
{
printf("%s: MAGIC 1 does not match!\n",devid_string);
return -1;
}
fread(&ss,sizeof(long),1,f);
if (r!=1)
{
printf("%s: unexpected end of file!\n",devid_string);
return -1;
}
if (ss != sizeof(state))
{
printf("%s: STRUCT SIZE does not match!\n",devid_string);
return -1;
}
fread(&state,sizeof(state),1,f);
if (r!=1)
{
printf("%s: unexpected end of file!\n",devid_string);
return -1;
}
r = fread(&m2,sizeof(u32),1,f);
if (r!=1)
{
printf("%s: unexpected end of file!\n",devid_string);
return -1;
}
if (m2 != cirrus_magic2)
{
printf("%s: MAGIC 1 does not match!\n",devid_string);
return -1;
}
printf("%s: %d bytes restored.\n",devid_string,(int)ss);
return 0;
}
/**
* Read from Framebuffer
*/
u32 CCirrus::mem_read(u32 address, int dsize)
{
u32 data = 0;
//printf("S3 mem read: %" LL "x, %d, %" LL "x \n", address, dsize, data);
return data;
}
/**
* Write to Framebuffer
*/
void CCirrus::mem_write(u32 address, int dsize, u32 data)
{
//printf("S3 mem write: %" LL "x, %d, %" LL "x \n", address, dsize, data);
switch(dsize) {
case 8:
case 16:
case 32:
break;
}
}
/**
* Read from Legacy Framebuffer
*/
u32 CCirrus::legacy_read(u32 address, int dsize)
{
u32 data = 0;
switch (dsize)
{
case 32:
data |= (u64)vga_mem_read((u32)address + 0xA0003) << 24;
data |= (u64)vga_mem_read((u32)address + 0xA0002) << 16;
case 16:
data |= (u64)vga_mem_read((u32)address + 0xA0001) << 8;
case 8:
data |= (u64)vga_mem_read((u32)address + 0xA0000);
}
// //printf("S3 legacy read: %" LL "x, %d, %" LL "x \n", address, dsize, data);
return data;
}
/**
* Write to Legacy Framebuffer
*/
void CCirrus::legacy_write(u32 address, int dsize, u32 data)
{
// //printf("S3 legacy write: %" LL "x, %d, %" LL "x \n", address, dsize, data);
switch(dsize) {
case 32:
vga_mem_write((u32)address+0xA0002, (u8)(data>>16));
vga_mem_write((u32)address+0xA0003, (u8)(data>>24));
case 16:
vga_mem_write((u32)address+0xA0001, (u8)(data>>8));
case 8:
vga_mem_write((u32)address+0xA0000, (u8)(data));
}
}
/**
* Read from Option ROM
*/
u32 CCirrus::rom_read(u32 address, int dsize)
{
u32 data = 0x00;
u8 *x=(u8 *)option_rom;
if(address<= rom_max) {
x+=address;
switch (dsize)
{
case 8:
data = (u32) endian_8((*((u8*)x))&0xff);
break;
case 16:
data = (u32) endian_16((*((u16*)x))&0xffff);
break;
case 32:
data = (u32) endian_32((*((u32*)x))&0xffffffff);
break;
}
//printf("S3 rom read: %" LL "x, %d, %" LL "x\n", address, dsize,data);
} else {
printf("S3 (BAD) rom read: %" LL "x, %d, %" LL "x\n", address, dsize,data);
}
return data;
}
/**
* Read from I/O Port
*/
u32 CCirrus::io_read(u32 address, int dsize)
{
u32 data = 0;
if (dsize !=8)
FAILURE("Unsupported dsize!\n");
switch(address) {
case 0x3c0:
data = read_b_3c0();
break;
case 0x3c1:
data = read_b_3c1();
break;
case 0x3c2:
data = read_b_3c2();
break;
case 0x3c3:
data = read_b_3c3();
break;
case 0x3c4:
data = read_b_3c4();
break;
case 0x3c5:
data = read_b_3c5();
break;
case 0x3c9:
data = read_b_3c9();
break;
case 0x3ca:
data = read_b_3ca();
break;
case 0x3cc:
data = read_b_3cc();
break;
case 0x3cf:
data = read_b_3cf();
break;
case 0x3b4:
case 0x3d4:
data = read_b_3d4();
break;
case 0x3b5:
case 0x3d5:
data = read_b_3d5();
break;
case 0x3ba:
case 0x3da:
data = read_b_3da();
break;
default:
printf("%%VGA-W-PORT: Unhandled port %x read\n",address);
throw((int)1);
}
//printf("S3 io read: %" LL "x, %d, %" LL "x \n", address+VGA_BASE, dsize, data);
return data;
}
/**
* Write to I/O Port
*/
void CCirrus::io_write(u32 address, int dsize, u32 data)
{
// printf("S3 io write: %" LL "x, %d, %" LL "x \n", address+VGA_BASE, dsize, data);
switch(dsize)
{
case 8:
io_write_b(address,(u8)data);
break;
case 16:
io_write_b(address ,(u8) data);
io_write_b(address + 1,(u8)(data>>8));
break;
default:
FAILURE("Weird IO size!");
}
}
void CCirrus::io_write_b(u32 address, u8 data)
{
switch(address) {
case 0x3c0:
write_b_3c0(data);
break;
case 0x3c2:
write_b_3c2(data);
break;
case 0x3c4:
write_b_3c4(data);
break;
case 0x3c5:
write_b_3c5(data);
break;
case 0x3c6:
write_b_3c6(data);
break;
case 0x3c7:
write_b_3c7(data);
break;
case 0x3c8:
write_b_3c8(data);
break;
case 0x3c9:
write_b_3c9(data);
break;
case 0x3ce:
write_b_3ce(data);
break;
case 0x3cf:
write_b_3cf(data);
break;
case 0x3b4:
case 0x3d4:
write_b_3d4(data);
break;
case 0x3b5:
case 0x3d5:
write_b_3d5(data);
break;
default:
printf("%%VGA-W-PORT: Unhandled port %x write\n",address);
throw((int)1);
}
}
void CCirrus::write_b_3c0(u8 value)
{
bool prev_video_enabled, prev_line_graphics, prev_int_pal_size;
/* Attribute Controller */
if (state.attribute_ctrl.flip_flop == 0)
{ /* address mode */
prev_video_enabled = state.attribute_ctrl.video_enabled;
state.attribute_ctrl.video_enabled = (value >> 5) & 0x01;
#if defined(DEBUG_VGA)
printf("io write 3c0: video_enabled = %u \n", (unsigned) state.attribute_ctrl.video_enabled);
#endif
if (state.attribute_ctrl.video_enabled == 0)
{
bx_gui->lock();
bx_gui->clear_screen();
bx_gui->unlock();
}
else if (!prev_video_enabled) {
#if defined(DEBUG_VGA)
printf("found enable transition \n");
#endif
redraw_area(0, 0, old_iWidth, old_iHeight);
}
value &= 0x1f; /* address = bits 0..4 */
state.attribute_ctrl.address = value;
switch (value) {
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x04: case 0x05: case 0x06: case 0x07:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0c: case 0x0d: case 0x0e: case 0x0f:
break;
#if defined(DEBUG_VGA)
default:
printf("io write 3c0: address mode reg=%u \n",(unsigned) value);
#endif
}
}
else { /* data-write mode */
switch (state.attribute_ctrl.address) {
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x04: case 0x05: case 0x06: case 0x07:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0c: case 0x0d: case 0x0e: case 0x0f:
if (value != state.attribute_ctrl.palette_reg[state.attribute_ctrl.address]) {
state.attribute_ctrl.palette_reg[state.attribute_ctrl.address] = value;
redraw_area(0, 0, old_iWidth, old_iHeight);
}
break;
case 0x10: // mode control register
prev_line_graphics = state.attribute_ctrl.mode_ctrl.enable_line_graphics;
prev_int_pal_size = state.attribute_ctrl.mode_ctrl.internal_palette_size;
state.attribute_ctrl.mode_ctrl.graphics_alpha =
(value >> 0) & 0x01;
state.attribute_ctrl.mode_ctrl.display_type =
(value >> 1) & 0x01;
state.attribute_ctrl.mode_ctrl.enable_line_graphics =
(value >> 2) & 0x01;
state.attribute_ctrl.mode_ctrl.blink_intensity =
(value >> 3) & 0x01;
state.attribute_ctrl.mode_ctrl.pixel_panning_compat =
(value >> 5) & 0x01;
state.attribute_ctrl.mode_ctrl.pixel_clock_select =
(value >> 6) & 0x01;
state.attribute_ctrl.mode_ctrl.internal_palette_size =
(value >> 7) & 0x01;
if (((value >> 2) & 0x01) != prev_line_graphics) {
bx_gui->lock();
bx_gui->set_text_charmap( & state.memory[0x20000 + state.charmap_address]);
bx_gui->unlock();
state.vga_mem_updated = 1;
}
if (((value >> 7) & 0x01) != prev_int_pal_size) {
redraw_area(0, 0, old_iWidth, old_iHeight);
}
#if defined(DEBUG_VGA)
printf("io write 3c0: mode control: %02x h \n", (unsigned) value);
#endif
break;
case 0x11: // Overscan Color Register
state.attribute_ctrl.overscan_color = (value & 0x3f);
#if defined(DEBUG_VGA)
printf("io write 3c0: overscan color = %02x \n",
(unsigned) value);
#endif
break;
case 0x12: // Color Plane Enable Register
state.attribute_ctrl.color_plane_enable = (value & 0x0f);
redraw_area(0, 0, old_iWidth, old_iHeight);
#if defined(DEBUG_VGA)
printf("io write 3c0: color plane enable = %02x \n",
(unsigned) value);
#endif
break;
case 0x13: // Horizontal Pixel Panning Register
state.attribute_ctrl.horiz_pel_panning = (value & 0x0f);
redraw_area(0, 0, old_iWidth, old_iHeight);
#if defined(DEBUG_VGA)
printf("io write 3c0: horiz pel panning = %02x \n",
(unsigned) value);
#endif
break;
case 0x14: // Color Select Register
state.attribute_ctrl.color_select = (value & 0x0f);
redraw_area(0, 0, old_iWidth, old_iHeight);
#if defined(DEBUG_VGA)
printf("io write 3c0: color select = %02x \n",
(unsigned) state.attribute_ctrl.color_select);
#endif
break;
default:
printf("io write 3c0: data-write mode %02x h \n",(unsigned) state.attribute_ctrl.address);
throw((int)1);
}
}
state.attribute_ctrl.flip_flop = !state.attribute_ctrl.flip_flop;
}
void CCirrus::write_b_3c2(u8 value)
{
/* Miscellaneous Output Register */
state.misc_output.color_emulation = (value >> 0) & 0x01;
state.misc_output.enable_ram = (value >> 1) & 0x01;
state.misc_output.clock_select = (value >> 2) & 0x03;
state.misc_output.select_high_bank = (value >> 5) & 0x01;
state.misc_output.horiz_sync_pol = (value >> 6) & 0x01;
state.misc_output.vert_sync_pol = (value >> 7) & 0x01;
#if defined(DEBUG_VGA)
printf("io write 3c2: \n");
printf(" color_emulation = %u \n", (unsigned) state.misc_output.color_emulation);
printf(" enable_ram = %u \n",(unsigned) state.misc_output.enable_ram);
printf(" clock_select = %u \n", (unsigned) state.misc_output.clock_select);
printf(" select_high_bank = %u \n", (unsigned) state.misc_output.select_high_bank);
printf(" horiz_sync_pol = %u \n", (unsigned) state.misc_output.horiz_sync_pol);
printf(" vert_sync_pol = %u \n", (unsigned) state.misc_output.vert_sync_pol);
#endif
}
void CCirrus::write_b_3c4(u8 value)
{
/* Sequencer Index Register */
state.sequencer.index = value;
}
void CCirrus::write_b_3c5(u8 value)
{
unsigned i;
u8 charmap1, charmap2;
/* Sequencer Registers 00..04 */
switch (state.sequencer.index) {
case 0: /* sequencer: reset */
#if defined(DEBUG_VGA)
printf("write 0x3c5: sequencer reset: value=0x%02x \n", (unsigned) value);
#endif
if (state.sequencer.reset1 && ((value & 0x01) == 0))
{
state.sequencer.char_map_select = 0;
state.charmap_address = 0;
bx_gui->lock();
bx_gui->set_text_charmap(& state.memory[0x20000 + state.charmap_address]);
bx_gui->unlock();
state.vga_mem_updated = 1;
}
state.sequencer.reset1 = (value >> 0) & 0x01;
state.sequencer.reset2 = (value >> 1) & 0x01;
break;
case 1: /* sequencer: clocking mode */
#if defined(DEBUG_VGA)
printf("io write 3c5=%02x: clocking mode reg: ignoring \n", (unsigned) value);
#endif
state.sequencer.reg1 = value & 0x3f;
state.x_dotclockdiv2 = ((value & 0x08) > 0);
break;
case 2: /* sequencer: map mask register */
state.sequencer.map_mask = (value & 0x0f);
for (i=0; i<4; i++)
state.sequencer.map_mask_bit[i] = (value >> i) & 0x01;
break;
case 3: /* sequencer: character map select register */