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Sym53C895.cpp
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Sym53C895.cpp
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/* ES40 emulator.
* Copyright (C) 2007-2008 by the ES40 Emulator Project
*
* WWW : http://sourceforge.net/projects/es40
* E-mail : [email protected]
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*
* Although this is not required, the author would appreciate being notified of,
* and receiving any modifications you may make to the source code that might serve
* the general public.
*/
/**
* \file
* Contains the code for the emulated Symbios SCSI controller.
*
* $Id: Sym53C895.cpp,v 1.23 2008/02/27 12:04:28 iamcamiel Exp $
*
* X-1.23 Brian Wheeler 27-FEB-2008
* Avoid compiler warnings.
*
* X-1.22 Camiel Vanderhoeven 16-FEB-2008
* Backported some of the improvements made in the 53C810 code.
*
* X-1.21 Camiel Vanderhoeven 28-JAN-2008
* Avoid compiler warnings.
*
* X-1.20 Camiel Vanderhoeven 24-JAN-2008
* Use new CPCIDevice::do_pci_read and CPCIDevice::do_pci_write.
*
* X-1.19 Camiel Vanderhoeven 18-JAN-2008
* Replaced sext_64 inlines with sext_u64_<bits> inlines for
* performance reasons (thanks to David Hittner for spotting this!)
*
* X-1.18 Camiel Vanderhoeven 12-JAN-2008
* Use disk's SCSI engine.
*
* X-1.17 Camiel Vanderhoeven 06-JAN-2008
* Leave changing the blocksize to the disk itself.
*
* X-1.16 Camiel Vanderhoeven 04-JAN-2008
* Less messages fprint'ed.
*
* X-1.15 Camiel Vanderhoeven 02-JAN-2008
* Avoid compiler warnings.
*
* X-1.14 Camiel Vanderhoeven 30-DEC-2007
* Print file id on initialization.
*
* X-1.13 Camiel Vanderhoeven 29-DEC-2007
* Compileable with older compilers (VC 6.0).
*
* X-1.12 Camiel Vanderhoeven 28-DEC-2007
* Throw exceptions rather than just exiting when errors occur.
*
* X-1.11 Camiel Vanderhoeven 28-DEC-2007
* Keep the compiler happy.
*
* X-1.10 Camiel Vanderhoeven 20-DEC-2007
* Do reselection on read commands.
*
* X-1.9 Camiel Vanderhoeven 19-DEC-2007
* Allow for different blocksizes.
*
* X-1.8 Camiel Vanderhoeven 18-DEC-2007
* Fixed silly mis-interpretation of "add-with-carry".
*
* X-1.7 Camiel Vanderhoeven 18-DEC-2007
* Byte-sized transfers for SCSI controller.
*
* X-1.6 Camiel Vanderhoeven 18-DEC-2007
* Removed some messages.
*
* X-1.5 Camiel Vanderhoeven 18-DEC-2007
* Selection timeout occurs after the phase is checked the first time.
*
* X-1.4 Camiel Vanderhoeven 17-DEC-2007
* Added general timer.
*
* X-1.3 Camiel Vanderhoeven 17-DEC-2007
* SaveState file format 2.1
*
* X-1.2 Camiel Vanderhoeven 16-DEC-2007
* Changed register structure.
*
* X-1.1 Camiel Vanderhoeven 14-DEC-2007
* Initial version in CVS.
**/
#if defined(DEBUG_SYM)
#define DEBUG_SYM_REGS
#define DEBUG_SYM_SCRIPTS
#endif
#include "StdAfx.h"
#include "Sym53C895.h"
#include "System.h"
#include "Disk.h"
#include "SCSIBus.h"
#define R_SCNTL0 0x00
#define R_SCNTL0_ARB1 0x80
#define R_SCNTL0_ARB0 0x40
#define R_SCNTL0_START 0x20
#define R_SCNTL0_WATN 0x10
#define R_SCNTL0_EPC 0x08
#define R_SCNTL0_AAP 0x02
#define R_SCNTL0_TRG 0x01
#define SCNTL0_MASK 0xFB
#define R_SCNTL1 0x01
#define R_SCNTL1_CON 0x10
#define R_SCNTL1_RST 0x08
#define R_SCNTL1_IARB 0x02
#define R_SCNTL2 0x02
#define R_SCNTL2_SDU 0x80
#define R_SCNTL2_CHM 0x40
#define R_SCNTL2_SLPMD 0x20
#define R_SCNTL2_SLPHBEN 0x10
#define R_SCNTL2_WSS 0x08
#define R_SCNTL2_VUE0 0x04
#define R_SCNTL2_VUE1 0x02
#define R_SCNTL2_WSR 0x01
#define SCNTL2_MASK 0xF2
#define SCNTL2_W1C 0x09
#define R_SCNTL3 0x03
#define R_SCNTL3_EWS 0x08
#define R_SCID 0x04
#define R_SCID_ID 0x0F
#define SCID_MASK 0x6F
#define R_SXFER 0x05
#define R_SDID 0x06
#define R_SDID_ID 0x0F
#define SDID_MASK 0x0F
#define R_GPREG 0x07
#define GPREG_MASK 0x1F
#define R_SFBR 0x08
#define R_SOCL 0x09
#define R_SOCL_ACK 0x40
#define R_SOCL_ATN 0x20
#define R_SSID 0x0A
#define R_SSID_VAL 0x80
#define R_SSID_ID 0x0F
#define R_SBCL 0x0B
#define R_SBCL_REQ 0x80
#define R_SBCL_ACK 0x40
#define R_SBCL_BSY 0x20
#define R_SBCL_SEL 0x10
#define R_SBCL_ATN 0x08
#define R_SBCL_MSG 0x04
#define R_SBCL_CD 0x02
#define R_SBCL_IO 0x01
#define R_SBCL_PHASE 0x07
#define R_DSTAT 0x0C
#define R_DSTAT_DFE 0x80
#define R_DSTAT_MDPE 0x40
#define R_DSTAT_BF 0x20
#define R_DSTAT_ABRT 0x10
#define R_DSTAT_SSI 0x08
#define R_DSTAT_SIR 0x04
#define R_DSTAT_IID 0x01
#define DSTAT_RC 0x7D
#define DSTAT_FATAL 0x7D
#define R_SSTAT0 0x0D
#define R_SSTAT0_RST 0x02
#define R_SSTAT0_SDP0 0x01
#define R_SSTAT1 0x0E
#define R_SSTAT1_SDP1 0x01
#define R_SSTAT2 0x0F
#define R_SSTAT2_LDSC 0x02
#define R_DSA 0x10
#define R_ISTAT 0x14
#define R_ISTAT_ABRT 0x80
#define R_ISTAT_SRST 0x40
#define R_ISTAT_SIGP 0x20
#define R_ISTAT_SEM 0x10
#define R_ISTAT_CON 0x08
#define R_ISTAT_INTF 0x04
#define R_ISTAT_SIP 0x02
#define R_ISTAT_DIP 0x01
#define ISTAT_MASK 0xF0
#define ISTAT_W1C 0x04
#define R_CTEST0 0x18
#define R_CTEST1 0x19
#define R_CTEST1_FMT 0xF0
#define R_CTEST1_FFL 0x0F
#define R_CTEST2 0x1A
#define R_CTEST2_DDIR 0x80
#define R_CTEST2_SIGP 0x40
#define R_CTEST2_CIO 0x20
#define R_CTEST2_CM 0x10
#define R_CTEST2_SRTCH 0x08
#define R_CTEST2_TEOP 0x04
#define R_CTEST2_DREQ 0x02
#define R_CTEST2_DACK 0x01
#define CTEST2_MASK 0x08
#define R_CTEST3 0x1B
#define R_CTEST3_REV 0xf0
#define R_CTEST3_FLF 0x08
#define R_CTEST3_CLF 0x04
#define R_CTEST3_FM 0x02
#define CTEST3_MASK 0x0B
#define R_TEMP 0x1C
#define R_DFIFO 0x20
#define R_CTEST4 0x21
#define R_CTEST5 0x22
#define R_CTEST5_ADCK 0x80
#define R_CTEST5_BBCK 0x40
#define CTEST5_MASK 0x3F
#define R_DBC 0x24
#define R_DCMD 0x27
#define R_DNAD 0x28
#define R_DSP 0x2C
#define R_DSPS 0x30
#define R_SCRATCHA 0x34
#define R_DMODE 0x38
#define R_DMODE_MAN 0x01
#define R_DIEN 0x39
#define DIEN_MASK 0x7D
#define R_SBR 0x3A
#define R_DCNTL 0x3B
#define R_DCNTL_SSM 0x10
#define R_DCNTL_STD 0x04
#define R_DCNTL_IRQD 0x02
#define R_DCNTL_COM 0x01
#define DCNTL_MASK 0xFB
#define R_ADDER 0x3C
#define R_SIEN0 0x40
#define SIEN0_MASK 0xFF
#define R_SIEN1 0x41
#define SIEN1_MASK 0x17
#define R_SIST0 0x42
#define R_SIST0_MA 0x80
#define R_SIST0_CMP 0x40
#define R_SIST0_SEL 0x20
#define R_SIST0_RSL 0x10
#define R_SIST0_SGE 0x08
#define R_SIST0_UDC 0x04
#define R_SIST0_RST 0x02
#define R_SIST0_PAR 0x01
#define SIST0_RC 0xFF
#define SIST0_FATAL 0x8F
#define R_SIST1 0x43
#define R_SIST1_SBMC 0x10
#define R_SIST1_STO 0x04
#define R_SIST1_GEN 0x02
#define R_SIST1_HTH 0x01
#define SIST1_RC 0x17
#define SIST1_FATAL 0x14
#define R_MACNTL 0x46
#define MACNTL_MASK 0x0F
#define R_GPCNTL 0x47
#define R_STIME0 0x48
#define R_STIME1 0x49
#define R_STIME1_GEN 0x0F
#define STIME1_MASK 0x7F
#define R_RESPID 0x4A
#define R_STEST0 0x4C
#define R_STEST1 0x4D
#define STEST1_MASK 0xCC
#define R_STEST2 0x4E
#define R_STEST2_SCE 0x80
#define R_STEST2_ROF 0x40
#define R_STEST2_DIF 0x20
#define R_STEST2_SLB 0x10
#define R_STEST2_SZM 0x08
#define R_STEST2_AWS 0x04
#define R_STEST2_EXT 0x02
#define R_STEST2_LOW 0x01
#define STEST2_MASK 0xBF
#define R_STEST3 0x4F
#define R_STEST3_TE 0x80
#define R_STEST3_STR 0x40
#define R_STEST3_HSC 0x20
#define R_STEST3_DSI 0x10
#define R_STEST3_S16 0x08
#define R_STEST3_TTM 0x04
#define R_STEST3_CSF 0x02
#define R_STEST3_STW 0x01
#define STEST3_MASK 0xFF
#define R_STEST4 0x52
#define R_SBDL 0x58
#define R_SCRATCHB 0x5C
#define R_SCRATCHC 0x60
#define R8(a) state.regs.reg8[R_##a]
#define R16(a) state.regs.reg16[R_##a/2]
#define R32(a) state.regs.reg32[R_##a/4]
// test bit in register
#define TB_R8(a,b) ((R8(a) & R_##a##_##b) == R_##a##_##b)
//set bit in register
#define SB_R8(a,b,c) R8(a) = (R8(a) & ~R_##a##_##b) | (c ? R_##a##_##b : 0)
// write with mask
#define WRM_R8(a,b) R8(a) = (R8(a) & ~a##_MASK) | ((b) & a##_MASK)
// write with mask and write-1-to-clear
#define WRMW1C_R8(a,b) R8(a) = (R8(a) & ~a##_MASK & ~a##_W1C) | ((b) & a##_MASK) | (R8(a) & ~(b) & a##_W1C)
#define RAISE(a,b) set_interrupt(R_##a,R_##a##_##b)
#define RDCLR_R8(a) R8(a) &= ~a##_RC
#define GET_DEST() (R8(SDID) & R_SCID_ID)
#define SET_DEST(a) R8(SDID) = (a) & R_SCID_ID
#define GET_DBC() (R32(DBC) & 0x00ffffff)
#define SET_DBC(a) R32(DBC) = (R32(DBC) & 0xff000000) | ((a) & 0x00ffffff)
#define PT state.per_target[GET_DEST()]
#define PTD get_disk(0,GET_DEST())
u32 sym_cfg_data[64] = {
/*00*/ 0x000c1000, // CFID: vendor + device
/*04*/ 0x02000001, // CFCS: command + status
/*08*/ 0x01000000, // CFRV: class + revision
/*0c*/ 0x00000000, // CFLT: latency timer + cache line size
/*10*/ 0x00000001, // BAR0: IO Space
/*14*/ 0x00000000, // BAR1: Memory space
/*18*/ 0x00000000, // BAR2: RAM space
/*1c*/ 0x00000000, // BAR3:
/*20*/ 0x00000000, // BAR4:
/*24*/ 0x00000000, // BAR5:
/*28*/ 0x00000000, // CCIC: CardBus
/*2c*/ 0x00000000, // CSID: subsystem + vendor
/*30*/ 0x00000000, // BAR6: expansion rom base
/*34*/ 0x00000000, // CCAP: capabilities pointer
/*38*/ 0x00000000,
/*3c*/ 0x401101ff, // CFIT: interrupt configuration
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
};
u32 sym_cfg_mask[64] = {
/*00*/ 0x00000000, // CFID: vendor + device
/*04*/ 0x00000157, // CFCS: command + status
/*08*/ 0x00000000, // CFRV: class + revision
/*0c*/ 0x0000ffff, // CFLT: latency timer + cache line size
/*10*/ 0xffffff00, // BAR0: IO space (256 bytes)
/*14*/ 0xffffff00, // BAR1: Memory space (256 bytes)
/*18*/ 0xfffff000, // BAR2: RAM space (4KB)
/*1c*/ 0x00000000, // BAR3:
/*20*/ 0x00000000, // BAR4:
/*24*/ 0x00000000, // BAR5:
/*28*/ 0x00000000, // CCIC: CardBus
/*2c*/ 0x00000000, // CSID: subsystem + vendor
/*30*/ 0x00000000, // BAR6: expansion rom base
/*34*/ 0x00000000, // CCAP: capabilities pointer
/*38*/ 0x00000000,
/*3c*/ 0x000000ff, // CFIT: interrupt configuration
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
};
/**
* Constructor.
**/
CSym53C895::CSym53C895(CConfigurator * cfg, CSystem * c, int pcibus, int pcidev)
: CDiskController(cfg,c,pcibus,pcidev,1,16)
{
add_function(0,sym_cfg_data, sym_cfg_mask);
ResetPCI();
c->RegisterClock(this, true);
chip_reset();
// create scsi bus
CSCSIBus * a = new CSCSIBus(cfg, c);
scsi_register(0, a, 7); // scsi id 7 by default
printf("%s: $Id: Sym53C895.cpp,v 1.23 2008/02/27 12:04:28 iamcamiel Exp $\n",devid_string);
}
CSym53C895::~CSym53C895()
{
delete scsi_bus[0];
}
void CSym53C895::chip_reset()
{
state.executing = false;
state.wait_reselect = false;
state.irq_asserted = false;
state.gen_timer = 0;
memset(state.regs.reg32,0,sizeof(state.regs.reg32));
R8(SCNTL0) = R_SCNTL0_ARB1 | R_SCNTL0_ARB0; // 810
R8(DSTAT) = R_DSTAT_DFE; // DMA FIFO empty // 810
// R8(SSTAT2) = R_SSTAT2_LDSC; // 810
R8(CTEST1) = R_CTEST1_FMT; // 810
R8(CTEST2) = R_CTEST2_DACK; // 810
R8(CTEST3) = (u8)(pci_state.config_data[0][2]<<4) & R_CTEST3_REV; // Chip rev.
R8(MACNTL) = 0xD0; // 895 type ID
R8(GPCNTL) = 0x0F; // 810
R8(STEST0) = 0x03; // 810
}
void CSym53C895::register_disk(class CDisk * dsk, int bus, int dev)
{
CDiskController::register_disk(dsk, bus, dev);
dsk->scsi_register(0,scsi_bus[0],dev);
}
static u32 sym_magic1 = 0x53C895CC;
static u32 sym_magic2 = 0xCC53C895;
/**
* Save state to a Virtual Machine State file.
**/
int CSym53C895::SaveState(FILE *f)
{
long ss = sizeof(state);
int res;
if (res = CPCIDevice::SaveState(f))
return res;
fwrite(&sym_magic1,sizeof(u32),1,f);
fwrite(&ss,sizeof(long),1,f);
fwrite(&state,sizeof(state),1,f);
fwrite(&sym_magic2,sizeof(u32),1,f);
printf("%s: %d bytes saved.\n",devid_string,(int)ss);
return 0;
}
/**
* Restore state from a Virtual Machine State file.
**/
int CSym53C895::RestoreState(FILE *f)
{
long ss;
u32 m1;
u32 m2;
int res;
size_t r;
if (res = CPCIDevice::RestoreState(f))
return res;
r = fread(&m1,sizeof(u32),1,f);
if (r!=1)
{
printf("%s: unexpected end of file!\n",devid_string);
return -1;
}
if (m1 != sym_magic1)
{
printf("%s: MAGIC 1 does not match!\n",devid_string);
return -1;
}
fread(&ss,sizeof(long),1,f);
if (r!=1)
{
printf("%s: unexpected end of file!\n",devid_string);
return -1;
}
if (ss != sizeof(state))
{
printf("%s: STRUCT SIZE does not match!\n",devid_string);
return -1;
}
fread(&state,sizeof(state),1,f);
if (r!=1)
{
printf("%s: unexpected end of file!\n",devid_string);
return -1;
}
r = fread(&m2,sizeof(u32),1,f);
if (r!=1)
{
printf("%s: unexpected end of file!\n",devid_string);
return -1;
}
if (m2 != sym_magic2)
{
printf("%s: MAGIC 1 does not match!\n",devid_string);
return -1;
}
printf("%s: %d bytes restored.\n",devid_string,(int)ss);
return 0;
}
void CSym53C895::WriteMem_Bar(int func,int bar, u32 address, int dsize, u32 data)
{
void * p;
switch (bar)
{
case 0:
case 1:
address &= 0x7f;
switch(dsize)
{
case 8:
#if defined(DEBUG_SYM_REGS)
printf("SYM: Write to register %02x: %02x. \n",address,data);
#endif
if (address>=R_SCRATCHC) {
state.regs.reg8[address] = (u8)data;
break;
}
switch (address)
{
// SIMPLE CASES: JUST WRITE
case R_SXFER: // 05
case R_DSA: // 10
case R_DSA+1: // 11
case R_DSA+2: // 12
case R_DSA+3: // 13
case R_CTEST0: // 18
case R_TEMP: // 1C
case R_TEMP+1: // 1D
case R_TEMP+2: // 1E
case R_TEMP+3: // 1F
case R_DSP: // 2C
case R_DSP+1: // 2D
case R_DSP+2: // 2E
case R_DSPS: // 30
case R_DSPS+1: // 31
case R_DSPS+2: // 32
case R_DSPS+3: // 33
case R_SCRATCHA:// 34
case R_SCRATCHA+1:// 35
case R_SCRATCHA+2:// 36
case R_SCRATCHA+3:// 37
case R_DMODE: // 38
case R_SBR: // 3A // 810
case R_GPCNTL: // 47
case R_STIME0: // 48
case R_RESPID: // 4A
case R_RESPID+1:// 4B
case R_STEST0: // 4C
case R_SCRATCHB:// 5C
case R_SCRATCHB+1:// 5D
case R_SCRATCHB+2:// 5E
case R_SCRATCHB+3:// 5F
state.regs.reg8[address] = (u8)data;
break;
case R_SCNTL0: // 00
// side effects: start arbitration bit
write_b_scntl0((u8)data);
break;
case R_SCNTL1: //01
// side effects: start immediate arbitration bit
write_b_scntl1((u8)data);
break;
case R_SCNTL2: //02
WRMW1C_R8(SCNTL2,(u8)data);
break;
case R_SCNTL3: //03
// side effects: clearing EWS
write_b_scntl3((u8)data);
break;
case R_SCID: // 04
WRM_R8(SCID,(u8)data);
break;
case R_SDID: // 06
WRM_R8(SDID,(u8)data);
break;
case R_GPREG: // 07
WRM_R8(GPREG,(u8)data);
break;
case R_ISTAT: // 14
write_b_istat((u8)data);
break;
case R_CTEST2: // 1A
WRM_R8(CTEST2,(u8)data);
break;
case R_CTEST3: // 1B
write_b_ctest3((u8)data);
break;
case R_CTEST4: // 21
write_b_ctest4((u8)data);
break;
case R_CTEST5: // 22
write_b_ctest5((u8)data);
break;
case R_DSP+3: // 2F
state.regs.reg8[address] = (u8)data;
post_dsp_write();
break;
case R_DIEN: // 39
WRM_R8(DIEN,(u8)data);
eval_interrupts();
break;
case R_DCNTL: // 3B
write_b_dcntl((u8)data);
break;
case R_SIEN0: // 40
R8(SIEN0) = (u8)data;
eval_interrupts();
break;
case R_SIEN1: // 41
WRM_R8(SIEN1,(u8)data);
eval_interrupts();
break;
case R_MACNTL: // 46 // 810
WRM_R8(MACNTL,(u8)data);
break;
case R_STIME1: // 49
WRM_R8(STIME1,(u8)data);
state.gen_timer = (R8(STIME1) & R_STIME1_GEN) * 30;
break;
case R_STEST1: // 4D
WRM_R8(STEST1,(u8)data);
break;
case R_STEST2: // 4E
write_b_stest2((u8)data);
break;
case R_STEST3: // 4F
write_b_stest3((u8)data);
break;
case R_DSTAT: // 0C
case R_SSTAT0: // 0D
case R_SSTAT1: // 0E
case R_SSTAT2: // 0F
//printf("SYM: Write to read-only memory at %02x. FreeBSD driver cache test.\n" ,address);
break;
default:
printf("SYM: Write 8 bits to unknown memory at %02x with %08x.\n",address,data);
throw((int)1);
}
break;
case 16:
WriteMem_Bar(0,1,address+0,8,(data>>0) & 0xff);
WriteMem_Bar(0,1,address+1,8,(data>>8) & 0xff);
break;
case 32:
WriteMem_Bar(0,1,address+0,8,(data>> 0) & 0xff);
WriteMem_Bar(0,1,address+1,8,(data>> 8) & 0xff);
WriteMem_Bar(0,1,address+2,8,(data>>16) & 0xff);
WriteMem_Bar(0,1,address+3,8,(data>>24) & 0xff);
break;
}
break;
case 2:
p = (u8*)state.ram + address;
switch(dsize)
{
case 8:
*((u8 *) p) = (u8) data;
break;
case 16:
*((u16 *) p) = (u16) data;
break;
case 32:
*((u32 *) p) = (u32) data;
break;
}
break;
}
}
u32 CSym53C895::ReadMem_Bar(int func,int bar, u32 address, int dsize)
{
u32 data = 0;
void * p;
switch (bar)
{
case 0:
case 1:
address &= 0x7f;
switch(dsize)
{
case 8:
if (address>=R_SCRATCHC)
{
data = state.regs.reg8[address];
break;
}
switch(address)
{
case R_SCNTL0: // 00
case R_SCNTL1: // 01
case R_SCNTL2: // 02
case R_SCNTL3: // 03
case R_SCID: // 04
case R_SXFER: // 05
case R_SDID: // 06
case R_GPREG: // 07
case R_SFBR: // 08
case R_SSID: // 0A
case R_SBCL: // 0B
case R_SSTAT0: // 0D
case R_SSTAT1: // 0E
case R_SSTAT2: // 0F
case R_DSA: // 10
case R_DSA+1: // 11
case R_DSA+2: // 12
case R_DSA+3: // 13
case R_ISTAT: // 14
case R_CTEST0: // 18
case R_CTEST1: // 19
case R_CTEST3: // 1B
case R_TEMP: // 1C
case R_TEMP+1: // 1D
case R_TEMP+2: // 1E
case R_TEMP+3: // 1F
case R_CTEST4: // 21
case R_CTEST5: // 22
case R_DBC: // 24 // 810
case R_DBC+1: // 25 // 810
case R_DBC+2: // 26 // 810
case R_DCMD: // 27 // 810
case R_DNAD: // 28 // 810
case R_DNAD+1: // 29 // 810
case R_DNAD+2: // 2A // 810
case R_DNAD+3: // 2B // 810
case R_DSP: // 2C
case R_DSP+1: // 2D
case R_DSP+2: // 2E
case R_DSP+3: // 2F
case R_DSPS: // 30
case R_DSPS+1: // 31
case R_DSPS+2: // 32
case R_DSPS+3: // 33
case R_DMODE: // 38
case R_DIEN: // 39
case R_SBR: // 3A // 810
case R_DCNTL: // 3B
case R_SIEN0: // 40
case R_SIEN1: // 41
case R_MACNTL: // 46 // 810
case R_GPCNTL: // 47
case R_STIME0: // 48
case R_STIME1: // 49
case R_RESPID: // 4A
case R_RESPID+1:// 4B
case R_STEST0: // 4C
case R_STEST1: // 4D
case R_STEST2: // 4E
case R_STEST3: // 4F
case R_STEST4: // 52
case R_SBDL: // 58
case R_SBDL+1: // 59
data = state.regs.reg8[address];
break;
case R_DSTAT: // 0C
data = read_b_dstat();
break;
case R_CTEST2: // 1A
data = read_b_ctest2();
break;
case R_DFIFO: // 20
data = R8(DBC) & 0x7f; // 810 - fake the DFIFO count
break;
case R_SCRATCHA: // 34
case R_SCRATCHA+1: // 35
case R_SCRATCHA+2: // 36
case R_SCRATCHA+3: // 37
data = read_b_scratcha(address-R_SCRATCHA);
break;
case R_SIST0: // 42
case R_SIST1: // 43
data = read_b_sist(address-R_SIST0);
break;
case R_SCRATCHB: // 5C
case R_SCRATCHB+1: // 5D
case R_SCRATCHB+2: // 5E
case R_SCRATCHB+3: // 5F
data = read_b_scratchb(address-R_SCRATCHB);
break;
default:
printf("SYM: Attempt to read %d bits from memory at %02x\n", dsize, address);
throw((int)1);
}
#if defined(DEBUG_SYM_REGS)
printf("SYM: Read frm register %02x: %02x. \n",address,data);
#endif
break;
case 16:
data = (ReadMem_Bar(0,1,address+0,8)<<0) & 0x00ff;
data |= (ReadMem_Bar(0,1,address+1,8)<<8) & 0xff00;
break;
case 32:
data = (ReadMem_Bar(0,1,address+0,8)<< 0) & 0x000000ff;
data |= (ReadMem_Bar(0,1,address+1,8)<< 8) & 0x0000ff00;
data |= (ReadMem_Bar(0,1,address+2,8)<<16) & 0x00ff0000;
data |= (ReadMem_Bar(0,1,address+3,8)<<24) & 0xff000000;
break;
}
break;
case 2:
p = (u8*)state.ram + address;
switch(dsize)
{
case 8:
return *((u8 *) p);
case 16:
return *((u16 *) p);
case 32:
return *((u32 *) p);
}
break;
}
return data;
}
u32 CSym53C895::config_read_custom(int func, u32 address, int dsize, u32 data)
{
if (address>=0x80)
return ReadMem_Bar(func,1,address-0x80,dsize);
else
return data;
}
void CSym53C895::config_write_custom(int func, u32 address, int dsize, u32 old_data, u32 new_data, u32 data)
{
if (address>=0x80)
WriteMem_Bar(func,1,address-0x80,dsize,data);
}
void CSym53C895::write_b_scntl0(u8 value)
{
bool old_start = TB_R8(SCNTL0,START);
WRM_R8(SCNTL0,value);
if (TB_R8(SCNTL0,START) && !old_start)
FAILURE("SYM: Don't know how to start arbitration sequence");
if (TB_R8(SCNTL0,TRG))
FAILURE("SYM: Don't know how to operate in target mode");
}
void CSym53C895::write_b_scntl1(u8 value)
{
bool old_iarb = TB_R8(SCNTL1,IARB);
bool old_con = TB_R8(SCNTL1,CON);
bool old_rst = TB_R8(SCNTL1,RST);
R8(SCNTL1) = value;
// if (TB_R8(SCNTL1,CON) != old_con)
// printf("SYM: Don't know how to forcibly connect or disconnect\n");
if (TB_R8(SCNTL1,RST) != old_rst)
{
SB_R8(SSTAT0,SDP0,false);
SB_R8(SSTAT1,SDP1,false);
R16(SBDL)=0;
R8(SBCL)=0;
SB_R8(SSTAT0,RST,!old_rst);
// printf("SYM: %s SCSI bus reset.\n",old_rst?"end":"start");
if (!old_rst)
RAISE(SIST0,RST);
}
if (TB_R8(SCNTL1,IARB) && !old_iarb)
FAILURE("SYM: Don't know how to start immediate arbitration sequence.\n");
}
void CSym53C895::write_b_scntl3(u8 value)
{
R8(SCNTL3) = value;
if (!TB_R8(SCNTL3,EWS))
SB_R8(SCNTL2,WSR,false);
}
void CSym53C895::write_b_istat(u8 value)
{
bool old_srst = TB_R8(ISTAT,SRST);
bool old_sem = TB_R8(ISTAT,SEM);
bool old_sigp = TB_R8(ISTAT,SIGP);
WRMW1C_R8(ISTAT, value);
if (TB_R8(ISTAT,ABRT))
{
// printf("SYM: Aborting on request.\n");
RAISE(DSTAT,ABRT);
}
if (TB_R8(ISTAT,SRST) && !old_srst)
{
// printf("SYM: Resetting on request.\n");
chip_reset();
}
// if (TB_R8(ISTAT,SEM) != old_sem)
// printf("SYM: SEM %s.\n",old_sem?"reset":"set");
// if (TB_R8(ISTAT,SIGP) != old_sigp)
// printf("SYM: SIGP %s.\n",old_sigp?"reset":"set");
if (TB_R8(ISTAT,SIGP))
{
if (state.wait_reselect)
{
// printf("SYM: SIGP while wait_reselect. Jumping...\n");
R32(DSP) = state.wait_jump;
state.wait_reselect = false;
state.executing = true;
}
}
eval_interrupts();
}
u8 CSym53C895::read_b_ctest2()
{
SB_R8(CTEST2, CIO, pci_state.config_data[0][4]!=0);
SB_R8(CTEST2, CM, pci_state.config_data[0][5]!=0);
SB_R8(CTEST2, SIGP, TB_R8(ISTAT, SIGP));
SB_R8(ISTAT, SIGP, false);
// printf("SYM: SIGP cleared by CTEST2 read.\n");
return R8(CTEST2);
}
void CSym53C895::write_b_ctest3(u8 value)
{
WRM_R8(CTEST3, value);
//if ((value>>3) & 1)
// printf("SYM: Don't know how to flush DMA FIFO\n");
//if ((value>>2) & 1)
// printf("SYM: Don't know how to clear DMA FIFO\n");
if ((value>>1) & 1)
FAILURE("SYM: Don't know how to handle FM mode");
}
void CSym53C895::write_b_ctest4(u8 value)