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System.cpp
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System.cpp
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/* ES40 emulator.
* Copyright (C) 2007-2008 by the ES40 Emulator Project
*
* Website: http://sourceforge.net/projects/es40
* E-mail : [email protected]
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*
* Although this is not required, the author would appreciate being notified of,
* and receiving any modifications you may make to the source code that might serve
* the general public.
*/
/**
* \file
* Contains the code for the emulated Typhoon Chipset devices.
*
* $Id: System.cpp,v 1.68 2008/03/04 19:05:21 iamcamiel Exp $
*
* X-1.67 Camiel Vanderhoeven 04-MAR-2008
* Support some basic MP features. (CPUID read from C-Chip MISC
* register, inter-processor interrupts)
*
* X-1.66 Brian Wheeler 02-MAR-2008
* Allow large memory sizes (>1GB).
*
* X-1.65 Camiel Vanderhoeven 02-MAR-2008
* Natural way to specify large numeric values ("10M") in the config file.
*
* X-1.64 Brian Wheeler 29-FEB-2008
* Do not generate unknown PCI 0 memory messages for legacy VGA
* memory region.
*
* X-1.63 Brian Wheeler 26-FEB-2008
* Support reading from Pchip TLBIV and TLBIA registers. (Which are
* supposed to be write-only!)
*
* X-1.62 David Leonard 20-FEB-2008
* Flush stdout during decompression progress.
*
* X-1.61 Camiel Vanderhoeven 08-FEB-2008
* Show originating device name on memory errors.
*
* X-1.60 Camiel Vanderhoeven 01-FEB-2008
* Avoid unnecessary shift-operations to calculate constant values.
*
* X-1.59 Camiel Vanderhoeven 28-JAN-2008
* Avoid compiler warnings.
*
* X-1.58 Camiel Vanderhoeven 25-JAN-2008
* Added option to disable the icache.
*
* X-1.57 Camiel Vanderhoeven 19-JAN-2008
* Run CPU in a separate thread if CPU_THREADS is defined.
* NOTA BENE: This is very experimental, and has several problems.
*
* X-1.56 Camiel Vanderhoeven 18-JAN-2008
* Process device interrupts after a 100-cpu-cycle delay.
*
* X-1.55 Camiel Vanderhoeven 12-JAN-2008
* Comments.
*
* X-1.54 Camiel Vanderhoeven 09-JAN-2008
* Let PtrToMemory return NULL when the address is out of range.
*
* X-1.53 Camiel Vanderhoeven 08-JAN-2008
* Layout of comments.
*
* X-1.52 Camiel Vanderhoeven 08-JAN-2008
* Split out chipset registers.
*
* X-1.51 Camiel Vanderhoeven 07-JAN-2008
* Corrected error in last update; csr reg. 0x600, not 0600...
*
* X-1.50 Camiel Vanderhoeven 07-JAN-2008
* DMA scatter/gather access. Split out some things.
*
* X-1.49 Camiel Vanderhoeven 02-JAN-2008
* Cleanup.
*
* X-1.48 Camiel Vanderhoeven 30-DEC-2007
* Comments.
*
* X-1.47 Camiel Vanderhoeven 30-DEC-2007
* Fixed error in printf again.
*
* X-1.46 Camiel Vanderhoeven 30-DEC-2007
* Fixed error in printf.
*
* X-1.45 Camiel Vanderhoeven 30-DEC-2007
* Print file id on initialization.
*
* X-1.44 Camiel Vanderhoeven 29-DEC-2007
* Fix memory-leak.
*
* X-1.43 Camiel Vanderhoeven 28-DEC-2007
* Throw exceptions rather than just exiting when errors occur.
*
* X-1.42 Camiel Vanderhoeven 28-DEC-2007
* Keep the compiler happy.
*
* X-1.41 Camiel Vanderhoeven 20-DEC-2007
* Close files and free memory when the emulator shuts down.
*
* X-1.40 Camiel Vanderhoeven 17-DEC-2007
* SaveState file format 2.1
*
* X-1.39 Camiel Vanderhoeven 14-DEC-2007
* Commented out SRM IDE READ replacement; doesn't work with SCSI!
*
* X-1.38 Camiel Vanderhoeven 10-DEC-2007
* Added get_cpu
*
* X-1.37 Camiel Vanderhoeven 10-DEC-2007
* Use configurator.
*
* X-1.36 Camiel Vanderhoeven 6-DEC-2007
* Report references to unused PCI space.
*
* X-1.35 Camiel Vanderhoeven 2-DEC-2007
* Avoid misprobing of unused PCI configuration space.
*
* X-1.34 Camiel Vanderhoeven 2-DEC-2007
* Added support for code profiling, and for direct operations on the
* Tsunami/Typhoon's interrupt registers.
*
* X-1.33 Brian Wheeler 1-DEC-2007
* 1. Ignore address bits 35- 42 in the physical address; this is
* correct according to the Tsunami/Typhoon HRM; which states that
* " The system address space is divided into two parts: system
* memory and PIO. This division is indicated by physical memory bit
* <43> = 1 for PIO accesses from the CPU [...] In general, bits
* <42:35> are don’t cares if bit <43> is asserted. [...] The
* Typhoon Cchip supports 32GB of system memory (35 bits total). "
* 2. Added support for Ctrl+C and panic.
*
* X-1.32 Camiel Vanderhoeven 17-NOV-2007
* Use CHECK_ALLOCATION.
*
* X-1.31 Camiel Vanderhoeven 16-NOV-2007
* Replaced PCI_ReadMem and PCI_WriteMem with PCI_Phys.
*
* X-1.30 Camiel Vanderhoeven 05-NOV-2007
* Put slow-to-fast clock ratio into #define CLOCK_RATIO. Increased
* this to 100,000.
*
* X-1.29 Camiel Vanderhoeven 18-APR-2007
* Decompressed ROM image is now identical between big- and small-
* endian platforms (put endian_64 around PALbase and PC).
*
* X-1.28 Camiel Vanderhoeven 18-APR-2007
* Faster lockstep mechanism (send info 50 cpu cycles at a time)
*
* X-1.27 Camiel Vanderhoeven 16-APR-2007
* Remove old address range if a new one is registered (same device/
* same index)
*
* X-1.26 Camiel Vanderhoeven 16-APR-2007
* Allow configuration strings with spaces in them.
*
*
* X-1.25 Camiel Vanderhoeven 11-APR-2007
* Moved all data that should be saved to a state file to a structure
* "state".
*
* X-1.24 Camiel Vanderhoeven 10-APR-2007
* New mechanism for SRM replacements. Where these need to be executed,
* CSystem::LoadROM() puts a special opcode (a CALL_PAL instruction
* with an otherwise illegal operand of 0x01234xx) in memory.
* CAlphaCPU::DoClock() recognizes these opcodes and performs the SRM
* action.
*
* X-1.23 Camiel Vanderhoeven 10-APR-2007
* Extended ROM-handling code to favor loading decompressed ROM code
* over loading compressed code, and to save decompressed ROM code
* during the first time the emulator is run.
*
* X-1.22 Camiel Vanderhoeven 10-APR-2007
* Removed obsolete ROM-handling code.
*
* X-1.21 Brian Wheeler 31-MAR-2007
* Removed ; after #endif to avoid compiler warnings.
*
* X-1.20 Camiel Vanderhoeven 26-MAR-2007
* Show references to unknown memory regions when DEBUG_UNKMEM is
* defined.
*
* X-1.19 Camiel Vanderhoeven 1-MAR-2007
* Changes for Solaris/SPARC port:
* a) All $-signs in variable names are replaced with underscores.
* b) Some functions now get a const char * argument i.s.o. char * to avoid
* compiler warnings.
* c) If ALIGN_MEM_ACCESS is defined, memory accesses are checked for natural
* alignment. If access is not naturally aligned, it is performed one byte
* at a time.
* d) Accesses to main-memory are byte-swapped on a big-endian architecture.
* This is done through the endian_xx macro's, that differ according to
* the endianness of the architecture.
*
* X-1.18 Camiel Vanderhoeven 28-FEB-2007
* In the lockstep-versions of the emulator, perform lockstep
* synchronisation for every clock tick.
*
* X-1.17 Camiel Vanderhoeven 27-FEB-2007
* Removed an unreachable "return 0;" line.
*
* X-1.16 Camiel Vanderhoeven 18-FEB-2007
* Keep track of the cycle-counter in single-step mode (using the
* iSSCycles variable.
*
* X-1.15 Camiel Vanderhoeven 16-FEB-2007
* a) Provide slow and fast clocks for devices. Typical fast-clocked
* devices are the CPU(s); most other devices that need a clock should
* probably be slow clock devices.
* b) DoClock() was replaced with Run(), which runs until one of the
* connected devices returns something other than 0; and SingleStep().
* c) Corrected some signed/unsigned integer comparison warnings.
*
* X-1.14 Brian Wheeler 13-FEB-2007
* a) Corrected some typo's in printf statements.
* b) Fixed some compiler warnings (assignment inside if()).
*
* X-1.13 Camiel Vanderhoeven 12-FEB-2007
* Removed error messages when accessing unknown memory.
*
* X-1.12 Camiel Vanderhoeven 12-FEB-2007
* Corrected a signed/unsigned integer comparison warning.
*
* X-1.11 Camiel Vanderhoeven 9-FEB-2007
* Added comments.
*
* X-1.10 Brian Wheeler 7-FEB-2007
* Remove FindConfig function, and load configuration file from the
* constructor.
*
* X-1.9 Camiel Vanderhoeven 7-FEB-2007
* a) CTraceEngine is no longer instantiated as a member of CSystem.
* b) Calls to trace_dev now use the TRC_DEVx macro's.
*
* X-1.8 Camiel Vanderhoeven 3-FEB-2007
* a) Removed last conditional for supporting another system than an ES40
* (#ifdef DS15)
* b) FindConfig() now returns the default value rather than crashing
* when none of the standard configuration files can be found.
*
* X-1.7 Brian Wheeler 3-FEB-2007
* Formatting.
*
* X-1.6 Brian Wheeler 3-FEB-2007
* Replaced several 64-bit values in 0x... syntax with X64(...).
*
* X-1.5 Brian Wheeler 3-FEB-2007
* Added possibility to load a configuration file.
*
* X-1.4 Brian Wheeler 3-FEB-2007
* Replaced 1i64 with X64(1) in two instances.
*
* X-1.3 Brian Wheeler 3-FEB-2007
* Scanf and printf statements made compatible with Linux/GCC/glibc.
*
* X-1.2 Brian Wheeler 3-FEB-2007
* Includes are now case-correct (necessary on Linux)
*
* X-1.1 Camiel Vanderhoeven 19-JAN-2007
* Initial version in CVS.
**/
#include "StdAfx.h"
#include "System.h"
#include "AlphaCPU.h"
#include "lockstep.h"
#include <ctype.h>
#include <stdlib.h>
#include <signal.h>
#define CLOCK_RATIO 10000
#if defined(LS_MASTER) || defined(LS_SLAVE)
char debug_string[10000] = "";
char * dbg_strptr = debug_string;
#endif
/**
* Constructor.
**/
CSystem::CSystem(CConfigurator * cfg)
{
int i;
if (theSystem != 0)
FAILURE("More than one system!!");
theSystem = this;
myCfg = cfg;
iNumComponents = 0;
iNumFastClocks = 0;
iNumSlowClocks = 0;
iNumMemories = 0;
iNumCPUs = 0;
iNumMemoryBits = (int)myCfg->get_num_value("memory.bits",27);
// iNumConfig = 0;
#if defined(IDB)
iSingleStep = 0;
iSSCycles = 0;
#endif
for (i=0;i<4;i++)
state.cchip.dim[i] = 0;
state.cchip.drir = 0;
state.cchip.misc = X64(0000000800000000);
state.cchip.csc = X64(3142444014157803);
state.dchip.drev = 0x01;
state.dchip.dsc = 0x43;
state.dchip.dsc2 = 0x03;
state.dchip.str = 0x25;
// initialize pchip data
for (i=0;i<2;i++)
{
memset(&state.pchip[i], 0, sizeof(struct SSys_state::SSys_pchip));
state.pchip[i].wsba[3] = 2;
}
state.pchip[0].pctl = X64(0000104401440081);
state.pchip[1].pctl = X64(0000504401440081);
state.tig.FwWrite = 0;
state.tig.HaltA = 0;
state.tig.HaltB = 0;
if(iNumMemoryBits > 30)
{
// size_t may not be big enough, and makes 2^31 negative, so the
// alloc fails. We're going to allocate the memory in
// 2^(iNumMemoryBits-10) chunks of 2^10.
CHECK_ALLOCATION(memory = calloc(1<<(iNumMemoryBits-10),1<<10));
}
else
CHECK_ALLOCATION(memory = calloc(1<<iNumMemoryBits,1));
printf("%s(%s): $Id: System.cpp,v 1.68 2008/03/04 19:05:21 iamcamiel Exp $\n",cfg->get_myName(),cfg->get_myValue());
}
/**
* Destructor. Calls the destructors for registered devices, and
* frees used memory.
**/
CSystem::~CSystem()
{
int i;
printf("Freeing memory in use by system...\n");
for (i=0;i<iNumComponents;i++)
delete acComponents[i];
for (i=0;i<iNumMemories;i++)
free(asMemories[i]);
free(memory);
}
/**
* free memory, and allocate and clear new memory.
**/
void CSystem::ResetMem(unsigned int membits) {
free(memory);
iNumMemoryBits=membits;
CHECK_ALLOCATION(memory = calloc(1<<iNumMemoryBits,1));
}
/**
* Register a device.
**/
int CSystem::RegisterComponent(CSystemComponent *component)
{
acComponents[iNumComponents] = component;
iNumComponents++;
return 0;
}
/**
* Get the number of bits that corresponds to the amount of RAM installed.
* (e.g. 28 = 256 MB, 29 = 512 MB, 30 = 1 GB)
**/
unsigned int CSystem::get_memory_bits()
{
return iNumMemoryBits;
}
/**
* Obtain a pointer to system memory.
**/
char * CSystem::PtrToMem(u64 address)
{
if (address>>iNumMemoryBits) // Non Memory
return 0;
return &(((char*)memory)[(int)address]);
}
/**
* Register a device as being a CPU. Return the CPU number.
**/
int CSystem::RegisterCPU(class CAlphaCPU * cpu)
{
if (iNumCPUs>=4)
return -1;
acCPUs[iNumCPUs] = cpu;
iNumCPUs++;
return iNumCPUs - 1;
}
/**
* Register a device as being clocked.
**/
int CSystem::RegisterClock(CSystemComponent *component, bool slow)
{
if (slow)
{
acSlowClocks[iNumSlowClocks] = component;
iNumSlowClocks++;
}
else
{
acFastClocks[iNumFastClocks] = component;
iNumFastClocks++;
}
return 0;
}
/**
* Reserve a range of the 64-bit system address space for a device.
**/
int CSystem::RegisterMemory(CSystemComponent *component, int index, u64 base, u64 length)
{
struct SMemoryUser * m;
int i;
for (i=0;i<iNumMemories;i++)
{
if ((asMemories[i]->component == component) && (asMemories[i]->index == index))
{
asMemories[i]->base = base;
asMemories[i]->length = length;
return 0;
}
}
CHECK_ALLOCATION(m = (struct SMemoryUser*) malloc(sizeof(struct SMemoryUser)));
m->component = component;
m->base = base;
m->length = length;
m->index = index;
asMemories[iNumMemories] = m;
iNumMemories++;
return 0;
}
int got_sigint = 0;
/**
* Handle a SIGINT by setting a flag that terminates the emulator.
**/
void sigint_handler (int signum)
{
got_sigint=1;
}
/**
* Run the system by clocking the CPU(s) and devices.
**/
int CSystem::Run()
{
int i,j,k;
int result;
/* catch CTRL-C and shutdown gracefully */
signal(SIGINT,&sigint_handler);
// start any threads...
for (i=0;i<iNumComponents;i++)
acComponents[i]->StartThreads();
for(k=0;!got_sigint;k++)
{
#if defined(CPU_THREADS)
sleep_ms(1);
#else
for(j=0;j<CLOCK_RATIO;j++)
{
for(i=0;i<iNumFastClocks;i++)
{
if (result = acFastClocks[i]->DoClock())
return result;
}
}
#endif
for(i=0;i<iNumSlowClocks;i++)
{
if (result = acSlowClocks[i]->DoClock())
return result;
}
#if !defined(HIDE_COUNTER)
#if defined(PROFILE)
printf("%d | %016" LL "x | %" LL "d profiled instructions. \r",k,acCPUs[0]->get_pc(),profiled_insts);
#else
printf("%d | %016" LL "x\r",k,acCPUs[0]->get_pc());
#endif
#endif
}
// stop any threads...
for (i=0;i<iNumComponents;i++)
acComponents[i]->StopThreads();
bool x = true;
while(x)
{
x = false;
for (i=0;i<iNumComponents;i++)
if (acComponents[i]->ActiveThreads())
{
x = true;
sleep_ms(1);
}
}
printf("%%SYS-W-SHUTDOWN: CTRL-C or Device Failed\n");
return 1;
}
/**
* Do one clock tick. The cpu(s) will execute one single instruction, and
* some devices may be clocked.
**/
int CSystem::SingleStep()
{
int i;
int result;
for(i=0;i<iNumFastClocks;i++)
{
result = acFastClocks[i]->DoClock();
if (result)
return result;
}
iSingleStep++;
#if defined(LS_MASTER) || defined(LS_SLAVE)
if (!(iSingleStep % 50))
{
lockstep_sync_m2s("sync1");
*dbg_strptr='\0';
lockstep_compare(debug_string);
dbg_strptr = debug_string;
*dbg_strptr='\0';
}
#endif
if (iSingleStep >= CLOCK_RATIO)
{
iSingleStep = 0;
for(i=0;i<iNumSlowClocks;i++)
{
result = acSlowClocks[i]->DoClock();
if (result)
return result;
}
#ifdef IDB
iSSCycles++;
#if !defined(LS_SLAVE)
if (bHashing)
#endif
printf("%d | %016" LL "x\r",iSSCycles,acCPUs[0]->get_pc());
#endif
}
return 0;
}
#ifdef DEBUG_PORTACCESS
u64 lastport;
#endif
/**
* \brief Write 8, 4, 2 or 1 byte(s) to a 64-bit system address. This could be memory,
* internal chipset registers, nothing or some device.
*
* Source: HRM, 10.1.1:
*
* System Space and Address Map
*
* The system address space is divided into two parts: system memory and PIO. This division
* is indicated by physical memory bit <43> = 1 for PIO accesses from the CPU, and
* by the PTP bit in the window registers for PTP accesses from the Pchip. While the operating
* system may choose bit <40> instead of bit <43> to represent PIO space, bit <43>
* is used throughout this chapter. In general, bits <42:35> are don’t cares if bit <43> is
* asserted.
*
* There is 16GB of PIO space available on the 21272 chipset with 8GB assigned to each
* Pchip. The Pchip supports up to bit <34> (35 bits total) of system address. However, the
* Version 1 Cchip only supports 4GB of system memory (32 bits total). As described in
* Chapter 6, the CAPbus protocol between the Pchip and Cchip does support up to bit
* <34>, as does the Cchip’s interface to the CPU. The Typhoon Cchip supports 32GB of
* system memory (35 bits total).
*
* The system address space is divided as shown in the following table:
*
* \code
* +-------------------+--------+-------------------------------+---------------------------------+
* | Space | Size | System Address <43:0> | Comments |
* +-------------------+--------+-------------------------------+---------------------------------+
* | System memory | 4GB | 000.0000.0000 - 000.FFFF.FFFF | Cacheable and prefetchable. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Reserved | 8188GB | 001.0000.0000 - 7FF.FFFF.FFFF | — |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Pchip0 PCI memory | 4GB | 800.0000.0000 - 800.FFFF.FFFF | Linear addressing. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | TIGbus | 1GB | 801.0000.0000 - 801.3FFF.FFFF | addr<5:0> = 0. Single byte |
* | | | | valid in quadword access. |
* | | | | 16MB accessible. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Reserved | 1GB | 801.4000.0000 - 801.7FFF.FFFF | — |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Pchip0 CSRs | 256MB | 801.8000.0000 - 801.8FFF.FFFF | addr<5:0> = 0. Quadword access. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Reserved | 256MB | 801.9000.0000 - 801.9FFF.FFFF | — |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Cchip CSRs | 256MB | 801.A000.0000 - 801.AFFF.FFFF | addr<5:0> = 0. Quadword access. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Dchip CSRs | 256MB | 801.B000.0000 - 801.BFFF.FFFF | addr<5:0> = 0. All eight bytes |
* | | | | in quadword access must be |
* | | | | identical. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Reserved | 768MB | 801.C000.0000 - 801.EFFF.FFFF | — |
* | Reserved | 128MB | 801.F000.0000 - 801.F7FF.FFFF | — |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Pchip 0 PCI IACK | 64MB | 801.F800.0000 - 801.FBFF.FFFF | Linear addressing. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Pchip0 PCI I/O | 32MB | 801.FC00.0000 - 801.FDFF.FFFF | Linear addressing. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Pchip0 PCI conf | 16MB | 801.FE00.0000 - 801.FEFF.FFFF | Linear addressing. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Reserved | 16MB | 801.FF00.0000 - 801.FFFF.FFFF | — |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Pchip1 PCI memory | 4GB | 802.0000.0000 - 802.FFFF.FFFF | Linear addressing. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Reserved | 2GB | 803.0000.0000 - 803.7FFF.FFFF | — |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Pchip1 CSRs | 256MB | 803.8000.0000 - 803.8FFF.FFFF | addr<5:0> = 0, quadword access. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Reserved | 1536MB | 803.9000.0000 - 803.EFFF.FFFF | — |
* | Reserved | 128MB | 803.F000.0000 - 803.F7FF.FFFF | — |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Pchip 1 PCI IACK | 64MB | 803.F800.0000 - 803.FBFF.FFFF | Linear addressing. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Pchip1 PCI I/O | 32MB | 803.FC00.0000 - 803.FDFF.FFFF | Linear addressing. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Pchip1 PCI conf | 16MB | 803.FE00.0000 - 803.FEFF.FFFF | Linear addressing. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Reserved | 16MB | 803.FF00.0000 - 803.FFFF.FFFF | — |
* | Reserved | 8172GB | 804.0000.0000 - FFF.FFFF.FFFF | Bits <42:35> are don’t cares if |
* | | | | bit <43> is asserted. |
* +-------------------+--------+-------------------------------+---------------------------------+
* \endcode
**/
void CSystem::WriteMem(u64 address, int dsize, u64 data,CSystemComponent * source)
{
u64 a;
int i;
u8 * p;
#if defined(ALIGN_MEM_ACCESS)
u64 t64;
u32 t32;
u16 t16;
#endif
a = address & X64(00000807ffffffff);
if (a>>iNumMemoryBits) // non-memory
{
// check registered device memory ranges
for(i=0;i<iNumMemories;i++)
{
if ( (a >= asMemories[i]->base)
&& (a < asMemories[i]->base + asMemories[i]->length) )
{
asMemories[i]->component->WriteMem(asMemories[i]->index, a-asMemories[i]->base, dsize, data);
return;
}
}
if ((a==X64(00000801FC000CF8)) && (dsize==32))
{
state.cf8_address[0] = (u32)data & 0x00ffffff;
return;
}
if ((a==X64(00000803FC000CF8)) && (dsize==32))
{
state.cf8_address[1] = (u32)data & 0x00ffffff;
return;
}
if ((a==X64(00000801FC000CFC)) && (dsize==32))
{
printf("PCI 0 config space write through CF8/CFC mechanism. \n");
getc(stdin);
WriteMem(X64(00000801FE000000) | state.cf8_address[0], dsize, data, source);
return;
}
if ((a==X64(00000803FC000CFC)) && (dsize==32))
{
printf("PCI 1 config space write through CF8/CFC mechanism. \n");
getc(stdin);
WriteMem(X64(00000803FE000000) | state.cf8_address[1], dsize, data, source);
return;
}
if (a>=X64(00000801A0000000) && a<=X64(00000801AFFFFFFF))
{
cchip_csr_write((u32)a&0xFFFFFFF,data);
return;
}
if (a>=X64(0000080180000000) && a<=X64(000008018FFFFFFF))
{
pchip_csr_write(0,(u32)a&0xFFFFFFF,data);
return;
}
if (a>=X64(0000080380000000) && a<=X64(000008038FFFFFFF))
{
pchip_csr_write(1,(u32)a&0xFFFFFFF,data);
return;
}
if (a>=X64(00000801B0000000) && a<=X64(00000801BFFFFFFF))
{
dchip_csr_write((u32)a&0xFFFFFFF,(u8)data&0xff);
return;
}
if (a>=X64(0000080100000000) && a<=X64(000008013FFFFFFF))
{
tig_write((u32)a&0x3FFFFFFF,(u8)data);
return;
}
if (a>=X64(801fc000000) && a<X64(801fe000000))
{
// Unused PCI I/O space
// if (source)
// printf("Write to unknown IO port %"LL"x on PCI 0 from %s \n",a & X64(1ffffff),source->devid_string);
// else
// printf("Write to unknown IO port %"LL"x on PCI 0 \n",a & X64(1ffffff));
return;
}
if (a>=X64(803fc000000) && a<X64(803fe000000))
{
// Unused PCI I/O space
if (source)
printf("Write to unknown IO port %"LL"x on PCI 1 from %s \n",a & X64(1ffffff),source->devid_string);
else
printf("Write to unknown IO port %"LL"x on PCI 1 \n",a & X64(1ffffff));
return;
}
if (a>=X64(80000000000) && a<X64(80100000000))
{
// Unused PCI memory space
u64 paddr = a & X64(ffffffff);
if(paddr > 0xb8fff || paddr < 0xb8000) { // skip legacy video
if (source)
printf("Write to unknown memory %"LL"x on PCI 0 from %s \n",a & X64(ffffffff),source->devid_string);
else
printf("Write to unknown memory %"LL"x on PCI 0 \n",a & X64(ffffffff));
}
}
if (a>=X64(80200000000) && a<X64(80300000000))
{
// Unused PCI memory space
if (source)
printf("Write to unknown memory %"LL"x on PCI 1 from %s \n",a & X64(ffffffff),source->devid_string);
else
printf("Write to unknown memory %"LL"x on PCI 1 \n",a & X64(ffffffff));
return;
}
#ifdef DEBUG_UNKMEM
if (source)
printf("Write to unknown memory %"LL"x from %s \n",a,source->devid_string);
else
printf("Write to unknown memory %"LL"x \n",a);
#endif
return;
}
p = (u8*)memory + a;
switch(dsize)
{
case 8:
*((u8 *) p) = (u8) data;
break;
case 16:
*((u16 *) p) = endian_16( (u16) data );
break;
case 32:
*((u32 *) p) = endian_32( (u32) data );
break;
default:
*((u64 *) p) = endian_64( (u64) data );
}
}
/**
* \brief Read 8, 4, 2 or 1 byte(s) from a 64-bit system address. This could be memory,
* internal chipset registers, nothing or some device.
*
* Source: HRM, 10.1.1:
*
* System Space and Address Map
*
* The system address space is divided into two parts: system memory and PIO. This division
* is indicated by physical memory bit <43> = 1 for PIO accesses from the CPU, and
* by the PTP bit in the window registers for PTP accesses from the Pchip. While the operating
* system may choose bit <40> instead of bit <43> to represent PIO space, bit <43>
* is used throughout this chapter. In general, bits <42:35> are don’t cares if bit <43> is
* asserted.
*
* There is 16GB of PIO space available on the 21272 chipset with 8GB assigned to each
* Pchip. The Pchip supports up to bit <34> (35 bits total) of system address. However, the
* Version 1 Cchip only supports 4GB of system memory (32 bits total). As described in
* Chapter 6, the CAPbus protocol between the Pchip and Cchip does support up to bit
* <34>, as does the Cchip’s interface to the CPU. The Typhoon Cchip supports 32GB of
* system memory (35 bits total).
*
* The system address space is divided as shown in the following table:
*
* \code
* +-------------------+--------+-------------------------------+---------------------------------+
* | Space | Size | System Address <43:0> | Comments |
* +-------------------+--------+-------------------------------+---------------------------------+
* | System memory | 4GB | 000.0000.0000 - 000.FFFF.FFFF | Cacheable and prefetchable. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Reserved | 8188GB | 001.0000.0000 - 7FF.FFFF.FFFF | — |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Pchip0 PCI memory | 4GB | 800.0000.0000 - 800.FFFF.FFFF | Linear addressing. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | TIGbus | 1GB | 801.0000.0000 - 801.3FFF.FFFF | addr<5:0> = 0. Single byte |
* | | | | valid in quadword access. |
* | | | | 16MB accessible. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Reserved | 1GB | 801.4000.0000 - 801.7FFF.FFFF | — |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Pchip0 CSRs | 256MB | 801.8000.0000 - 801.8FFF.FFFF | addr<5:0> = 0. Quadword access. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Reserved | 256MB | 801.9000.0000 - 801.9FFF.FFFF | — |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Cchip CSRs | 256MB | 801.A000.0000 - 801.AFFF.FFFF | addr<5:0> = 0. Quadword access. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Dchip CSRs | 256MB | 801.B000.0000 - 801.BFFF.FFFF | addr<5:0> = 0. All eight bytes |
* | | | | in quadword access must be |
* | | | | identical. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Reserved | 768MB | 801.C000.0000 - 801.EFFF.FFFF | — |
* | Reserved | 128MB | 801.F000.0000 - 801.F7FF.FFFF | — |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Pchip 0 PCI IACK | 64MB | 801.F800.0000 - 801.FBFF.FFFF | Linear addressing. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Pchip0 PCI I/O | 32MB | 801.FC00.0000 - 801.FDFF.FFFF | Linear addressing. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Pchip0 PCI conf | 16MB | 801.FE00.0000 - 801.FEFF.FFFF | Linear addressing. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Reserved | 16MB | 801.FF00.0000 - 801.FFFF.FFFF | — |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Pchip1 PCI memory | 4GB | 802.0000.0000 - 802.FFFF.FFFF | Linear addressing. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Reserved | 2GB | 803.0000.0000 - 803.7FFF.FFFF | — |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Pchip1 CSRs | 256MB | 803.8000.0000 - 803.8FFF.FFFF | addr<5:0> = 0, quadword access. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Reserved | 1536MB | 803.9000.0000 - 803.EFFF.FFFF | — |
* | Reserved | 128MB | 803.F000.0000 - 803.F7FF.FFFF | — |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Pchip 1 PCI IACK | 64MB | 803.F800.0000 - 803.FBFF.FFFF | Linear addressing. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Pchip1 PCI I/O | 32MB | 803.FC00.0000 - 803.FDFF.FFFF | Linear addressing. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Pchip1 PCI conf | 16MB | 803.FE00.0000 - 803.FEFF.FFFF | Linear addressing. |
* +-------------------+--------+-------------------------------+---------------------------------+
* | Reserved | 16MB | 803.FF00.0000 - 803.FFFF.FFFF | — |
* | Reserved | 8172GB | 804.0000.0000 - FFF.FFFF.FFFF | Bits <42:35> are don’t cares if |
* | | | | bit <43> is asserted. |
* +-------------------+--------+-------------------------------+---------------------------------+
* \endcode
**/
u64 CSystem::ReadMem(u64 address, int dsize, CSystemComponent * source)
{
u64 a;
int i;
u8 * p;
a = address & X64(00000807ffffffff);
if (a>>iNumMemoryBits) // Non Memory
{
// check registered device memory ranges
for(i=0;i<iNumMemories;i++)
{
if ( (a >= asMemories[i]->base)
&& (a < asMemories[i]->base + asMemories[i]->length) )
return asMemories[i]->component->ReadMem(asMemories[i]->index, a-asMemories[i]->base, dsize);
}
if ((a==X64(00000801FC000CFC)) && (dsize==32))
{
printf("PCI 0 config space read through CF8/CFC mechanism. \n");
getc(stdin);
return ReadMem(X64(00000801FE000000) | state.cf8_address[0], dsize, source);
}
if ((a==X64(00000803FC000CFC)) && (dsize==32))
{
printf("PCI 1 config space read through CF8/CFC mechanism. \n");
getc(stdin);
return ReadMem(X64(00000803FE000000) | state.cf8_address[1], dsize, source);
}
if (a>=X64(00000801A0000000) && a<=X64(00000801AFFFFFFF))
return cchip_csr_read((u32)a&0xFFFFFFF, source);
if (a>=X64(0000080180000000) && a<=X64(000008018FFFFFFF))
return pchip_csr_read(0,(u32)a&0xFFFFFFF);
if (a>=X64(0000080380000000) && a<=X64(000008038FFFFFFF))
return pchip_csr_read(1,(u32)a&0xFFFFFFF);
if (a>=X64(00000801B0000000) && a<=X64(00000801BFFFFFFF))
return dchip_csr_read((u32)a&0xFFFFFFF) * X64(0101010101010101);
if (a>=X64(0000080100000000) && a<=X64(000008013FFFFFFF))
return tig_read((u32)a&0x3FFFFFFF);
if ( (a>=X64(801fe000000) && a<X64(801ff000000))
|| (a>=X64(803fe000000) && a<X64(803ff000000)) )
{
// Unused PCI configuration space
switch(dsize)
{
case 8:
return X64_BYTE;
case 16:
return X64_WORD;
case 32:
return X64_LONG;
case 64:
return X64_QUAD;
}
}
if (a>=X64(800000c0000) && a<X64(801000e0000))
{
// Unused PCI ROM BIOS space
return 0;
}
if (a>=X64(801fc000000) && a<X64(801fe000000))
{
// Unused PCI I/O space