From 9cefa0a90c12baa1caad13563b451570400a64b2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matthias=20G=C3=B6rgens?= Date: Mon, 29 Apr 2024 12:52:50 +0800 Subject: [PATCH 1/4] Create dependabot.yml --- .github/dependabot.yml | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 .github/dependabot.yml diff --git a/.github/dependabot.yml b/.github/dependabot.yml new file mode 100644 index 0000000..53f8242 --- /dev/null +++ b/.github/dependabot.yml @@ -0,0 +1,6 @@ +version: 2 +updates: + - package-ecosystem: "cargo" + directory: "/" + schedule: + interval: "weekly" From e6a3eb34d3f45d0db6f31e8c76c8c9a8b4f58beb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matthias=20G=C3=B6rgens?= Date: Mon, 29 Apr 2024 12:59:00 +0800 Subject: [PATCH 2/4] Create CI workflow --- .github/workflows/rust.yml | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 .github/workflows/rust.yml diff --git a/.github/workflows/rust.yml b/.github/workflows/rust.yml new file mode 100644 index 0000000..b4d9512 --- /dev/null +++ b/.github/workflows/rust.yml @@ -0,0 +1,29 @@ +name: Rust + +on: + push: + branches: [ "main" ] + pull_request: + branches: + - "**" + +env: + CARGO_TERM_COLOR: always + +jobs: + test: + + runs-on: ubuntu-latest + + steps: + - uses: actions/checkout@v4 + - name: Check + run: cargo check + - name: Clippy + run: cargo clippy + - name: Format + run: cargo fmt --all --check + - name: Build + run: cargo build --verbose + - name: Run tests + run: cargo test --verbose From 70a95c650943fd7fc6cd5da467ff70f19a466d54 Mon Sep 17 00:00:00 2001 From: Matthias Goergens Date: Mon, 29 Apr 2024 13:00:21 +0800 Subject: [PATCH 3/4] Clippy automatic fixes --- rrs-cli/src/main.rs | 10 ++----- rrs-lib/src/csrs.rs | 45 ++++------------------------- rrs-lib/src/instruction_executor.rs | 2 +- rrs-lib/src/instruction_formats.rs | 2 +- rrs-lib/src/lib.rs | 4 +-- rrs-lib/src/memories.rs | 24 ++++----------- 6 files changed, 18 insertions(+), 69 deletions(-) diff --git a/rrs-cli/src/main.rs b/rrs-cli/src/main.rs index 40641a2..65b6b65 100644 --- a/rrs-cli/src/main.rs +++ b/rrs-cli/src/main.rs @@ -40,8 +40,8 @@ fn get_arg_matches() -> ArgMatches<'static> { .get_matches() } -fn process_u32_arg<'a>( - args: &ArgMatches<'a>, +fn process_u32_arg( + args: &ArgMatches<'_>, name: &str, base: u32, default: u32, @@ -123,11 +123,7 @@ impl Memory for SimulationCtrlDevice { } fn write_mem(&mut self, _addr: u32, _size: MemAccessSize, store_data: u32) -> bool { - if store_data != 0 { - self.stop = true; - } else { - self.stop = false; - } + self.stop = store_data != 0; true } diff --git a/rrs-lib/src/csrs.rs b/rrs-lib/src/csrs.rs index 4259b55..a245df9 100644 --- a/rrs-lib/src/csrs.rs +++ b/rrs-lib/src/csrs.rs @@ -156,17 +156,12 @@ impl CSR for MIsa { fn write(&mut self, _val: u32) {} } +#[derive(Default)] pub struct MVendorID { pub bank: u32, pub offset: u32, } -impl Default for MVendorID { - fn default() -> Self { - MVendorID { bank: 0, offset: 0 } - } -} - impl CSR for MVendorID { fn read(&self) -> u32 { (self.bank & 0x7f) | ((self.offset & 0x1ffffff) << 7) @@ -217,20 +212,12 @@ impl CSR for MStatus { } } +#[derive(Default)] pub struct MTVec { pub base: u32, pub vectored_mode: bool, } -impl Default for MTVec { - fn default() -> Self { - MTVec { - base: 0, - vectored_mode: false, - } - } -} - impl CSR for MTVec { fn read(&self) -> u32 { let mut read_data = self.base & 0xfffffffc; @@ -248,22 +235,13 @@ impl CSR for MTVec { } } +#[derive(Default)] pub struct MIx { pub external: bool, pub timer: bool, pub software: bool, } -impl Default for MIx { - fn default() -> Self { - MIx { - external: false, - timer: false, - software: false, - } - } -} - impl CSR for MIx { fn read(&self) -> u32 { let mut read_data = 0; @@ -290,20 +268,12 @@ impl CSR for MIx { } } +#[derive(Default)] pub struct MCountInhibit { pub cycle: bool, pub instret: bool, } -impl Default for MCountInhibit { - fn default() -> Self { - MCountInhibit { - cycle: false, - instret: false, - } - } -} - impl CSR for MCountInhibit { fn read(&self) -> u32 { let mut read_data = 0; @@ -339,16 +309,11 @@ pub enum ExceptionCause { ECallMMode = 0xb, } +#[derive(Default)] pub struct MCause { pub cause: u32, } -impl Default for MCause { - fn default() -> Self { - MCause { cause: 0 } - } -} - impl CSR for MCause { fn read(&self) -> u32 { self.cause diff --git a/rrs-lib/src/instruction_executor.rs b/rrs-lib/src/instruction_executor.rs index f1b4673..c336493 100644 --- a/rrs-lib/src/instruction_executor.rs +++ b/rrs-lib/src/instruction_executor.rs @@ -47,7 +47,7 @@ //! ); //! ``` -use super::csrs::{CSRAddr, ExceptionCause, MIx, PrivLevel}; +use super::csrs::{ExceptionCause, MIx, PrivLevel}; use super::instruction_formats; use super::process_instruction; use super::CSR; diff --git a/rrs-lib/src/instruction_formats.rs b/rrs-lib/src/instruction_formats.rs index 84a7ea5..f1eb8ce 100644 --- a/rrs-lib/src/instruction_formats.rs +++ b/rrs-lib/src/instruction_formats.rs @@ -455,7 +455,7 @@ mod tests { assert_eq!( UType::new(0xfffff037), UType { - imm: (0xfffff000 as u32) as i32, + imm: 0xfffff000_u32 as i32, rd: 0, } ); diff --git a/rrs-lib/src/lib.rs b/rrs-lib/src/lib.rs index 7545b84..1be5616 100644 --- a/rrs-lib/src/lib.rs +++ b/rrs-lib/src/lib.rs @@ -227,7 +227,7 @@ mod tests { use super::instruction_string_outputter::InstructionStringOutputter; use super::*; - fn run_insns<'a, M: Memory>(executor: &mut InstructionExecutor<'a, M>, end_pc: u32) { + fn run_insns(executor: &mut InstructionExecutor<'_, M>, end_pc: u32) { while executor.hart_state.pc != end_pc { let mut outputter = InstructionStringOutputter { insn_pc: executor.hart_state.pc, @@ -329,6 +329,6 @@ mod tests { assert_eq!(hart.csr_set.mscratch.val, 0xbaadf00d); assert_eq!(hart.csr_set.mtvec.base, 0x1234abc0); - assert_eq!(hart.csr_set.mtvec.vectored_mode, true); + assert!(hart.csr_set.mtvec.vectored_mode); } } diff --git a/rrs-lib/src/memories.rs b/rrs-lib/src/memories.rs index 951ee0f..a7189ab 100644 --- a/rrs-lib/src/memories.rs +++ b/rrs-lib/src/memories.rs @@ -245,17 +245,11 @@ mod tests { Some(0xbaadf00d) ); - assert_eq!(test_mem.write_mem(0x7, MemAccessSize::Byte, 0xff), true); + assert!(test_mem.write_mem(0x7, MemAccessSize::Byte, 0xff)); - assert_eq!( - test_mem.write_mem(0x2, MemAccessSize::HalfWord, 0xaaaaface), - true - ); + assert!(test_mem.write_mem(0x2, MemAccessSize::HalfWord, 0xaaaaface)); - assert_eq!( - test_mem.write_mem(0x1, MemAccessSize::Byte, 0x1234abcd), - true - ); + assert!(test_mem.write_mem(0x1, MemAccessSize::Byte, 0x1234abcd)); assert_eq!( test_mem.read_mem(0x0, MemAccessSize::Word), @@ -269,7 +263,7 @@ mod tests { assert_eq!(test_mem.read_mem(0x8, MemAccessSize::Word), None); - assert_eq!(test_mem.write_mem(0x8, MemAccessSize::Word, 0x0), false); + assert!(!test_mem.write_mem(0x8, MemAccessSize::Word, 0x0)); } struct TestMemory; @@ -341,15 +335,9 @@ mod tests { Some(0x44444444) ); - assert_eq!( - test_mem_space.write_mem(0x208, MemAccessSize::Word, 0xffffffff), - true - ); + assert!(test_mem_space.write_mem(0x208, MemAccessSize::Word, 0xffffffff)); - assert_eq!( - test_mem_space.write_mem(0x20c, MemAccessSize::Word, 0xffffffff), - false - ); + assert!(!test_mem_space.write_mem(0x20c, MemAccessSize::Word, 0xffffffff)); assert_eq!(test_mem_space.read_mem(0x108, MemAccessSize::Word), None); From 9a11b0c5cbf52a23ef0cfc95ea98228de6dd0fce Mon Sep 17 00:00:00 2001 From: Matthias Goergens Date: Mon, 29 Apr 2024 13:01:14 +0800 Subject: [PATCH 4/4] Use find as suggested by Clippy --- rrs-lib/src/memories.rs | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/rrs-lib/src/memories.rs b/rrs-lib/src/memories.rs index a7189ab..9bd319d 100644 --- a/rrs-lib/src/memories.rs +++ b/rrs-lib/src/memories.rs @@ -145,13 +145,9 @@ impl MemorySpace { // Gets the memory region that covers an address if it exists. fn get_memory_region_by_addr(&mut self, addr: u32) -> Option<&mut MemoryRegion> { - for memory_region in self.memory_regions.iter_mut() { - if (addr >= memory_region.base) && (addr < (memory_region.base + memory_region.size)) { - return Some(memory_region); - } - } - - None + self.memory_regions.iter_mut().find(|memory_region| { + (addr >= memory_region.base) && (addr < (memory_region.base + memory_region.size)) + }) } /// Add an inner memory.