From 0d6d727574141411058c9a206126969f31d46c5f Mon Sep 17 00:00:00 2001 From: unknown Date: Wed, 3 Apr 2024 19:50:10 +0900 Subject: [PATCH] add scala headers --- .scalafmt.conf | 2 +- build.sbt | 14 ++++---- project/metals.sbt | 2 +- project/project/metals.sbt | 2 +- project/project/project/metals.sbt | 2 +- src/main/scala/hwdbg/configs/configs.scala | 17 +++++++-- src/main/scala/hwdbg/libs/mem/init_mem.scala | 37 ++++++++++++++------ src/main/scala/top.scala | 31 +++++++++++----- 8 files changed, 76 insertions(+), 31 deletions(-) diff --git a/.scalafmt.conf b/.scalafmt.conf index 3381358..f1eddfe 100644 --- a/.scalafmt.conf +++ b/.scalafmt.conf @@ -1,2 +1,2 @@ -version = "3.5.9" +version = "3.8.1" runner.dialect = scala213 \ No newline at end of file diff --git a/build.sbt b/build.sbt index 87ec4f9..ae3c6cf 100644 --- a/build.sbt +++ b/build.sbt @@ -1,8 +1,8 @@ // See README.md for license details. -ThisBuild / scalaVersion := "2.13.12" -ThisBuild / version := "0.1.0" -ThisBuild / organization := "org.hyperdbg" +ThisBuild / scalaVersion := "2.13.12" +ThisBuild / version := "0.1.0" +ThisBuild / organization := "org.hyperdbg" val chiselVersion = "6.0.0" @@ -11,14 +11,16 @@ lazy val root = (project in file(".")) name := "hwdbg", libraryDependencies ++= Seq( "org.chipsalliance" %% "chisel" % chiselVersion, - "org.scalatest" %% "scalatest" % "3.2.16" % "test", + "org.scalatest" %% "scalatest" % "3.2.16" % "test" ), scalacOptions ++= Seq( "-language:reflectiveCalls", "-deprecation", "-feature", "-Xcheckinit", - "-Ymacro-annotations", + "-Ymacro-annotations" ), - addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full), + addCompilerPlugin( + "org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full + ) ) diff --git a/project/metals.sbt b/project/metals.sbt index cbb25c6..119c929 100644 --- a/project/metals.sbt +++ b/project/metals.sbt @@ -2,5 +2,5 @@ // This file enables sbt-bloop to create bloop config files. -addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.5.11") +addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.5.15") diff --git a/project/project/metals.sbt b/project/project/metals.sbt index cbb25c6..119c929 100644 --- a/project/project/metals.sbt +++ b/project/project/metals.sbt @@ -2,5 +2,5 @@ // This file enables sbt-bloop to create bloop config files. -addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.5.11") +addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.5.15") diff --git a/project/project/project/metals.sbt b/project/project/project/metals.sbt index cbb25c6..119c929 100644 --- a/project/project/project/metals.sbt +++ b/project/project/project/metals.sbt @@ -2,5 +2,5 @@ // This file enables sbt-bloop to create bloop config files. -addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.5.11") +addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.5.15") diff --git a/src/main/scala/hwdbg/configs/configs.scala b/src/main/scala/hwdbg/configs/configs.scala index 9c37f59..ea7af34 100644 --- a/src/main/scala/hwdbg/configs/configs.scala +++ b/src/main/scala/hwdbg/configs/configs.scala @@ -1,9 +1,22 @@ +/** @file + * configs.scala + * @author + * Sina Karvandi (sina@hyperdbg.org) + * @brief + * Configuration files + * @details + * @version 0.1 + * @date + * 2024-04-03 + * + * @copyright + * This project is released under the GNU Public License v3. + */ package hwdbg.configs import chisel3._ import chisel3.util._ - /** @brief * The constants for min-max tree */ @@ -45,4 +58,4 @@ object GeneralConfigurations { // Default number of bytes used in initialized SRAM memory // val DEFAULT_CONFIGURATION_INITIALIZED_MEMORY_SIZE: Int = 8192 // 8 KB -} \ No newline at end of file +} diff --git a/src/main/scala/hwdbg/libs/mem/init_mem.scala b/src/main/scala/hwdbg/libs/mem/init_mem.scala index 669cf7f..d5f705a 100644 --- a/src/main/scala/hwdbg/libs/mem/init_mem.scala +++ b/src/main/scala/hwdbg/libs/mem/init_mem.scala @@ -1,15 +1,32 @@ +/** @file + * init_mem.scala + * @author + * Sina Karvandi (sina@hyperdbg.org) + * @brief + * Initialize SRAM memory from a file + * @details + * @version 0.1 + * @date + * 2024-04-03 + * + * @copyright + * This project is released under the GNU Public License v3. + */ package hwdbg.libs.mem import chisel3._ import chisel3.util.experimental.loadMemoryFromFileInline +import hwdbg.configs._ + class InitMemInline( - debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG, - memoryFile: String = "", - addrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH, - width: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH, - size: Int = GeneralConfigurations.DEFAULT_CONFIGURATION_INITIALIZED_MEMORY_SIZE - ) extends Module { + debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG, + memoryFile: String = "", + addrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH, + width: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH, + size: Int = + GeneralConfigurations.DEFAULT_CONFIGURATION_INITIALIZED_MEMORY_SIZE +) extends Module { val io = IO(new Bundle { val enable = Input(Bool()) @@ -19,7 +36,7 @@ class InitMemInline( val dataOut = Output(UInt(width.W)) }) - val mem = SyncReadMem(size / width, UInt(width.W)) + val mem = SyncReadMem(size / width, UInt(width.W)) // // Initialize memory @@ -32,7 +49,7 @@ class InitMemInline( when(io.enable) { val rdwrPort = mem(io.addr) - when (io.write) { rdwrPort := io.dataIn } - .otherwise { io.dataOut := rdwrPort } + when(io.write) { rdwrPort := io.dataIn } + .otherwise { io.dataOut := rdwrPort } } -} \ No newline at end of file +} diff --git a/src/main/scala/top.scala b/src/main/scala/top.scala index c6a7857..fe068f4 100644 --- a/src/main/scala/top.scala +++ b/src/main/scala/top.scala @@ -1,3 +1,17 @@ +/** @file + * top.scala + * @author + * Sina Karvandi (sina@hyperdbg.org) + * @brief + * hwdbg's top module + * @details + * @version 0.1 + * @date + * 2024-04-03 + * + * @copyright + * This project is released under the GNU Public License v3. + */ package hwdbg import chisel3._ @@ -28,7 +42,7 @@ class DebuggerModule( // // Interrupt signals (lines) - // + // val plInSignal = Input(Bool()) // PS to PL signal val psOutInterrupt = Output(Bool()) // PL to PS interrupt @@ -38,12 +52,11 @@ class DebuggerModule( val rdAddr = Input(UInt(bramAddrWidth.W)) // read address val rdData = Output(UInt(bramDataWidth.W)) // read data val wrAddr = Input(UInt(bramAddrWidth.W)) // write address - val wrEna = Input(Bool()) // enable writing + val wrEna = Input(Bool()) // enable writing val wrData = Input(UInt(bramDataWidth.W)) // write data }) - } object Main extends App { @@ -54,18 +67,18 @@ object Main extends App { println( ChiselStage.emitSystemVerilog( new DebuggerModule( - DebuggerConfigurations.ENABLE_DEBUG, + DebuggerConfigurations.ENABLE_DEBUG, DebuggerConfigurations.NUMBER_OF_INPUT_PINS, DebuggerConfigurations.NUMBER_OF_OUTPUT_PINS, DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH, DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH ), firtoolOpts = Array( - "-disable-all-randomization", - "-strip-debug-info", - "--split-verilog", // The intention for this argument (and next argument) is to separate generated files. - "-o", - "generated/", + "-disable-all-randomization", + "-strip-debug-info", + "--split-verilog", // The intention for this argument (and next argument) is to separate generated files. + "-o", + "generated/" ) ) )