From 189edd2b806cd86cfb25d04860a024e98503cf2c Mon Sep 17 00:00:00 2001
From: Sina Karvandi <sina@hyperdbg.org>
Date: Fri, 3 May 2024 17:50:35 +0900
Subject: [PATCH] add check for ps_outInterrupt

---
 .../test_DebuggerModuleTestingBRAM.py                  | 10 +++++++---
 .../hwdbg/communication/interpreter/interpreter.scala  |  1 -
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/sim/hwdbg/DebuggerModuleTestingBRAM/test_DebuggerModuleTestingBRAM.py b/sim/hwdbg/DebuggerModuleTestingBRAM/test_DebuggerModuleTestingBRAM.py
index 642d85b..8f5fbcf 100644
--- a/sim/hwdbg/DebuggerModuleTestingBRAM/test_DebuggerModuleTestingBRAM.py
+++ b/sim/hwdbg/DebuggerModuleTestingBRAM/test_DebuggerModuleTestingBRAM.py
@@ -351,7 +351,9 @@ async def DebuggerModuleTestingBRAM_test(dut):
     clock_counter = 0
     interrupt_not_delivered = False
 
-    while dut.io_psOutInterrupt != 1:
+    while str(dut.io_psOutInterrupt) != "1":
+        
+        # print("State of interrupt: '" + str(dut.io_psOutInterrupt)+ "'")
 
         if clock_counter % 10 == 0:
             print("Number of clock cycles spent in debuggee (PL): " + str(clock_counter))
@@ -382,6 +384,8 @@ async def DebuggerModuleTestingBRAM_test(dut):
     print_bram_content(dut)
 
     #
-    # Check the final input on the next clock
+    # Check the final input on the next clock and run the circuit for a couple
+    # of more clock cycles
     #
-    await RisingEdge(dut.clock)
+    for _ in range(10):
+        await RisingEdge(dut.clock)
diff --git a/src/main/scala/hwdbg/communication/interpreter/interpreter.scala b/src/main/scala/hwdbg/communication/interpreter/interpreter.scala
index 9e1dac1..6d4e7c7 100644
--- a/src/main/scala/hwdbg/communication/interpreter/interpreter.scala
+++ b/src/main/scala/hwdbg/communication/interpreter/interpreter.scala
@@ -197,7 +197,6 @@ class DebuggerPacketInterpreter(
             // Configuration was done, send the response (result)
             //
             state := sSendResponse
-
           }
 
         }.otherwise {