make testing with cocotb

src/test/tb/Makefile → sim/Makefile

@@ -1,7 +1,7 @@
 # Makefile
 
 TOPLEVEL_LANG = verilog
-VERILOG_SOURCES = $(shell pwd)/../../../generated/DebuggerModuleTestingBRAM.sv
+VERILOG_SOURCES = $(shell pwd)/../generated/DebuggerModuleTestingBRAM.sv
 TOPLEVEL = DebuggerModuleTestingBRAM
 MODULE = test_DebuggerModuleTestingBRAM
 

sim/README.md → sim/modelsim/README.md

@@ -8,16 +8,16 @@ In the "modelsim.config" file, the first line that starts with "module:" is the
 
 For example:
 ```
-module:MinMaxParallelOnlineComparatorTest
+module:DebuggerModuleTest
 clock
-maxOutput_3 
+inputPin 
 ```
 
 If you don't specify the signals to be filtered, then **ALL** signals will be shown.
 
 For example:
 ```
-module:MinMaxParallelOnlineComparatorTest
+module:DebuggerModuleTest
 ```
 
 At last, run it with the following command:

sim/modelsim/modelsim.config

@@ -0,0 +1,3 @@
+module:DebuggerModuleTest
+io_inputPin
+io_outputPin

sim/modelsim/modelsim.tcl

@@ -0,0 +1,2 @@
+add wave -position insertpoint {*io_inputPin*}
+add wave -position insertpoint {*io_outputPin*}

src/test/tb/test_DebuggerModuleTestingBRAM.py → sim/test_DebuggerModuleTestingBRAM.py

@@ -28,6 +28,22 @@ async def DebuggerModuleTestingBRAM_test(dut):
     assert LogicArray(dut.io_outputPin_13.value) == LogicArray("X")
     assert LogicArray(dut.io_outputPin_14.value) == LogicArray("X")
     assert LogicArray(dut.io_outputPin_15.value) == LogicArray("X")
+    assert LogicArray(dut.io_outputPin_16.value) == LogicArray("X")
+    assert LogicArray(dut.io_outputPin_17.value) == LogicArray("X")
+    assert LogicArray(dut.io_outputPin_18.value) == LogicArray("X")
+    assert LogicArray(dut.io_outputPin_19.value) == LogicArray("X")
+    assert LogicArray(dut.io_outputPin_20.value) == LogicArray("X")
+    assert LogicArray(dut.io_outputPin_21.value) == LogicArray("X")
+    assert LogicArray(dut.io_outputPin_22.value) == LogicArray("X")
+    assert LogicArray(dut.io_outputPin_23.value) == LogicArray("X")
+    assert LogicArray(dut.io_outputPin_24.value) == LogicArray("X")
+    assert LogicArray(dut.io_outputPin_25.value) == LogicArray("X")
+    assert LogicArray(dut.io_outputPin_26.value) == LogicArray("X")
+    assert LogicArray(dut.io_outputPin_27.value) == LogicArray("X")
+    assert LogicArray(dut.io_outputPin_28.value) == LogicArray("X")
+    assert LogicArray(dut.io_outputPin_29.value) == LogicArray("X")
+    assert LogicArray(dut.io_outputPin_30.value) == LogicArray("X")
+    assert LogicArray(dut.io_outputPin_31.value) == LogicArray("X")
 
     # Set initial input value to prevent it from floating
     dut.io_inputPin_0.value = 0
@@ -46,6 +62,22 @@ async def DebuggerModuleTestingBRAM_test(dut):
     dut.io_inputPin_13.value = 0
     dut.io_inputPin_14.value = 0
     dut.io_inputPin_15.value = 0
+    dut.io_inputPin_16.value = 0
+    dut.io_inputPin_17.value = 0
+    dut.io_inputPin_18.value = 0
+    dut.io_inputPin_19.value = 0
+    dut.io_inputPin_20.value = 0
+    dut.io_inputPin_21.value = 0
+    dut.io_inputPin_22.value = 0
+    dut.io_inputPin_23.value = 0
+    dut.io_inputPin_24.value = 0
+    dut.io_inputPin_25.value = 0
+    dut.io_inputPin_26.value = 0
+    dut.io_inputPin_27.value = 0
+    dut.io_inputPin_28.value = 0
+    dut.io_inputPin_29.value = 0
+    dut.io_inputPin_30.value = 0
+    dut.io_inputPin_31.value = 0
 
     clock = Clock(dut.clock, 10, units="ns")  # Create a 10ns period clock on port clock
 

src/main/scala/hwdbg/configs/configs.scala

@@ -25,7 +25,7 @@ object DebuggerPorts {
   //
   // The following constant shows the key value object of the mappings
   // of pins to ports (used for inputs)
-  // For example,
+  //    For example,
   //                port 0 (in) -> contains 12 pins
   //                port 1 (in) -> contains 9 pins
   //                port 2 (in) -> contains 11 pins
@@ -35,7 +35,7 @@ object DebuggerPorts {
   //
   // The following constant shows the key value object of the mappings
   // of pins to ports (used for outputs)
-  // For example,
+  //    For example,
   //                port 0 (out) -> contains 12 pins
   //                port 1 (out) -> contains 9 pins
   //                port 2 (out) -> contains 11 pins

src/main/scala/top_test.scala

@@ -134,10 +134,9 @@ object MainWithInitializedBRAM extends App {
       ),
       firtoolOpts = Array(
         "-disable-all-randomization",
-        "-strip-debug-info",
-        "--split-verilog", // The intention for this argument (and next argument) is to separate generated files.
+        // "--split-verilog", // The intention for this argument (and next argument) is to separate generated files.
         "-o",
-        "generated/"
+        "generated/DebuggerModuleTestingBRAM.sv"
       )
     )
   )