diff --git a/sim/hwdbg/DebuggerModuleTestingBRAM/test_DebuggerModuleTestingBRAM.py b/sim/hwdbg/DebuggerModuleTestingBRAM/test_DebuggerModuleTestingBRAM.py
index 176a16e..4b63565 100644
--- a/sim/hwdbg/DebuggerModuleTestingBRAM/test_DebuggerModuleTestingBRAM.py
+++ b/sim/hwdbg/DebuggerModuleTestingBRAM/test_DebuggerModuleTestingBRAM.py
@@ -155,6 +155,8 @@ async def DebuggerModuleTestingBRAM_test(dut):
 
     # Tell the hwdbg to receive BRAM results
     dut.io_plInSignal.value = 1
+    await RisingEdge(dut.clock)
+    dut.io_plInSignal.value = 0
 
     # Set initial input value to prevent it from floating
     dut.io_inputPin_0.value = 1
@@ -193,13 +195,18 @@ async def DebuggerModuleTestingBRAM_test(dut):
     # Synchronize with the clock. This will regisiter the initial `inputPinX` value
     await RisingEdge(dut.clock)
     
-    expected_val = 0  # Matches initial input value
-    for i in range(10):
-        val = random.randint(0, 1)
-        dut.io_inputPin_0.value = val  # Assign the random value val to the input port d
+    #
+    # expected_val = 0  # Matches initial input value
+    # for i in range(10):
+    #     val = random.randint(0, 1)
+    #     dut.io_inputPin_0.value = val  # Assign the random value val to the input port d
+    #     await RisingEdge(dut.clock)
+    #     #assert dut.io_inputPin_0.value == expected_val, f"output q was incorrect on the {i}th cycle"
+    #     expected_val = val # Save random value for next RisingEdge
+
+    # Run the debugger for some times
+    for _ in range(100):
         await RisingEdge(dut.clock)
-        #assert dut.io_inputPin_0.value == expected_val, f"output q was incorrect on the {i}th cycle"
-        expected_val = val # Save random value for next RisingEdge
 
     # Check the final input on the next clock
     await RisingEdge(dut.clock)
diff --git a/src/main/scala/hwdbg/communication/interpreter/interpreter.scala b/src/main/scala/hwdbg/communication/interpreter/interpreter.scala
index e3a04dd..22d1bb9 100644
--- a/src/main/scala/hwdbg/communication/interpreter/interpreter.scala
+++ b/src/main/scala/hwdbg/communication/interpreter/interpreter.scala
@@ -122,7 +122,7 @@ class DebuggerPacketInterpreter(
           //
           // Remain at the same state (no action)
           //
-          state := sDone
+          state := sIdle
         }
 
       }
diff --git a/src/main/scala/hwdbg/configs/test_configs.scala b/src/main/scala/hwdbg/configs/test_configs.scala
index 2a8b093..b4bab22 100644
--- a/src/main/scala/hwdbg/configs/test_configs.scala
+++ b/src/main/scala/hwdbg/configs/test_configs.scala
@@ -24,6 +24,6 @@ import chisel3.util._
  */
 object TestingConfigurations {
 
-  val BRAM_INITIALIZATION_FILE_PATH: String = "./src/resources/8kb_BRAM.hex.txt"
+  val BRAM_INITIALIZATION_FILE_PATH: String = "./src/test/bram/send_version.hex.txt"
 
 }
diff --git a/src/main/scala/hwdbg/libs/mem/init_reg_mem_from_file.scala b/src/main/scala/hwdbg/libs/mem/init_reg_mem_from_file.scala
index 7b26374..9606d89 100644
--- a/src/main/scala/hwdbg/libs/mem/init_reg_mem_from_file.scala
+++ b/src/main/scala/hwdbg/libs/mem/init_reg_mem_from_file.scala
@@ -33,10 +33,12 @@ object InitRegMemFromFileTools {
     var counter: Int = 0
     val buffer = new ArrayBuffer[UInt]
     for (line <- Source.fromFile(path).getLines()) {
+
       val tokens: Array[String] = line.split("(//)").map(_.trim)
+
       if (tokens.nonEmpty && tokens.head != "") {
 
-        val i = Integer.parseInt(tokens.head, 16)
+        val i = Integer.parseInt(tokens.head.split(";")(0).trim, 16)
 
         LogInfo(debug)(
           f"Initialize memory [${counter}%x]: 0x${i}%x"
diff --git a/src/resources/8kb_BRAM.hex.txt b/src/test/bram/send_version.hex.txt
similarity index 53%
rename from src/resources/8kb_BRAM.hex.txt
rename to src/test/bram/send_version.hex.txt
index 941902f..5a7f87d 100644
--- a/src/resources/8kb_BRAM.hex.txt
+++ b/src/test/bram/send_version.hex.txt
@@ -1,68 +1,68 @@
-01020304
-05060708
-090a0b0c
-0d0e0f10
-11121314
-15161718
-191a1b1c
-1d1e1f20
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
+00000000 ; +0x0   | Checksum
+00000000 ; +0x4   | Checksum
+48595045 ; +0x8   | Indicator
+0d0e0f10 ; +0xc   | Indicator
+00000004 ; +0x10  | TypeOfThePacket - DEBUGGER_TO_DEBUGGEE_HARDWARE_LEVEL (0x4)
+00000000 ; +0x14  | RequestedActionOfThePacket - hwdbgActionSendVersion (0x0) 
+00000000 ; +0x18  |
+00000000 ; +0x1c  |
+00000000 ; +0x20  |
+00000000 ; +0x24  |
+00000000 ; +0x28  |
+00000000 ; +0x2c  |
+00000000 ; +0x30  |
+00000000 ; +0x34  |
+00000000 ; +0x38  |
+00000000 ; +0x3c  |
+00000000 ; +0x40  |
+00000000 ; +0x44  |
+00000000 ; +0x48  |
+00000000 ; +0x4c  |
+00000000 ; +0x50  |
+00000000 ; +0x54  |
+00000000 ; +0x58  |
+00000000 ; +0x5c  |
+00000000 ; +0x60  |
+00000000 ; +0x64  |
+00000000 ; +0x68  |
+00000000 ; +0x6c  |
+00000000 ; +0x70  |
+00000000 ; +0x74  |
+00000000 ; +0x78  |
+00000000 ; +0x7c  |
+00000000 ; +0x80  |
+00000000 ; +0x84  |
+00000000 ; +0x88  |
+00000000 ; +0x8c  |
+00000000 ; +0x90  |
+00000000 ; +0x94  |
+00000000 ; +0x98  |
+00000000 ; +0x9c  |
+00000000 ; +0xa0  |
+00000000 ; +0xa4  |
+00000000 ; +0xa8  |
+00000000 ; +0xac  |
+00000000 ; +0xb0  |
+00000000 ; +0xb4  |
+00000000 ; +0xb8  |
+00000000 ; +0xbc  |
+00000000 ; +0xc0  |
+00000000 ; +0xc4  |
+00000000 ; +0xc8  |
+00000000 ; +0xcc  |
+00000000 ; +0xd0  |
+00000000 ; +0xd4  |
+00000000 ; +0xd8  |
+00000000 ; +0xdc  |
+00000000 ; +0xe0  |
+00000000 ; +0xe4  |
+00000000 ; +0xe8  |
+00000000 ; +0xec  |
+00000000 ; +0xf0  |
+00000000 ; +0xf4  |
+00000000 ; +0xf8  |
+00000000 ; +0xfc  |
+00000000 ; +0x100 |
 00000000
 00000000
 00000000