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/** | ||
* @file | ||
* mux_2_to_1_io.scala | ||
* @author | ||
* Sina Karvandi ([email protected]) | ||
* @brief | ||
* Implementation of MUX 2 to 1 (I/O) | ||
* @details | ||
* @version 0.1 | ||
* @date | ||
* 2024-05-05 | ||
* | ||
* @copyright | ||
* This project is released under the GNU Public License v3. | ||
*/ | ||
package hwdbg.libs.mux | ||
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import chisel3._ | ||
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import hwdbg.configs._ | ||
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class Mux2To1IO( | ||
debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG | ||
) extends Module { | ||
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val io = IO(new Bundle { | ||
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val a = Input(Bool()) | ||
val b = Input(Bool()) | ||
val select = Input(Bool()) | ||
val out = Output(Bool()) | ||
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}) | ||
io.out := io.a & io.select | io.b & (~io.select) | ||
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} | ||
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object Mux2To1IO { | ||
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def apply( | ||
debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG | ||
)( | ||
a: Bool, | ||
b: Bool, | ||
select: Bool | ||
): (Bool) = { | ||
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val mux2To1IO = Module( | ||
new Mux2To1IO( | ||
debug | ||
) | ||
) | ||
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val out = Wire(Bool()) | ||
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// | ||
// Configure the input signals | ||
// | ||
mux2To1IO.io.a := a | ||
mux2To1IO.io.b := b | ||
mux2To1IO.io.select := select | ||
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// | ||
// Configure the output signals | ||
// | ||
out := mux2To1IO.io.out | ||
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// | ||
// Return the output result | ||
// | ||
out | ||
} | ||
} |
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