From 2e0a0550bb43de1eb5901f80f3ed0a290fa4b6f1 Mon Sep 17 00:00:00 2001
From: Sina Karvandi <sina@hyperdbg.org>
Date: Sun, 5 May 2024 20:49:16 +0900
Subject: [PATCH] add MUX 2 to 1 IO

---
 .../interpreter/port_information.scala        |  7 +-
 .../scala/hwdbg/libs/mux/mux_2_to_1_io.scala  | 73 +++++++++++++++++++
 src/test/bram/send_version.hex.txt            |  2 +-
 3 files changed, 80 insertions(+), 2 deletions(-)
 create mode 100644 src/main/scala/hwdbg/libs/mux/mux_2_to_1_io.scala

diff --git a/src/main/scala/hwdbg/communication/interpreter/port_information.scala b/src/main/scala/hwdbg/communication/interpreter/port_information.scala
index 4555be7..3155d55 100644
--- a/src/main/scala/hwdbg/communication/interpreter/port_information.scala
+++ b/src/main/scala/hwdbg/communication/interpreter/port_information.scala
@@ -131,8 +131,13 @@ class InterpreterPortInformation(
       is(sSendPortItems) {
 
         //
+        // Send input port items
         //
-        //
+        LogInfo(debug)("Iterating over input pins:")
+
+        inputPortsConfiguration.foreach { case (port, pins) =>
+          LogInfo(debug)(s"Port $port has $pins pins")
+        }
 
       }
     }
diff --git a/src/main/scala/hwdbg/libs/mux/mux_2_to_1_io.scala b/src/main/scala/hwdbg/libs/mux/mux_2_to_1_io.scala
new file mode 100644
index 0000000..a011d9c
--- /dev/null
+++ b/src/main/scala/hwdbg/libs/mux/mux_2_to_1_io.scala
@@ -0,0 +1,73 @@
+/**
+ * @file
+ *   mux_2_to_1_io.scala
+ * @author
+ *   Sina Karvandi (sina@hyperdbg.org)
+ * @brief
+ *   Implementation of MUX 2 to 1 (I/O)
+ * @details
+ * @version 0.1
+ * @date
+ *   2024-05-05
+ *
+ * @copyright
+ *   This project is released under the GNU Public License v3.
+ */
+package hwdbg.libs.mux
+
+import chisel3._
+
+import hwdbg.configs._
+
+class Mux2To1IO(
+    debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG
+) extends Module {
+
+  val io = IO(new Bundle {
+
+    val a = Input(Bool())
+    val b = Input(Bool())
+    val select = Input(Bool())
+    val out = Output(Bool())
+
+  })
+  io.out := io.a & io.select | io.b & (~io.select)
+
+}
+
+object Mux2To1IO {
+
+  def apply(
+      debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG
+  )(
+      a: Bool,
+      b: Bool,
+      select: Bool
+  ): (Bool) = {
+
+    val mux2To1IO = Module(
+      new Mux2To1IO(
+        debug
+      )
+    )
+
+    val out = Wire(Bool())
+
+    //
+    // Configure the input signals
+    //
+    mux2To1IO.io.a := a
+    mux2To1IO.io.b := b
+    mux2To1IO.io.select := select
+
+    //
+    // Configure the output signals
+    //
+    out := mux2To1IO.io.out
+
+    //
+    // Return the output result
+    //
+    out
+  }
+}
diff --git a/src/test/bram/send_version.hex.txt b/src/test/bram/send_version.hex.txt
index cdcc611..8e8b4b3 100644
--- a/src/test/bram/send_version.hex.txt
+++ b/src/test/bram/send_version.hex.txt
@@ -3,7 +3,7 @@
 52444247 ; +0x8   | Indicator
 48595045 ; +0xc   | Indicator
 00000004 ; +0x10  | TypeOfThePacket - DEBUGGER_TO_DEBUGGEE_HARDWARE_LEVEL (0x4)
-00008555 ; +0x14  | RequestedActionOfThePacket - hwdbgActionSendVersion (0x0) 
+00000001 ; +0x14  | RequestedActionOfThePacket - hwdbgActionSendVersion (0x0) 
 00000000 ; +0x18  |
 00000000 ; +0x1c  |
 00000000 ; +0x20  |