From 54bce68781cfac900ef64e2db4ea8e875297f77c Mon Sep 17 00:00:00 2001 From: Sina Karvandi Date: Mon, 8 Apr 2024 13:33:41 +0900 Subject: [PATCH] creating the interpreter module --- .../scala/hwdbg/interpreter/interpreter.scala | 148 ++++++++++++++++++ src/main/scala/hwdbg/libs/mem/init_mem.scala | 2 +- src/main/scala/hwdbg/main.scala | 3 +- .../scala/hwdbg/types/communication.scala | 44 ++++++ src/main/scala/top.scala | 1 - src/main/scala/top_test.scala | 1 - 6 files changed, 194 insertions(+), 5 deletions(-) create mode 100644 src/main/scala/hwdbg/interpreter/interpreter.scala create mode 100644 src/main/scala/hwdbg/types/communication.scala diff --git a/src/main/scala/hwdbg/interpreter/interpreter.scala b/src/main/scala/hwdbg/interpreter/interpreter.scala new file mode 100644 index 0000000..ba30fb1 --- /dev/null +++ b/src/main/scala/hwdbg/interpreter/interpreter.scala @@ -0,0 +1,148 @@ +/** @file + * interpreter.scala + * @author + * Sina Karvandi (sina@hyperdbg.org) + * @brief + * Remote debugger packet interpreter module + * @details + * @version 0.1 + * @date + * 2024-04-08 + * + * @copyright + * This project is released under the GNU Public License v3. + */ +package hwdbg.interpreter + +import chisel3._ +import circt.stage.ChiselStage + +import hwdbg.configs._ +import hwdbg.types._ + +class DebuggerPacketInterpreter( + debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG, + numberOfInputPins: Int = DebuggerConfigurations.NUMBER_OF_INPUT_PINS, + numberOfOutputPins: Int = DebuggerConfigurations.NUMBER_OF_OUTPUT_PINS, + bramAddrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH, + bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH +) extends Module { + val io = IO(new Bundle { + + // + // Chip signals + // + val en = Input(Bool()) // chip enable signal + + // + // Input/Output signals + // + val inputPin = Input(Vec(numberOfInputPins, UInt((1.W)))) // input pins + val outputPin = Output(Vec(numberOfOutputPins, UInt((1.W)))) // output pins + + // + // Interrupt signals (lines) + // + val plInSignal = Input(Bool()) // PS to PL signal + val psOutInterrupt = Output(Bool()) // PL to PS interrupt + + // + // BRAM (Block RAM) ports + // + val rdWrAddr = Output(UInt(bramAddrWidth.W)) // read/write address + val rdData = Input(UInt(bramDataWidth.W)) // read data + val wrEna = Output(Bool()) // enable writing + val wrData = Output(UInt(bramDataWidth.W)) // write data + + // + // Interpretation signals + // + val interpretationDone = Output(Bool()) // interpretation done or not? + val foundValidPacket = Output(Bool()) // packet was valid or not + val requestedActionOfThePacket = Output(UInt(32.W)) // the requested action + + }) + + /* + val receivedPacketBuffer = Wire(new DebuggerRemotePacket()) + receivedPacketBuffer.key := io.key + receivedPacketBuffer.value := io.value + io.struct_key := ms.key + io.struct_value := ms.value + */ + +} + +object DebuggerPacketInterpreter { + + def apply( + debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG, + numberOfInputPins: Int = DebuggerConfigurations.NUMBER_OF_INPUT_PINS, + numberOfOutputPins: Int = DebuggerConfigurations.NUMBER_OF_OUTPUT_PINS, + bramAddrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH, + bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH + )( + en: Bool, + inputPin: Vec[UInt], + plInSignal: Bool, + rdData: UInt + ): (Vec[UInt], Bool, UInt, Bool, UInt, Bool, Bool, UInt) = { + + val debuggerPacketInterpreter = Module( + new DebuggerPacketInterpreter( + debug, + numberOfInputPins, + numberOfOutputPins, + bramAddrWidth, + bramDataWidth + ) + ) + + val outputPin = Wire(Vec(numberOfOutputPins, UInt((1.W)))) + val psOutInterrupt = Wire(Bool()) + val rdWrAddr = Wire(UInt(bramAddrWidth.W)) + val wrEna = Wire(Bool()) + val wrData = Wire(UInt(bramDataWidth.W)) + val interpretationDone = Wire(Bool()) + val foundValidPacket = Wire(Bool()) + val requestedActionOfThePacket = Wire(UInt(32.W)) + + // + // Configure the input signals + // + debuggerPacketInterpreter.io.en := en + debuggerPacketInterpreter.io.inputPin := inputPin + debuggerPacketInterpreter.io.plInSignal := plInSignal + debuggerPacketInterpreter.io.rdData := rdData + + // + // Configure the output signals + // + outputPin := debuggerPacketInterpreter.io.outputPin + psOutInterrupt := debuggerPacketInterpreter.io.psOutInterrupt + rdWrAddr := debuggerPacketInterpreter.io.rdWrAddr + wrEna := debuggerPacketInterpreter.io.wrEna + wrData := debuggerPacketInterpreter.io.wrData + + // + // Configure the output signals related to interpreted packets + // + interpretationDone := debuggerPacketInterpreter.io.interpretationDone + foundValidPacket := debuggerPacketInterpreter.io.foundValidPacket + requestedActionOfThePacket := debuggerPacketInterpreter.io.requestedActionOfThePacket + + // + // Return the output result + // + ( + outputPin, + psOutInterrupt, + rdWrAddr, + wrEna, + wrData, + interpretationDone, + foundValidPacket, + requestedActionOfThePacket + ) + } +} diff --git a/src/main/scala/hwdbg/libs/mem/init_mem.scala b/src/main/scala/hwdbg/libs/mem/init_mem.scala index d8b1f0d..b4102d4 100644 --- a/src/main/scala/hwdbg/libs/mem/init_mem.scala +++ b/src/main/scala/hwdbg/libs/mem/init_mem.scala @@ -91,7 +91,7 @@ object InitMemInline { initMemInlineModule.io.dataIn := dataIn // - // Configure the input signals + // Configure the output signals // dataOut := initMemInlineModule.io.dataOut diff --git a/src/main/scala/hwdbg/main.scala b/src/main/scala/hwdbg/main.scala index 94fdbe9..8389312 100644 --- a/src/main/scala/hwdbg/main.scala +++ b/src/main/scala/hwdbg/main.scala @@ -15,7 +15,6 @@ package hwdbg import chisel3._ -import chisel3.util.Counter import circt.stage.ChiselStage import hwdbg.configs._ @@ -109,7 +108,7 @@ object DebuggerMain { debuggerMainModule.io.rdData := rdData // - // Configure the input signals + // Configure the output signals // outputPin := debuggerMainModule.io.outputPin psOutInterrupt := debuggerMainModule.io.psOutInterrupt diff --git a/src/main/scala/hwdbg/types/communication.scala b/src/main/scala/hwdbg/types/communication.scala new file mode 100644 index 0000000..afd9e70 --- /dev/null +++ b/src/main/scala/hwdbg/types/communication.scala @@ -0,0 +1,44 @@ +/** @file + * communication.scala + * @author + * Sina Karvandi (sina@hyperdbg.org) + * @brief + * Data types for the communication + * @details + * @version 0.1 + * @date + * 2024-04-08 + * + * @copyright + * This project is released under the GNU Public License v3. + */ +package hwdbg.types + +import chisel3._ + +/* +Structure in C: + +typedef struct _DEBUGGER_REMOTE_PACKET +{ + BYTE Checksum; + UINT64 Indicator; /* Shows the type of the packet */ + DEBUGGER_REMOTE_PACKET_TYPE TypeOfThePacket; + DEBUGGER_REMOTE_PACKET_REQUESTED_ACTION RequestedActionOfThePacket; + +} DEBUGGER_REMOTE_PACKET, *PDEBUGGER_REMOTE_PACKET; + + */ + +/** @brief + * The packet used for communication with the remote debugger + */ +class DebuggerRemotePacket() extends Bundle { + val Checksum = UInt(8.W) // 1 bytes + val Alignment0 = UInt((64 - 8).W) // 7 bytes + val Indicator = UInt(64.W) // 8 bytes + val TypeOfThePacket = UInt(32.W) // 4 bytes + val RequestedActionOfThePacket = UInt(32.W) // 4 bytes +} + +// ----------------------------------------------------------------------- diff --git a/src/main/scala/top.scala b/src/main/scala/top.scala index 7081f0a..e340b37 100644 --- a/src/main/scala/top.scala +++ b/src/main/scala/top.scala @@ -13,7 +13,6 @@ * This project is released under the GNU Public License v3. */ import chisel3._ -import chisel3.util.Counter import circt.stage.ChiselStage import hwdbg._ diff --git a/src/main/scala/top_test.scala b/src/main/scala/top_test.scala index 7977804..d52eeed 100644 --- a/src/main/scala/top_test.scala +++ b/src/main/scala/top_test.scala @@ -13,7 +13,6 @@ * This project is released under the GNU Public License v3. */ import chisel3._ -import chisel3.util.Counter import circt.stage.ChiselStage import hwdbg._