From 66a8f3ef6038cfa7ea99b1db0b4522e45d8a8127 Mon Sep 17 00:00:00 2001
From: Sina Karvandi <sina@hyperdbg.org>
Date: Sun, 14 Apr 2024 23:01:13 +0900
Subject: [PATCH] infer register as memory (for testing bram)

---
 src/main/scala/hwdbg/configs/configs.scala    |   2 +-
 .../hwdbg/libs/mem/init_mem_content.scala     | 115 ++++++++++++++++++
 src/main/scala/hwdbg/main.scala               |  15 ++-
 src/main/scala/top_test.scala                 |   2 +-
 4 files changed, 129 insertions(+), 5 deletions(-)
 create mode 100644 src/main/scala/hwdbg/libs/mem/init_mem_content.scala

diff --git a/src/main/scala/hwdbg/configs/configs.scala b/src/main/scala/hwdbg/configs/configs.scala
index acf2b0b..6c0fec1 100644
--- a/src/main/scala/hwdbg/configs/configs.scala
+++ b/src/main/scala/hwdbg/configs/configs.scala
@@ -66,5 +66,5 @@ object GeneralConfigurations {
 object TestingConfigurations {
 
   val BRAM_INITIALIZATION_FILE_PATH: String =
-    "src/main/resources/8kb_BRAM.hex.txt"
+    "/home/sina/HyperDbg/hwdbg/src/resources/8kb_BRAM.hex.txt"
 }
diff --git a/src/main/scala/hwdbg/libs/mem/init_mem_content.scala b/src/main/scala/hwdbg/libs/mem/init_mem_content.scala
new file mode 100644
index 0000000..0d83b13
--- /dev/null
+++ b/src/main/scala/hwdbg/libs/mem/init_mem_content.scala
@@ -0,0 +1,115 @@
+/** @file
+  *   init_mem_content.scala
+  * @author
+  *   Sina Karvandi (sina@hyperdbg.org)
+  * @brief
+  *   Initialize SRAM memory from a file (directly from the content of file)
+  * @details
+  * @version 0.1
+  * @date
+  *   2024-04-14
+  *
+  * @copyright
+  *   This project is released under the GNU Public License v3.
+  */
+package hwdbg.libs.mem
+
+import scala.collection.mutable.ArrayBuffer
+import scala.io.Source
+
+import chisel3._
+
+import hwdbg.configs._
+
+object Tools {
+  def readmemh(path: String, width: Int): Seq[UInt] = {
+    val buffer = new ArrayBuffer[UInt]
+    for (line <- Source.fromFile(path).getLines()) {
+      val tokens: Array[String] = line.split("(//)").map(_.trim)
+      if (tokens.nonEmpty && tokens.head != "") {
+        val i = Integer.parseInt(tokens.head, 16)
+        buffer.append(i.U(width.W))
+      }
+    }
+    buffer.toSeq
+  }
+}
+
+class InitMemContent(
+    debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
+    memoryFile: String = TestingConfigurations.BRAM_INITIALIZATION_FILE_PATH,
+    addrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
+    width: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH,
+    size: Int =
+      GeneralConfigurations.DEFAULT_CONFIGURATION_INITIALIZED_MEMORY_SIZE
+) extends Module {
+
+  val io = IO(new Bundle {
+    val enable = Input(Bool())
+    val write = Input(Bool())
+    val addr = Input(UInt(addrWidth.W))
+    val dataIn = Input(UInt(width.W))
+    val dataOut = Output(UInt(width.W))
+  })
+
+  val mem = RegInit(VecInit(Tools.readmemh(memoryFile, width)))
+
+  when(io.enable) {
+    val rdwrPort = mem(io.addr)
+    io.dataOut := rdwrPort
+
+    when(io.write) {
+      mem(io.addr) := io.dataIn
+    }
+  }.otherwise {
+    io.dataOut := 0.U
+  }
+}
+
+object InitMemContent {
+
+  def apply(
+      debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
+      memoryFile: String = TestingConfigurations.BRAM_INITIALIZATION_FILE_PATH,
+      addrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
+      width: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH,
+      size: Int =
+        GeneralConfigurations.DEFAULT_CONFIGURATION_INITIALIZED_MEMORY_SIZE
+  )(
+      enable: Bool,
+      write: Bool,
+      addr: UInt,
+      dataIn: UInt
+  ): UInt = {
+
+    val initMemContentModule = Module(
+      new InitMemContent(
+        debug,
+        memoryFile,
+        addrWidth,
+        width,
+        size
+      )
+    )
+
+    val dataOut = Wire(UInt(width.W))
+
+    //
+    // Configure the input signals
+    //
+    initMemContentModule.io.enable := enable
+    initMemContentModule.io.write := write
+    initMemContentModule.io.addr := addr
+    initMemContentModule.io.dataIn := dataIn
+
+    //
+    // Configure the output signals
+    //
+    dataOut := initMemContentModule.io.dataOut
+
+    //
+    // Return the output result
+    //
+    dataOut
+  }
+}
diff --git a/src/main/scala/hwdbg/main.scala b/src/main/scala/hwdbg/main.scala
index 2c92919..2f07d02 100644
--- a/src/main/scala/hwdbg/main.scala
+++ b/src/main/scala/hwdbg/main.scala
@@ -82,11 +82,20 @@ class DebuggerMain(
     io.outputPin(i) := requestedActionOfThePacket(i)
   }
 
+  //
+  // Used to force chisel not to ignore the write pin of BRAM
+  //
+  when(interpretationDone && foundValidPacket) {
+    io.wrEna := true.B
+    io.wrData := requestedActionOfThePacket
+
+  }.otherwise {
+    io.wrEna := false.B
+    io.wrData := 0.U
+  }
+
   io.rdWrAddr := rdWrAddr
-  io.wrEna := false.B
-  io.wrData := 0.U
   io.psOutInterrupt := false.B // For now, just assert false
-
 }
 
 object DebuggerMain {
diff --git a/src/main/scala/top_test.scala b/src/main/scala/top_test.scala
index 14337c8..661accf 100644
--- a/src/main/scala/top_test.scala
+++ b/src/main/scala/top_test.scala
@@ -64,7 +64,7 @@ class DebuggerModuleTestingBRAM(
   // Instantiate the BRAM memory initializer module
   //
   val dataOut =
-    InitMemInline(
+    InitMemContent(
       debug,
       TestingConfigurations.BRAM_INITIALIZATION_FILE_PATH,
       bramAddrWidth,