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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,139 @@ | ||
| /** | ||
| * @file | ||
| * exec.scala | ||
| * @author | ||
| * Sina Karvandi ([email protected]) | ||
| * @brief | ||
| * Script execution engine | ||
| * @details | ||
| * @version 0.1 | ||
| * @date | ||
| * 2024-05-07 | ||
| * | ||
| * @copyright | ||
| * This project is released under the GNU Public License v3. | ||
| */ | ||
| package hwdbg.exec | ||
|
|
||
| import chisel3._ | ||
| import chisel3.util._ | ||
|
|
||
| import hwdbg.configs._ | ||
| import hwdbg.stage._ | ||
|
|
||
| class ScriptExec( | ||
| debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG, | ||
| numberOfPins: Int = DebuggerConfigurations.NUMBER_OF_PINS, | ||
| maximumNumberOfStages: Int = DebuggerConfigurations.MAXIMUM_NUMBER_OF_STAGES, | ||
| bramAddrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH, | ||
| bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH, | ||
| portsConfiguration: Map[Int, Int] = DebuggerPorts.PORT_PINS_MAP | ||
| ) extends Module { | ||
|
|
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| val io = IO(new Bundle { | ||
|
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| // | ||
| // Chip signals | ||
| // | ||
| val en = Input(Bool()) // chip enable signal | ||
|
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| // | ||
| // Input/Output signals | ||
| // | ||
| val inputPin = Input(Vec(numberOfPins, UInt((1.W)))) // input pins | ||
| val outputPin = Output(Vec(numberOfPins, UInt((1.W)))) // output pins | ||
| }) | ||
|
|
||
| // | ||
| // Output pins | ||
| // | ||
| val outputPin = Wire(Vec(numberOfPins, UInt((1.W)))) | ||
|
|
||
| // | ||
| // Stage registers | ||
| // | ||
| val stageRegs = Reg(new StageRegisters(debug, numberOfPins, maximumNumberOfStages)) | ||
|
|
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| // ----------------------------------------------------------------------- | ||
| // | ||
| // *** Move each register (input vector) to the next stage at each clock *** | ||
| // | ||
| for (i <- 0 until maximumNumberOfStages) { | ||
|
|
||
| if (i == 0) { | ||
|
|
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| // | ||
| // At the first stage, the input registers should be passed to the | ||
| // first registers set of the stage registers | ||
| // | ||
| stageRegs.pinValues(i) := io.inputPin | ||
|
|
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| } else if (i == (maximumNumberOfStages - 1)) { | ||
|
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| // | ||
| // At the last stage, the state registers should be passed to the output | ||
| // | ||
| outputPin := stageRegs.pinValues(i) | ||
|
|
||
| } else { | ||
|
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| // | ||
| // At the normal (middle) stage, the state registers should be passed to | ||
| // the next level of stage registers | ||
| // | ||
| stageRegs.pinValues(i + 1) := stageRegs.pinValues(i) | ||
| } | ||
| } | ||
| // ----------------------------------------------------------------------- | ||
|
|
||
| // | ||
| // Connect the output signals | ||
| // | ||
| io.outputPin := outputPin | ||
|
|
||
| } | ||
|
|
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| object ScriptExec { | ||
|
|
||
| def apply( | ||
| debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG, | ||
| numberOfPins: Int = DebuggerConfigurations.NUMBER_OF_PINS, | ||
| maximumNumberOfStages: Int = DebuggerConfigurations.MAXIMUM_NUMBER_OF_STAGES, | ||
| bramAddrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH, | ||
| bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH, | ||
| portsConfiguration: Map[Int, Int] = DebuggerPorts.PORT_PINS_MAP | ||
| )( | ||
| en: Bool, | ||
| inputPin: Vec[UInt] | ||
| ): (Vec[UInt]) = { | ||
|
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| val scriptExecModule = Module( | ||
| new ScriptExec( | ||
| debug, | ||
| numberOfPins, | ||
| maximumNumberOfStages, | ||
| bramAddrWidth, | ||
| bramDataWidth, | ||
| portsConfiguration | ||
| ) | ||
| ) | ||
|
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| val outputPin = Wire(Vec(numberOfPins, UInt((1.W)))) | ||
|
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| // | ||
| // Configure the input signals | ||
| // | ||
| scriptExecModule.io.en := en | ||
| scriptExecModule.io.inputPin := inputPin | ||
|
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| // | ||
| // Configure the output signals | ||
| // | ||
| outputPin := scriptExecModule.io.outputPin | ||
|
|
||
| // | ||
| // Return the output result | ||
| // | ||
| outputPin | ||
| } | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,28 @@ | ||
| /** | ||
| * @file | ||
| * stage.scala | ||
| * @author | ||
| * Sina Karvandi ([email protected]) | ||
| * @brief | ||
| * Data types related to stage registers | ||
| * @details | ||
| * @version 0.1 | ||
| * @date | ||
| * 2024-05-07 | ||
| * | ||
| * @copyright | ||
| * This project is released under the GNU Public License v3. | ||
| */ | ||
| package hwdbg.stage | ||
|
|
||
| import chisel3._ | ||
|
|
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| import hwdbg.configs._ | ||
|
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| class StageRegisters( | ||
| debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG, | ||
| numberOfPins: Int = DebuggerConfigurations.NUMBER_OF_PINS, | ||
| maximumNumberOfStages: Int = DebuggerConfigurations.MAXIMUM_NUMBER_OF_STAGES | ||
| ) extends Bundle { | ||
| val pinValues = Vec(maximumNumberOfStages, UInt(numberOfPins.W)) | ||
| } |
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