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add working version of port information sender
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@SinaKarvandi
SinaKarvandi committed May 6, 2024
1 parent 68cd5a1 commit 78e8ae5
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Showing 7 changed files with 66 additions and 188 deletions.
124 changes: 24 additions & 100 deletions src/main/scala/hwdbg/communication/interpreter/port_information.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -25,15 +25,14 @@ import hwdbg.utils._

object InterpreterPortInformationEnums {
object State extends ChiselEnum {
val sIdle, sSendCountOfInputPorts, sSendCountOfOutputPorts, sSendInputPortItems, sSendOutputPortItems, sDone = Value
val sIdle, sSendCountOfPorts, sSendPortItems, sDone = Value
}
}

class InterpreterPortInformation(
debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH,
inputPortsConfiguration: Map[Int, Int] = DebuggerPorts.PORT_PINS_MAP_INPUT,
outputPortsConfiguration: Map[Int, Int] = DebuggerPorts.PORT_PINS_MAP_OUTPUT
portsConfiguration: Map[Int, Int] = DebuggerPorts.PORT_PINS_MAP
) extends Module {

//
Expand Down Expand Up @@ -66,25 +65,18 @@ class InterpreterPortInformation(
//
// Get number of input/output ports
//
val numberOfInputPorts = inputPortsConfiguration.size
val numberOfOutputPorts = outputPortsConfiguration.size
val numberOfPorts = portsConfiguration.size

//
// Convert input port pins into vector
//
// val inputPinsVec = VecInit(inputPortsConfiguration.values.toSeq.map(_.U))
val inputPinsVec = RegInit(VecInit(Seq.fill(numberOfInputPorts)(0.U(bramDataWidth.W))))
// val pinsVec = VecInit(portsConfiguration.values.toSeq.map(_.U))
val pinsVec = RegInit(VecInit(Seq.fill(numberOfPorts)(0.U(bramDataWidth.W))))

//
// Convert output port pins into vector
// Determine the width for numberOfSentPins
//
// val outputPinsVec = VecInit(outputPortsConfiguration.values.toSeq.map(_.U))
val outputPinsVec = RegInit(VecInit(Seq.fill(numberOfOutputPorts)(0.U(bramDataWidth.W))))

//
// Determine the width for numberOfSentPins based on conditions
//
val numberOfSentPinsWidth = if (numberOfInputPorts > numberOfOutputPorts) log2Ceil(numberOfInputPorts) else log2Ceil(numberOfOutputPorts)
val numberOfSentPinsWidth = log2Ceil(numberOfPorts)

//
// Registers for keeping track of sent pin details
Expand All @@ -110,16 +102,16 @@ class InterpreterPortInformation(
//
// Going to the next state (sending count of input ports)
//
state := sSendCountOfInputPorts
state := sSendCountOfPorts
}
is(sSendCountOfInputPorts) {
is(sSendCountOfPorts) {

//
// Send count of input ports
// Send count of input.output ports
//
LogInfo(debug)("Number of input ports (PORT_PINS_MAP_INPUT): " + numberOfInputPorts)
LogInfo(debug)("Number of ports (PORT_PINS_MAP): " + numberOfPorts)

sendingData := numberOfInputPorts.U
sendingData := numberOfPorts.U

//
// Data is valid
Expand All @@ -131,48 +123,18 @@ class InterpreterPortInformation(
//
LogInfo(debug)("Iterating over input pins:")

inputPortsConfiguration.foreach { case (port, pins) =>
portsConfiguration.foreach { case (port, pins) =>
LogInfo(debug)(s"Port $port has $pins pins")
inputPinsVec(port) := pins.U
pinsVec(port) := pins.U
}

//
// Going to the next state (sending count of input ports)
//
state := sSendCountOfOutputPorts
state := sSendPortItems

}
is(sSendCountOfOutputPorts) {

//
// Send count of output ports
//
LogInfo(debug)("Number of output ports (PORT_PINS_MAP_OUTPUT): " + numberOfOutputPorts)

sendingData := numberOfOutputPorts.U

//
// Data is valid
//
dataValidOutput := true.B

//
// Fill the port info
//
LogInfo(debug)("Iterating over output pins:")

outputPortsConfiguration.foreach { case (port, pins) =>
LogInfo(debug)(s"Port $port has $pins pins")
outputPinsVec(port) := pins.U
}

//
// Next, we gonna send each ports' information ()
//
state := sSendInputPortItems

}
is(sSendInputPortItems) {
is(sSendPortItems) {

//
// Send input port items
Expand All @@ -181,56 +143,17 @@ class InterpreterPortInformation(
//
// Adjust data
//
sendingData := inputPinsVec(numberOfSentPins)
sendingData := pinsVec(numberOfSentPins)

//
// Data is valid
//
dataValidOutput := true.B

when(numberOfSentPins === numberOfInputPorts.U) {
when(numberOfSentPins === (numberOfPorts - 1).U) {

//
// Reset the pins sent for sending output details
//
numberOfSentPins := 0.U

state := sSendOutputPortItems

}.otherwise {

//
// Send next index
//
numberOfSentPins := numberOfSentPins + 1.U

//
// Stay at the same state
//
state := sSendInputPortItems
}

}
is(sSendOutputPortItems) {

//
// Send output port items
//

//
// Adjust data
//
sendingData := outputPinsVec(numberOfSentPins)

//
// Data is valid
//
dataValidOutput := true.B

when(numberOfSentPins === numberOfOutputPorts.U) {

//
// Reset the pins sent for sending input details (later)
// Reset the pins sent for sending details
//
numberOfSentPins := 0.U

Expand All @@ -246,8 +169,9 @@ class InterpreterPortInformation(
//
// Stay at the same state
//
state := sSendOutputPortItems
state := sSendPortItems
}

}
is(sDone) {

Expand Down Expand Up @@ -281,16 +205,16 @@ object InterpreterPortInformation {
def apply(
debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH,
inputPortsConfiguration: Map[Int, Int] = DebuggerPorts.PORT_PINS_MAP_INPUT,
outputPortsConfiguration: Map[Int, Int] = DebuggerPorts.PORT_PINS_MAP_OUTPUT
portsConfiguration: Map[Int, Int] = DebuggerPorts.PORT_PINS_MAP
)(
en: Bool
): (Bool, Bool, UInt) = {

val interpreterPortInformation = Module(
new InterpreterPortInformation(
debug,
bramDataWidth
bramDataWidth,
portsConfiguration
)
)

Expand Down
24 changes: 4 additions & 20 deletions src/main/scala/hwdbg/configs/configs.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -26,23 +26,12 @@ object DebuggerPorts {

//
// The following constant shows the key value object of the mappings
// of pins to ports (used for inputs)
// of pins to ports (used for inputs/outputs)
// For example,
// port 0 (in) -> contains 12 pins
// port 1 (in) -> contains 9 pins
// port 2 (in) -> contains 11 pins
//
val PORT_PINS_MAP_INPUT: Map[Int, Int] = Map(0 -> 12, 1 -> 9, 2 -> 11)

//
// The following constant shows the key value object of the mappings
// of pins to ports (used for outputs)
// For example,
// port 0 (out) -> contains 12 pins
// port 1 (out) -> contains 9 pins
// port 2 (out) -> contains 11 pins
//
val PORT_PINS_MAP_OUTPUT: Map[Int, Int] = Map(0 -> 4, 1 -> 7, 2 -> 11, 3 -> 10)
val PORT_PINS_MAP: Map[Int, Int] = Map(0 -> 12, 1 -> 9, 2 -> 11)

}

Expand All @@ -58,14 +47,9 @@ object DebuggerConfigurations {
val ENABLE_DEBUG: Boolean = true

//
// Number of input pins
//
val NUMBER_OF_INPUT_PINS: Int = 32

//
// Number of output pins
// Number of input/output pins
//
val NUMBER_OF_OUTPUT_PINS: Int = 32
val NUMBER_OF_PINS: Int = 32

//
// Address width of the Block RAM (BRAM)
Expand Down
4 changes: 2 additions & 2 deletions src/main/scala/hwdbg/configs/test_configs.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ import chisel3.util._
*/
object TestingConfigurations {

val BRAM_INITIALIZATION_FILE_PATH: String = "./src/test/bram/send_version.hex.txt"
// val BRAM_INITIALIZATION_FILE_PATH: String = "./src/test/bram/port_information.hex.txt"
// val BRAM_INITIALIZATION_FILE_PATH: String = "./src/test/bram/send_version.hex.txt"
val BRAM_INITIALIZATION_FILE_PATH: String = "./src/test/bram/port_information.hex.txt"

}
40 changes: 13 additions & 27 deletions src/main/scala/hwdbg/main.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -27,28 +27,18 @@ import hwdbg.communication.interpreter._

class DebuggerMain(
debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
numberOfInputPins: Int = DebuggerConfigurations.NUMBER_OF_INPUT_PINS,
numberOfOutputPins: Int = DebuggerConfigurations.NUMBER_OF_OUTPUT_PINS,
numberOfPins: Int = DebuggerConfigurations.NUMBER_OF_PINS,
bramAddrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH,
inputPortsConfiguration: Map[Int, Int] = DebuggerPorts.PORT_PINS_MAP_INPUT,
outputPortsConfiguration: Map[Int, Int] = DebuggerPorts.PORT_PINS_MAP_OUTPUT
portsConfiguration: Map[Int, Int] = DebuggerPorts.PORT_PINS_MAP
) extends Module {

//
// Ensure sum of input port values equals numberOfInputPins (NUMBER_OF_INPUT_PINS)
// Ensure sum of input port values equals numberOfPins (NUMBER_OF_PINS)
//
require(
inputPortsConfiguration.values.sum == numberOfInputPins,
"err, the sum of the inputPortsConfiguration (PORT_PINS_MAP_INPUT) values must equal the numberOfInputPins (NUMBER_OF_INPUT_PINS)."
)

//
// Ensure sum of output port values equals numberOfOutputPins (NUMBER_OF_OUTPUT_PINS)
//
require(
outputPortsConfiguration.values.sum == numberOfOutputPins,
"err, the sum of the outputPortsConfiguration (PORT_PINS_MAP_OUTPUT) values must equal the numberOfOutputPins (NUMBER_OF_OUTPUT_PINS)."
portsConfiguration.values.sum == numberOfPins,
"err, the sum of the portsConfiguration (PORT_PINS_MAP) values must equal the numberOfPins (NUMBER_OF_PINS)."
)

val io = IO(new Bundle {
Expand All @@ -61,8 +51,8 @@ class DebuggerMain(
//
// Input/Output signals
//
val inputPin = Input(Vec(numberOfInputPins, UInt((1.W)))) // input pins
val outputPin = Output(Vec(numberOfOutputPins, UInt((1.W)))) // output pins
val inputPin = Input(Vec(numberOfPins, UInt((1.W)))) // input pins
val outputPin = Output(Vec(numberOfPins, UInt((1.W)))) // output pins

//
// Interrupt signals (lines)
Expand Down Expand Up @@ -168,7 +158,7 @@ class DebuggerMain(
// -----------------------------------------------------------------------
// Configure the output signals
//
for (i <- 0 until numberOfOutputPins) {
for (i <- 0 until numberOfPins) {
io.outputPin(i) := 0.U
}

Expand All @@ -183,12 +173,10 @@ object DebuggerMain {

def apply(
debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
numberOfInputPins: Int = DebuggerConfigurations.NUMBER_OF_INPUT_PINS,
numberOfOutputPins: Int = DebuggerConfigurations.NUMBER_OF_OUTPUT_PINS,
numberOfPins: Int = DebuggerConfigurations.NUMBER_OF_PINS,
bramAddrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH,
inputPortsConfiguration: Map[Int, Int] = DebuggerPorts.PORT_PINS_MAP_INPUT,
outputPortsConfiguration: Map[Int, Int] = DebuggerPorts.PORT_PINS_MAP_OUTPUT
portsConfiguration: Map[Int, Int] = DebuggerPorts.PORT_PINS_MAP
)(
en: Bool,
inputPin: Vec[UInt],
Expand All @@ -199,16 +187,14 @@ object DebuggerMain {
val debuggerMainModule = Module(
new DebuggerMain(
debug,
numberOfInputPins,
numberOfOutputPins,
numberOfPins,
bramAddrWidth,
bramDataWidth,
inputPortsConfiguration,
outputPortsConfiguration
portsConfiguration
)
)

val outputPin = Wire(Vec(numberOfOutputPins, UInt((1.W))))
val outputPin = Wire(Vec(numberOfPins, UInt((1.W))))
val psOutInterrupt = Wire(Bool())
val rdWrAddr = Wire(UInt(bramAddrWidth.W))
val wrEna = Wire(Bool())
Expand Down
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