create combinational logic for sending version

sim/hwdbg/DebuggerModuleTestingBRAM/Makefile

@@ -8,6 +8,7 @@ VERILOG_SOURCES += $(shell pwd)/../../../generated/SendReceiveSynchronizer.sv
 VERILOG_SOURCES += $(shell pwd)/../../../generated/DebuggerPacketReceiver.sv
 VERILOG_SOURCES += $(shell pwd)/../../../generated/DebuggerPacketSender.sv
 VERILOG_SOURCES += $(shell pwd)/../../../generated/DebuggerPacketInterpreter.sv
+VERILOG_SOURCES += $(shell pwd)/../../../generated/InterpreterSendVersion.sv
 TOPLEVEL = DebuggerModuleTestingBRAM
 MODULE = test_DebuggerModuleTestingBRAM
 

sim/hwdbg/DebuggerModuleTestingBRAM/test_DebuggerModuleTestingBRAM.py

@@ -378,6 +378,11 @@ async def DebuggerModuleTestingBRAM_test(dut):
     else:    
         print("Debuggee (PL) interrupted Debugger (PS)")
 
+    #
+    # Run one more clock cycle to apply the latest BRAM modifications
+    #
+    await RisingEdge(dut.clock)
+
     #
     # Print contents of BRAM
     #

src/main/scala/hwdbg/communication/interpreter/interpreter.scala → src/main/scala/hwdbg/communication/interpreter.scala

@@ -19,7 +19,6 @@ import chisel3._
 import chisel3.util.{switch, is}
 import circt.stage.ChiselStage
 
-import hwdbg.version._
 import hwdbg.configs._
 import hwdbg.types._
 
@@ -239,19 +238,36 @@ class DebuggerPacketInterpreter(
             //
 
             //
-            // Set the version
+            // Instantiate the versinon sender
             //
-            sendingData := Version.getEncodedVersion.U
+            val (
+              noNewDataSenderModule,
+              dataValidOutputModule,
+              sendingDataModule
+            ) =
+              InterpreterSendVersion(
+                debug,
+                bramDataWidth
+              )(
+                io.sendWaitForBuffer // send waiting for buffer as an activation signal to the module
+              )
 
             //
-            // Data is valid to send
+            // Set data validity
             //
-            dataValidOutput := true.B
+            dataValidOutput := dataValidOutputModule
 
             //
-            // Only one buffer is enough to send, so we're done
+            // Set data
             //
-            state := sDone
+            sendingData := sendingDataModule
+
+            //
+            // Once sending data is done, we'll go to the Done state
+            //
+            when(noNewDataSenderModule === true.B) {
+              state := sDone
+            }
 
           }.elsewhen(regRequestedActionOfThePacketOutput === HwdbgResponseEnums.hwdbgResponsePinInformation.id.U) {
 

src/main/scala/hwdbg/communication/interpreter/send_version.scala

@@ -0,0 +1,123 @@
+/**
+ * @file
+ *   send_version.scala
+ * @author
+ *   Sina Karvandi ([email protected])
+ * @brief
+ *   Send version (in interpreter)
+ * @details
+ * @version 0.1
+ * @date
+ *   2024-05-03
+ *
+ * @copyright
+ *   This project is released under the GNU Public License v3.
+ */
+package hwdbg.communication.interpreter
+
+import chisel3._
+import chisel3.util.{switch, is}
+import circt.stage.ChiselStage
+
+import hwdbg.version._
+import hwdbg.configs._
+
+class InterpreterSendVersion(
+    debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
+    bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+) extends Module {
+
+  val io = IO(new Bundle {
+
+    //
+    // Chip signals
+    //
+    val en = Input(Bool()) // chip enable signal
+
+    //
+    // Sending singals
+    //
+    val noNewDataSender = Output(Bool()) // should sender finish sending buffers or not?
+    val dataValidOutput = Output(Bool()) // should sender send next buffer or not?
+    val sendingData = Output(UInt(bramDataWidth.W)) // data to be sent to the debugger
+
+  })
+
+  //
+  // Output pins
+  //
+  val noNewDataSender = WireInit(false.B)
+  val dataValidOutput = WireInit(false.B)
+  val sendingData = WireInit(0.U(bramDataWidth.W))
+
+  //
+  // Apply the chip enable signal
+  //
+  when(io.en === true.B) {
+
+    //
+    // Set the version
+    //
+    sendingData := Version.getEncodedVersion.U
+
+    //
+    // Sending the version in one clock cycle
+    //
+    noNewDataSender := true.B
+    dataValidOutput := true.B
+
+  }
+
+  // ---------------------------------------------------------------------
+
+  //
+  // Connect output pins
+  //
+  io.noNewDataSender := noNewDataSender
+  io.dataValidOutput := dataValidOutput
+  io.sendingData := sendingData
+
+}
+
+object InterpreterSendVersion {
+
+  def apply(
+      debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
+      bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+  )(
+      en: Bool
+  ): (Bool, Bool, UInt) = {
+
+    val interpreterSendVersion = Module(
+      new InterpreterSendVersion(
+        debug,
+        bramDataWidth
+      )
+    )
+
+    val noNewDataSender = Wire(Bool())
+    val dataValidOutput = Wire(Bool())
+    val sendingData = Wire(UInt(bramDataWidth.W))
+
+    //
+    // Configure the input signals
+    //
+    interpreterSendVersion.io.en := en
+
+    //
+    // Configure the output signals
+    //
+    noNewDataSender := interpreterSendVersion.io.noNewDataSender
+    dataValidOutput := interpreterSendVersion.io.dataValidOutput
+    sendingData := interpreterSendVersion.io.sendingData
+
+    //
+    // Return the output result
+    //
+    (
+      noNewDataSender,
+      dataValidOutput,
+      sendingData
+    )
+  }
+}