fix receiver FSM logic

sim/hwdbg/communication/DebuggerPacketReceiver/test_DebuggerPacketReceiver.py

@@ -45,10 +45,10 @@ async def DebuggerPacketReceiver_test(dut):
     # Assert initial output is unknown
     #
     assert LogicArray(dut.io_rdWrAddr.value) == LogicArray("XXXXXXXXXXXXX")
-    assert LogicArray(dut.io_requestedActionOfThePacketOutput.value) == LogicArray("ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ")
+    assert LogicArray(dut.io_requestedActionOfThePacketOutput.value) == LogicArray("XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX")
     assert LogicArray(dut.io_requestedActionOfThePacketOutputValid.value) == LogicArray("X")
     assert LogicArray(dut.io_dataValidOutput.value) == LogicArray("X")
-    assert LogicArray(dut.io_receivingData.value) == LogicArray("ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ")
+    assert LogicArray(dut.io_receivingData.value) == LogicArray("XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX")
     assert LogicArray(dut.io_finishedReceivingBuffer.value) == LogicArray("X")
 
     clock = Clock(dut.clock, 10, units="ns")  # Create a 10ns period clock on port clock
@@ -64,6 +64,8 @@ async def DebuggerPacketReceiver_test(dut):
     # Initial values
     #
     dut.io_en.value = 0
+    dut.io_readNextData.value = 0
+    dut.io_noNewDataReceiver.value = 0
     dut.io_plInSignal.value = 0
 
     #
@@ -96,7 +98,7 @@ async def DebuggerPacketReceiver_test(dut):
         #
         # Wait until the data is received
         #
-        for _ in range(1000):
+        for _ in range(20):
             if (dut.io_dataValidOutput.value == 1):
                 break
             else:
@@ -106,13 +108,19 @@ async def DebuggerPacketReceiver_test(dut):
                     case 0x8: # indicator
                         dut.io_rdData.value = 0x48595045 # first 32 bits of the indicator
                     case 0x10: # type
-                        dut.io_rdData.value = 0x10101010
+                        dut.io_rdData.value = 0x4 # debugger to hardware packet (DEBUGGER_TO_DEBUGGEE_HARDWARE_LEVEL)
                     case 0x14: # requested action
                         dut.io_rdData.value = 0x14141414
                     case _:
                         assert "invalid address in the address line"
             await RisingEdge(dut.clock)
 
+
+        #
+        # No new data needed to be received
+        #
+        dut.io_noNewDataReceiver.value = 1
+
         #
         # Run extra waiting clocks
         #

src/main/scala/hwdbg/communication/receiver.scala

@@ -26,8 +26,8 @@ import hwdbg.constants._
 
 object DebuggerPacketReceiverEnums {
   object State extends ChiselEnum {
-    val sIdle, sReadChecksum, sReadIndicator, sReadTypeOfThePacket, sReadRequestedActionOfThePacket, sRequestedActionIsValid, sReadActionBuffer,
-        sDone = Value
+    val sIdle, sReadChecksum, sReadIndicator, sReadTypeOfThePacket, sReadRequestedActionOfThePacket, sRequestedActionIsValid, sWaitToReadActionBuffer,
+        sReadActionBuffer, sDone = Value
   }
 }
 
@@ -91,10 +91,10 @@ class DebuggerPacketReceiver(
   val rdWrAddr = WireInit(0.U(bramAddrWidth.W))
   val regRdWrAddr = RegInit(0.U(bramAddrWidth.W))
   val finishedReceivingBuffer = WireInit(false.B)
-  val requestedActionOfThePacketOutput = WireInit(0.U(new DebuggerRemotePacket().RequestedActionOfThePacket.getWidth.W))
-  val requestedActionOfThePacketOutputValid = WireInit(false.B)
-  val dataValidOutput = WireInit(false.B)
-  val receivingData = WireInit(0.U(bramDataWidth.W))
+  val regRequestedActionOfThePacketOutput = RegInit(0.U(new DebuggerRemotePacket().RequestedActionOfThePacket.getWidth.W))
+  val regRequestedActionOfThePacketOutputValid = RegInit(false.B)
+  val regDataValidOutput = RegInit(false.B)
+  val regReceivingData = RegInit(0.U(bramDataWidth.W))
 
   //
   // Rising-edge detector for start receiving signal
@@ -139,10 +139,10 @@ class DebuggerPacketReceiver(
         // Configure the output pins in case of sIdle
         //
         rdWrAddr := 0.U
-        requestedActionOfThePacketOutput := 0.U
-        requestedActionOfThePacketOutputValid := false.B
-        dataValidOutput := false.B
-        receivingData := 0.U
+        regRequestedActionOfThePacketOutput := 0.U
+        regRequestedActionOfThePacketOutputValid := false.B
+        regDataValidOutput := false.B
+        regReceivingData := 0.U
         finishedReceivingBuffer := false.B
 
       }
@@ -217,6 +217,9 @@ class DebuggerPacketReceiver(
         // Check whether the type of the packet is valid or not
         //
         val packetType: DebuggerRemotePacketType.Value = DebuggerRemotePacketType.DEBUGGER_TO_DEBUGGEE_HARDWARE_LEVEL
+        LogInfo(debug)(
+          f"Check packet type with DEBUGGER_TO_DEBUGGEE_HARDWARE_LEVEL (0x${packetType.id}%x)"
+        )
         when(io.rdData === packetType.id.U) {
 
           //
@@ -241,12 +244,20 @@ class DebuggerPacketReceiver(
         //
         // Read the RequestedActionOfThePacket
         //
-        requestedActionOfThePacketOutput := io.rdData
+        regRequestedActionOfThePacketOutput := io.rdData
 
         //
         // The RequestedActionOfThePacketOutput is valid from now
         //
-        requestedActionOfThePacketOutputValid := true.B
+        regRequestedActionOfThePacketOutputValid := true.B
+
+        //
+        // Goes to the next section
+        //
+        state := sWaitToReadActionBuffer
+
+      }
+      is(sWaitToReadActionBuffer) {
 
         //
         // Check if the caller needs to read the next part of
@@ -277,7 +288,7 @@ class DebuggerPacketReceiver(
           //
           // Stay at the same state
           //
-          state := sRequestedActionIsValid
+          state := sWaitToReadActionBuffer
         }
 
       }
@@ -286,17 +297,17 @@ class DebuggerPacketReceiver(
         //
         // Data outputs are now valid
         //
-        dataValidOutput := true.B
+        regDataValidOutput := true.B
 
         //
         // Adjust the read buffer data
         //
-        receivingData := io.rdData
+        regReceivingData := io.rdData
 
         //
         // Return to the previous state of action
         //
-        state := sRequestedActionIsValid
+        state := sWaitToReadActionBuffer
 
       }
       is(sDone) {
@@ -306,6 +317,14 @@ class DebuggerPacketReceiver(
         //
         regRdWrAddr := 0.U
 
+        //
+        // Requested action buffer and the receiving buffer is no longer valid
+        //
+        regRequestedActionOfThePacketOutput := 0.U
+        regRequestedActionOfThePacketOutputValid := false.B
+        regReceivingData := 0.U
+        regDataValidOutput := false.B
+
         //
         // The receiving is done at this stage, either
         // was successful of unsucessful, we'll release the
@@ -328,10 +347,10 @@ class DebuggerPacketReceiver(
   // Connect output pins
   //
   io.rdWrAddr := rdWrAddr
-  io.requestedActionOfThePacketOutput := requestedActionOfThePacketOutput
-  io.requestedActionOfThePacketOutputValid := requestedActionOfThePacketOutputValid
-  io.dataValidOutput := dataValidOutput
-  io.receivingData := receivingData
+  io.requestedActionOfThePacketOutput := regRequestedActionOfThePacketOutput
+  io.requestedActionOfThePacketOutputValid := regRequestedActionOfThePacketOutputValid
+  io.dataValidOutput := regDataValidOutput
+  io.receivingData := regReceivingData
   io.finishedReceivingBuffer := finishedReceivingBuffer
 
 }