send input output port count

src/main/scala/hwdbg/communication/interpreter.scala

@@ -296,9 +296,36 @@ class DebuggerPacketInterpreter(
             //
 
             //
-            // TODO: To be implemented
+            // Instantiate the port information module
             //
-            state := sDone
+            val (
+              noNewDataSenderModule,
+              dataValidOutputModule,
+              sendingDataModule
+            ) =
+              InterpreterPortInformation(
+                debug,
+                bramDataWidth
+              )(
+                io.sendWaitForBuffer // send waiting for buffer as an activation signal to the module
+              )
+
+            //
+            // Set data validity
+            //
+            dataValidOutput := dataValidOutputModule
+
+            //
+            // Set data
+            //
+            sendingData := sendingDataModule
+
+            //
+            // Once sending data is done, we'll go to the Done state
+            //
+            when(noNewDataSenderModule === true.B) {
+              state := sDone
+            }
 
           }.elsewhen(regRequestedActionOfThePacketOutput === HwdbgResponseEnums.hwdbgResponseScriptBufferConfigurationResult.id.U) {
 

src/main/scala/hwdbg/communication/interpreter/port_information.scala

@@ -21,12 +21,27 @@ import circt.stage.ChiselStage
 
 import hwdbg.version._
 import hwdbg.configs._
+import hwdbg.utils._
+
+object InterpreterPortInformationEnums {
+  object State extends ChiselEnum {
+    val sIdle, sSendCountOfInputPorts, sSendCountOfOutputPorts, sSendPortItems, sDone = Value
+  }
+}
 
 class InterpreterPortInformation(
     debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
-    bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+    bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH,
+    inputPortsConfiguration: Map[Int, Int] = DebuggerPorts.PORT_PINS_MAP_INPUT,
+    outputPortsConfiguration: Map[Int, Int] = DebuggerPorts.PORT_PINS_MAP_OUTPUT
 ) extends Module {
 
+  //
+  // Import state enum
+  //
+  import InterpreterPortInformationEnums.State
+  import InterpreterPortInformationEnums.State._
+
   val io = IO(new Bundle {
 
     //
@@ -43,6 +58,11 @@ class InterpreterPortInformation(
 
   })
 
+  //
+  // State registers
+  //
+  val state = RegInit(sIdle)
+
   //
   // Output pins
   //
@@ -55,16 +75,67 @@ class InterpreterPortInformation(
   //
   when(io.en === true.B) {
 
-    //
-    // Set the version
-    //
-    sendingData := Version.getEncodedVersion.U
+    switch(state) {
 
-    //
-    // Sending the version in one clock cycle
-    //
-    noNewDataSender := true.B
-    dataValidOutput := true.B
+      is(sIdle) {
+
+        //
+        // Going to the next state (sending count of input ports)
+        //
+        state := sSendCountOfInputPorts
+      }
+      is(sSendCountOfInputPorts) {
+
+        //
+        // Send count of input ports
+        //
+        val numberOfInputPorts = inputPortsConfiguration.size
+        LogInfo(debug)("Number of input ports (PORT_PINS_MAP_INPUT): " + numberOfInputPorts)
+
+        sendingData := numberOfInputPorts.U
+
+        //
+        // Data is valid
+        //
+        noNewDataSender := true.B
+        dataValidOutput := true.B
+
+        //
+        // Going to the next state (sending count of input ports)
+        //
+        state := sSendCountOfOutputPorts
+
+      }
+      is(sSendCountOfOutputPorts) {
+
+        //
+        // Send count of output ports
+        //
+        val numberOfOutputPorts = outputPortsConfiguration.size
+        LogInfo(debug)("Number of output ports (PORT_PINS_MAP_OUTPUT): " + numberOfOutputPorts)
+
+        sendingData := numberOfOutputPorts.U
+
+        //
+        // Data is valid
+        //
+        noNewDataSender := true.B
+        dataValidOutput := true.B
+
+        //
+        // Next, we gonna send each ports' information ()
+        //
+        state := sSendPortItems
+
+      }
+      is(sSendPortItems) {
+
+        //
+        //
+        //
+
+      }
+    }
 
   }
 
@@ -83,7 +154,9 @@ object InterpreterPortInformation {
 
   def apply(
       debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
-      bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+      bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH,
+      inputPortsConfiguration: Map[Int, Int] = DebuggerPorts.PORT_PINS_MAP_INPUT,
+      outputPortsConfiguration: Map[Int, Int] = DebuggerPorts.PORT_PINS_MAP_OUTPUT
   )(
       en: Bool
   ): (Bool, Bool, UInt) = {

src/main/scala/hwdbg/configs/configs.scala

@@ -55,7 +55,7 @@ object DebuggerConfigurations {
   //
   // whether to enable debug or not
   //
-  val ENABLE_DEBUG: Boolean = false
+  val ENABLE_DEBUG: Boolean = true
 
   //
   // Number of input pins

src/main/scala/hwdbg/libs/mem/init_reg_mem_from_file.scala

@@ -71,7 +71,10 @@ class InitRegMemFromFile(
     val dataOut = Output(UInt(width.W))
   })
 
-  val mem = RegInit(VecInit(InitRegMemFromFileTools.readmemh(debug, memoryFile, width)))
+  //
+  // Not needed to show the BRAM information
+  //
+  val mem = RegInit(VecInit(InitRegMemFromFileTools.readmemh(false, memoryFile, width)))
 
   val actualAddr = Wire(UInt(addrWidth.W))
   val actualData = Wire(UInt(width.W))

src/main/scala/hwdbg/types/communication.scala

@@ -67,54 +67,6 @@ class DebuggerRemotePacket() extends Bundle {
 
 // -----------------------------------------------------------------------
 
-//
-// Structure in C:
-//
-// typedef struct _DEBUGGER_REMOTE_PACKET
-// {
-//     BYTE                                    Checksum;
-//     UINT64                                  Indicator; /* Shows the type of the packet */
-//     DEBUGGER_REMOTE_PACKET_TYPE             TypeOfThePacket;
-//     DEBUGGER_REMOTE_PACKET_REQUESTED_ACTION RequestedActionOfThePacket;
-//
-// } DEBUGGER_REMOTE_PACKET, *PDEBUGGER_REMOTE_PACKET;
-//
-
-/**
- * @brief
- *   The packet used for communication with the remote debugger
- */
-class DebuggerRemotePacket() extends Bundle {
-
-  //
-  // Structure fields
-  //
-  val Checksum = UInt(8.W) // 1 byte
-  val Alignment0 = UInt((64 - 8).W) // 7 bytes
-  val Indicator = UInt(64.W) // 8 bytes
-  val TypeOfThePacket = UInt(32.W) // 4 bytes
-  val RequestedActionOfThePacket = UInt(32.W) // 4 bytes
-
-  //
-  // Offset of structure fields
-  //
-  object Offset {
-
-    val checksum = (0) / 8
-
-    val indicator = (Checksum.getWidth + Alignment0.getWidth) / 8
-
-    val typeOfThePacket = (Checksum.getWidth + Alignment0.getWidth + Indicator.getWidth) / 8
-
-    val requestedActionOfThePacket = (Checksum.getWidth + Alignment0.getWidth + Indicator.getWidth + TypeOfThePacket.getWidth) / 8
-
-    val startOfDataBuffer =
-      (Checksum.getWidth + Alignment0.getWidth + Indicator.getWidth + TypeOfThePacket.getWidth + RequestedActionOfThePacket.getWidth) / 8
-  }
-}
-
-// -----------------------------------------------------------------------
-
 //
 // Structure in C:
 //

src/main/scala/hwdbg/utils/utils.scala

@@ -25,7 +25,9 @@ import chisel3.util._
 object LogInfo {
 
   def apply(debug: Boolean)(message: String): Unit = {
-    println("[*] debug msg: " + message)
+    if (debug) {
+      println("[*] debug msg: " + message)
+    }
   }
 }