diff --git a/src/main/scala/hwdbg/interpreter/interpreter.scala b/src/main/scala/hwdbg/interpreter/interpreter.scala index 1c3b59b..9fe68f3 100644 --- a/src/main/scala/hwdbg/interpreter/interpreter.scala +++ b/src/main/scala/hwdbg/interpreter/interpreter.scala @@ -20,10 +20,12 @@ import circt.stage.ChiselStage import hwdbg.configs._ import hwdbg.types._ +import hwdbg.utils._ object DebuggerPacketInterpreterEnums { object State extends ChiselEnum { - val sIdle, sInit = Value + val sIdle, sInit, sReadChecksum, sReadIndicator, sReadTypeOfThePacket, + sReadRequestedActionOfThePacket, sDone = Value } } @@ -79,43 +81,143 @@ class DebuggerPacketInterpreter( val regRdWrAddr = RegInit(0.U(bramAddrWidth.W)) val regInterpretationDone = RegInit(false.B) val regFoundValidPacket = RegInit(false.B) - val regRequestedActionOfThePacket = RegInit(0.U(32.W)) - // ------------------------------- + // + // Structure (as register) of the received packet buffer + // + val regReceivedPacketBuffer = RegInit( + 0.U.asTypeOf(new DebuggerRemotePacket()) + ) - /* - val receivedPacketBuffer = Wire(new DebuggerRemotePacket()) - receivedPacketBuffer.key := io.key - receivedPacketBuffer.value := io.value - io.struct_key := ms.key - io.struct_value := ms.value - */ + // + // Apply the chip enable signal + // + when(io.en === true.B) { + + switch(state) { + + is(sIdle) { + + // + // Create logs from communication structure offsets + // + LogInfo(debug)( + f"The offset of Checksum is 0x${regReceivedPacketBuffer.Offset.checksum}%x" + ) + LogInfo(debug)( + f"The offset of Indicator is 0x${regReceivedPacketBuffer.Offset.indicator}%x" + ) + LogInfo(debug)( + f"The offset of TypeOfThePacket is 0x${regReceivedPacketBuffer.Offset.typeOfThePacket}%x" + ) + LogInfo(debug)( + f"The offset of RequestedActionOfThePacket is 0x${regReceivedPacketBuffer.Offset.requestedActionOfThePacket}%x" + ) + + // + // Check whether the interrupt from the PS is received or not + // + when(io.plInSignal === true.B) { + state := sInit + } + + // + // Configure the registers in case of sIdle + // + regRdWrAddr := 0.U + regInterpretationDone := false.B + regFoundValidPacket := false.B + regReceivedPacketBuffer.RequestedActionOfThePacket := 0.U - switch(state) { + } + is(sInit) { - is(sIdle) { + // + // Adjust address to read Checksum from BRAM + // + regRdWrAddr := regReceivedPacketBuffer.Offset.checksum.U - // - // Check whether the interrupt from the PS is received or not - // - when(io.en === true.B && io.plInSignal === true.B) { - state := sInit + // + // Goes to the next section + // + state := sReadChecksum } + is(sReadChecksum) { + + // + // Read the Checksum + // + regReceivedPacketBuffer.Checksum := io.rdData + + // + // Adjust address to read Indicator from BRAM + // + regRdWrAddr := regReceivedPacketBuffer.Offset.indicator.U + + // + // Goes to the next section + // + state := sReadIndicator + } + is(sReadIndicator) { + + // + // Read the Indicator + // + regReceivedPacketBuffer.Indicator := io.rdData + + // + // Adjust address to read TypeOfThePacket from BRAM + // + regRdWrAddr := regReceivedPacketBuffer.Offset.typeOfThePacket.U + + // + // Goes to the next section + // + state := sReadTypeOfThePacket + } + is(sReadTypeOfThePacket) { + + // + // Read the TypeOfThePacket + // + regReceivedPacketBuffer.TypeOfThePacket := io.rdData + + // + // Adjust address to read RequestedActionOfThePacket from BRAM + // + regRdWrAddr := regReceivedPacketBuffer.Offset.requestedActionOfThePacket.U + + // + // Goes to the next section + // + state := sReadRequestedActionOfThePacket + } + is(sReadRequestedActionOfThePacket) { - // - // Configure the registers in case of sIdle - // - regRdWrAddr := 0.U - regInterpretationDone := false.B - regFoundValidPacket := false.B - regRequestedActionOfThePacket := 0.U - - } - is(sInit) { + // + // Read the RequestedActionOfThePacket + // + regReceivedPacketBuffer.RequestedActionOfThePacket := io.rdData - // - // Test - // + // + // Reading all values + // + state := sDone + } + is(sDone) { + + // + // Adjust the output bits + // + regInterpretationDone := true.B + regFoundValidPacket := true.B + + // + // Go to the idle state + // + state := sIdle + } } } @@ -127,7 +229,7 @@ class DebuggerPacketInterpreter( io.rdWrAddr := regRdWrAddr io.interpretationDone := regInterpretationDone io.foundValidPacket := regFoundValidPacket - io.requestedActionOfThePacket := regRequestedActionOfThePacket + io.requestedActionOfThePacket := regReceivedPacketBuffer.RequestedActionOfThePacket } diff --git a/src/main/scala/hwdbg/main.scala b/src/main/scala/hwdbg/main.scala index fd12bdc..bdc599f 100644 --- a/src/main/scala/hwdbg/main.scala +++ b/src/main/scala/hwdbg/main.scala @@ -78,7 +78,10 @@ class DebuggerMain( // // Configure the output signals // - io.outputPin := 0.U + for (i <- 0 until numberOfOutputPins) { + io.outputPin(i) := 0.U + } + io.rdWrAddr := rdWrAddr io.wrEna := false.B io.wrData := 0.U diff --git a/src/main/scala/hwdbg/types/communication.scala b/src/main/scala/hwdbg/types/communication.scala index afd9e70..fc2a437 100644 --- a/src/main/scala/hwdbg/types/communication.scala +++ b/src/main/scala/hwdbg/types/communication.scala @@ -16,29 +16,49 @@ package hwdbg.types import chisel3._ -/* -Structure in C: - -typedef struct _DEBUGGER_REMOTE_PACKET -{ - BYTE Checksum; - UINT64 Indicator; /* Shows the type of the packet */ - DEBUGGER_REMOTE_PACKET_TYPE TypeOfThePacket; - DEBUGGER_REMOTE_PACKET_REQUESTED_ACTION RequestedActionOfThePacket; - -} DEBUGGER_REMOTE_PACKET, *PDEBUGGER_REMOTE_PACKET; - - */ +// +// Structure in C: +// +// typedef struct _DEBUGGER_REMOTE_PACKET +// { +// BYTE Checksum; +// UINT64 Indicator; /* Shows the type of the packet */ +// DEBUGGER_REMOTE_PACKET_TYPE TypeOfThePacket; +// DEBUGGER_REMOTE_PACKET_REQUESTED_ACTION RequestedActionOfThePacket; +// +// } DEBUGGER_REMOTE_PACKET, *PDEBUGGER_REMOTE_PACKET; +// /** @brief * The packet used for communication with the remote debugger */ class DebuggerRemotePacket() extends Bundle { + + // + // Structure fields + // val Checksum = UInt(8.W) // 1 bytes val Alignment0 = UInt((64 - 8).W) // 7 bytes val Indicator = UInt(64.W) // 8 bytes val TypeOfThePacket = UInt(32.W) // 4 bytes val RequestedActionOfThePacket = UInt(32.W) // 4 bytes + + // + // Offset of structure fields + // + object Offset { + + val checksum = (0) / 8 + + val indicator = + (Checksum.getWidth + Alignment0.getWidth) / 8 + + val typeOfThePacket = + (Checksum.getWidth + Alignment0.getWidth + Indicator.getWidth) / 8 + + val requestedActionOfThePacket = + (Checksum.getWidth + Alignment0.getWidth + Indicator.getWidth + TypeOfThePacket.getWidth) / 8 + } } // ----------------------------------------------------------------------- diff --git a/src/main/scala/hwdbg/utils/utils.scala b/src/main/scala/hwdbg/utils/utils.scala new file mode 100644 index 0000000..5d3a08b --- /dev/null +++ b/src/main/scala/hwdbg/utils/utils.scala @@ -0,0 +1,28 @@ +/** @file + * utils.scala + * @author + * Sina Karvandi (sina@hyperdbg.org) + * @brief + * Different utilities and functionalities + * @details + * @version 0.1 + * @date + * 2024-04-12 + * + * @copyright + * This project is released under the GNU Public License v3. + */ +package hwdbg.utils + +import chisel3._ +import chisel3.util._ + +/** @brief + * Create logs and debug messages + */ +object LogInfo { + + def apply(debug: Boolean)(message: String): Unit = { + println("[*] debug msg: " + message) + } +}