diff --git a/.scalafmt.conf b/.scalafmt.conf
new file mode 100644
index 0000000..3381358
--- /dev/null
+++ b/.scalafmt.conf
@@ -0,0 +1,2 @@
+version = "3.5.9"
+runner.dialect = scala213
\ No newline at end of file
diff --git a/.vscode/settings.json b/.vscode/settings.json
new file mode 100644
index 0000000..5abb201
--- /dev/null
+++ b/.vscode/settings.json
@@ -0,0 +1,8 @@
+{
+    "editor.formatOnSave": true,
+    "editor.formatOnSaveMode": "file",
+    "metals.scalafmtConfigPath": ".scalafmt.conf",
+    "files.watcherExclude": {
+        "**/target": true
+    }
+}
\ No newline at end of file
diff --git a/scalafmt.conf:Zone.Identifier b/scalafmt.conf:Zone.Identifier
new file mode 100644
index 0000000..24a199e
--- /dev/null
+++ b/scalafmt.conf:Zone.Identifier
@@ -0,0 +1,3 @@
+[ZoneTransfer]
+ZoneId=3
+HostUrl=https://raw.githubusercontent.com/cslab-chosun/online-fuzzy-chisel/main/.scalafmt.conf
diff --git a/src/main/scala/hwdbg/configs/configs.scala b/src/main/scala/hwdbg/configs/configs.scala
index 57c70c8..9c37f59 100644
--- a/src/main/scala/hwdbg/configs/configs.scala
+++ b/src/main/scala/hwdbg/configs/configs.scala
@@ -9,14 +9,40 @@ import chisel3.util._
   */
 object DebuggerConfigurations {
 
-  val ENABLE_DEBUG: Boolean = false // whether to enable debug or not
+  //
+  // whether to enable debug or not
+  //
+  val ENABLE_DEBUG: Boolean = false
 
-  val NUMBER_OF_INPUT_PINS: Int = 16 // Number of input pins
+  //
+  // Number of input pins
+  //
+  val NUMBER_OF_INPUT_PINS: Int = 16
 
-  val NUMBER_OF_OUTPUT_PINS: Int = 16 // Number of output pins
+  //
+  // Number of output pins
+  //
+  val NUMBER_OF_OUTPUT_PINS: Int = 16
 
-  val BLOCK_RAM_ADDR_WIDTH: Int = 13 // Address width of the Block RAM (BRAM)
+  //
+  // Address width of the Block RAM (BRAM)
+  //
+  val BLOCK_RAM_ADDR_WIDTH: Int = 13
 
-  val BLOCK_RAM_DATA_WIDTH: Int = 32 // Data width of the Block RAM (BRAM)
+  //
+  // Data width of the Block RAM (BRAM)
+  //
+  val BLOCK_RAM_DATA_WIDTH: Int = 32
 
+}
+
+/** @brief
+  *   The constants for min-max tree
+  */
+object GeneralConfigurations {
+
+  //
+  // Default number of bytes used in initialized SRAM memory
+  //
+  val DEFAULT_CONFIGURATION_INITIALIZED_MEMORY_SIZE: Int = 8192 // 8 KB
 }
\ No newline at end of file
diff --git a/src/main/scala/hwdbg/libs/mem/init_mem.scala b/src/main/scala/hwdbg/libs/mem/init_mem.scala
new file mode 100644
index 0000000..669cf7f
--- /dev/null
+++ b/src/main/scala/hwdbg/libs/mem/init_mem.scala
@@ -0,0 +1,38 @@
+package hwdbg.libs.mem
+
+import chisel3._
+import chisel3.util.experimental.loadMemoryFromFileInline
+
+class InitMemInline(
+  debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
+  memoryFile: String = "",
+  addrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
+  width: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH,
+  size: Int = GeneralConfigurations.DEFAULT_CONFIGURATION_INITIALIZED_MEMORY_SIZE
+  ) extends Module {
+
+  val io = IO(new Bundle {
+    val enable = Input(Bool())
+    val write = Input(Bool())
+    val addr = Input(UInt(10.W))
+    val dataIn = Input(UInt(width.W))
+    val dataOut = Output(UInt(width.W))
+  })
+
+  val mem =           SyncReadMem(size / width, UInt(width.W))  
+
+  //
+  // Initialize memory
+  //
+  if (memoryFile.trim().nonEmpty) {
+    loadMemoryFromFileInline(mem, memoryFile)
+  }
+
+  io.dataOut := DontCare
+
+  when(io.enable) {
+    val rdwrPort = mem(io.addr)
+    when (io.write) { rdwrPort := io.dataIn }
+      .otherwise    { io.dataOut := rdwrPort }
+  }
+}
\ No newline at end of file
diff --git a/src/main/scala/top.scala b/src/main/scala/top.scala
index b7ed1b3..c6a7857 100644
--- a/src/main/scala/top.scala
+++ b/src/main/scala/top.scala
@@ -35,28 +35,31 @@ class DebuggerModule(
     //
     // BRAM (Block RAM) ports
     //
-    val rdAddr = Input(UInt(bramAddrWidth.W))
-    val rdData = Output(UInt(bramDataWidth.W))
-    val wrAddr = Input(UInt(bramAddrWidth.W))
-    val wrEna  = Input(Bool())
-    val wrData = Input(UInt(bramDataWidth.W))
+    val rdAddr = Input(UInt(bramAddrWidth.W)) // read address
+    val rdData = Output(UInt(bramDataWidth.W)) // read data
+    val wrAddr = Input(UInt(bramAddrWidth.W)) // write address
+    val wrEna  = Input(Bool()) // enable writing
+    val wrData = Input(UInt(bramDataWidth.W)) // write data
 
   })
 
-  // Blink LED every second using Chisel built-in util.Counter
-  val led = RegInit(startOn.B)
-  val (_, counterWrap) = Counter(true.B, freq / 2)
-  when(counterWrap) {
-    led := ~led
-  }
-  io.led0 := led
+
 }
 
 object Main extends App {
-  // These lines generate the Verilog output
+
+  //
+  // Generate hwdbg verilog files
+  //
   println(
     ChiselStage.emitSystemVerilog(
-      new Blinky(1000),
+      new DebuggerModule(
+        DebuggerConfigurations.ENABLE_DEBUG, 
+        DebuggerConfigurations.NUMBER_OF_INPUT_PINS,
+        DebuggerConfigurations.NUMBER_OF_OUTPUT_PINS,
+        DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
+        DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+      ),
       firtoolOpts = Array(
       "-disable-all-randomization", 
       "-strip-debug-info",