add structures related to port information

sim/hwdbg/DebuggerModuleTestingBRAM/Makefile

@@ -10,6 +10,7 @@ VERILOG_SOURCES += $(shell pwd)/../../../generated/DebuggerPacketSender.sv
 VERILOG_SOURCES += $(shell pwd)/../../../generated/DebuggerPacketInterpreter.sv
 VERILOG_SOURCES += $(shell pwd)/../../../generated/InterpreterSendVersion.sv
 VERILOG_SOURCES += $(shell pwd)/../../../generated/InterpreterSendError.sv
+VERILOG_SOURCES += $(shell pwd)/../../../generated/InterpreterPortInformation.sv
 TOPLEVEL = DebuggerModuleTestingBRAM
 MODULE = test_DebuggerModuleTestingBRAM
 

src/main/scala/hwdbg/communication/interpreter/port_information.scala

@@ -0,0 +1,123 @@
+/**
+ * @file
+ *   port_information.scala
+ * @author
+ *   Sina Karvandi ([email protected])
+ * @brief
+ *   Send port information (in interpreter)
+ * @details
+ * @version 0.1
+ * @date
+ *   2024-05-04
+ *
+ * @copyright
+ *   This project is released under the GNU Public License v3.
+ */
+package hwdbg.communication.interpreter
+
+import chisel3._
+import chisel3.util.{switch, is}
+import circt.stage.ChiselStage
+
+import hwdbg.version._
+import hwdbg.configs._
+
+class InterpreterPortInformation(
+    debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
+    bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+) extends Module {
+
+  val io = IO(new Bundle {
+
+    //
+    // Chip signals
+    //
+    val en = Input(Bool()) // chip enable signal
+
+    //
+    // Sending singals
+    //
+    val noNewDataSender = Output(Bool()) // should sender finish sending buffers or not?
+    val dataValidOutput = Output(Bool()) // should sender send next buffer or not?
+    val sendingData = Output(UInt(bramDataWidth.W)) // data to be sent to the debugger
+
+  })
+
+  //
+  // Output pins
+  //
+  val noNewDataSender = WireInit(false.B)
+  val dataValidOutput = WireInit(false.B)
+  val sendingData = WireInit(0.U(bramDataWidth.W))
+
+  //
+  // Apply the chip enable signal
+  //
+  when(io.en === true.B) {
+
+    //
+    // Set the version
+    //
+    sendingData := Version.getEncodedVersion.U
+
+    //
+    // Sending the version in one clock cycle
+    //
+    noNewDataSender := true.B
+    dataValidOutput := true.B
+
+  }
+
+  // ---------------------------------------------------------------------
+
+  //
+  // Connect output pins
+  //
+  io.noNewDataSender := noNewDataSender
+  io.dataValidOutput := dataValidOutput
+  io.sendingData := sendingData
+
+}
+
+object InterpreterPortInformation {
+
+  def apply(
+      debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
+      bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+  )(
+      en: Bool
+  ): (Bool, Bool, UInt) = {
+
+    val interpreterPortInformation = Module(
+      new InterpreterPortInformation(
+        debug,
+        bramDataWidth
+      )
+    )
+
+    val noNewDataSender = Wire(Bool())
+    val dataValidOutput = Wire(Bool())
+    val sendingData = Wire(UInt(bramDataWidth.W))
+
+    //
+    // Configure the input signals
+    //
+    interpreterPortInformation.io.en := en
+
+    //
+    // Configure the output signals
+    //
+    noNewDataSender := interpreterPortInformation.io.noNewDataSender
+    dataValidOutput := interpreterPortInformation.io.dataValidOutput
+    sendingData := interpreterPortInformation.io.sendingData
+
+    //
+    // Return the output result
+    //
+    (
+      noNewDataSender,
+      dataValidOutput,
+      sendingData
+    )
+  }
+}

src/main/scala/hwdbg/types/communication.scala

@@ -17,6 +17,8 @@ package hwdbg.types
 
 import chisel3._
 
+// -----------------------------------------------------------------------
+
 //
 // Structure in C:
 //
@@ -65,6 +67,129 @@ class DebuggerRemotePacket() extends Bundle {
 
 // -----------------------------------------------------------------------
 
+//
+// Structure in C:
+//
+// typedef struct _DEBUGGER_REMOTE_PACKET
+// {
+//     BYTE                                    Checksum;
+//     UINT64                                  Indicator; /* Shows the type of the packet */
+//     DEBUGGER_REMOTE_PACKET_TYPE             TypeOfThePacket;
+//     DEBUGGER_REMOTE_PACKET_REQUESTED_ACTION RequestedActionOfThePacket;
+//
+// } DEBUGGER_REMOTE_PACKET, *PDEBUGGER_REMOTE_PACKET;
+//
+
+/**
+ * @brief
+ *   The packet used for communication with the remote debugger
+ */
+class DebuggerRemotePacket() extends Bundle {
+
+  //
+  // Structure fields
+  //
+  val Checksum = UInt(8.W) // 1 byte
+  val Alignment0 = UInt((64 - 8).W) // 7 bytes
+  val Indicator = UInt(64.W) // 8 bytes
+  val TypeOfThePacket = UInt(32.W) // 4 bytes
+  val RequestedActionOfThePacket = UInt(32.W) // 4 bytes
+
+  //
+  // Offset of structure fields
+  //
+  object Offset {
+
+    val checksum = (0) / 8
+
+    val indicator = (Checksum.getWidth + Alignment0.getWidth) / 8
+
+    val typeOfThePacket = (Checksum.getWidth + Alignment0.getWidth + Indicator.getWidth) / 8
+
+    val requestedActionOfThePacket = (Checksum.getWidth + Alignment0.getWidth + Indicator.getWidth + TypeOfThePacket.getWidth) / 8
+
+    val startOfDataBuffer =
+      (Checksum.getWidth + Alignment0.getWidth + Indicator.getWidth + TypeOfThePacket.getWidth + RequestedActionOfThePacket.getWidth) / 8
+  }
+}
+
+// -----------------------------------------------------------------------
+
+//
+// Structure in C:
+//
+// typedef struct _HWDBG_PORT_INFORMATION
+// {
+//     UINT32 CountOfPorts;
+//
+//     /*
+//
+//     Here the pin information details will be available
+//
+//         UINT16     | UINT16
+//         Port Index | Port Size
+//
+//     */
+//
+// } HWDBG_PORT_INFORMATION, *PHWDBG_PORT_INFORMATION;
+
+/**
+ * @brief
+ *   The structure of port information in hwdbg
+ */
+class HwdbgPortInformation() extends Bundle {
+
+  //
+  // Structure fields
+  //
+  val CountOfPorts = UInt(32.W) // 4 bytes
+
+  //
+  // Offset of structure fields
+  //
+  object Offset {
+
+    val countOfPorts = (0) / 8
+  }
+}
+
+// -----------------------------------------------------------------------
+
+//
+// Structure in C:
+//
+// typedef struct _HWDBG_PORT_INFORMATION_ITEMS
+// {
+//     UINT16 PortIndex;
+//     UINT16 PortSize;
+//
+// } HWDBG_PORT_INFORMATION_ITEMS, *PHWDBG_PORT_INFORMATION_ITEMS;
+
+/**
+ * @brief
+ *   The structure of port information (each item) in hwdbg
+ */
+class HwdbgPortInformationItems() extends Bundle {
+
+  //
+  // Structure fields
+  //
+  val PortIndex = UInt(16.W) // 2 bytes
+  val PortSize = UInt(16.W) // 2 bytes
+
+  //
+  // Offset of structure fields
+  //
+  object Offset {
+
+    val portIndex = (0) / 8
+
+    val portSize = (PortIndex.getWidth) / 8
+  }
+}
+
+// -----------------------------------------------------------------------
+
 /**
  * @brief
  *   Different action of hwdbg (SHARED WITH HYPERDBG) (HWDBG_ACTION_ENUMS)