From f9800526d6fe5098e72b78a0c2ea956d253c0eea Mon Sep 17 00:00:00 2001
From: Sina Karvandi <sina@hyperdbg.org>
Date: Wed, 3 Apr 2024 15:32:13 +0900
Subject: [PATCH] add debugger input and output pins

---
 .gitignore                                 | 14 ++++----
 src/main/scala/hwdbg/configs/configs.scala | 22 ++++++++++++
 src/main/scala/top.scala                   | 39 ++++++++++++++++++++--
 3 files changed, 66 insertions(+), 9 deletions(-)
 create mode 100644 src/main/scala/hwdbg/configs/configs.scala

diff --git a/.gitignore b/.gitignore
index 3d192aa..2c2be70 100644
--- a/.gitignore
+++ b/.gitignore
@@ -340,12 +340,12 @@ project/plugins/project/
 hs_err_pid*
 
 # Visual Studio Code
-#.vscode/*
-#!.vscode/settings.json
-#!.vscode/tasks.json
-#!.vscode/launch.json
-#!.vscode/extensions.json
-#!.vscode/*.code-snippets
+.vscode/*
+!.vscode/settings.json
+!.vscode/tasks.json
+!.vscode/launch.json
+!.vscode/extensions.json
+!.vscode/*.code-snippets
 
 # Local History for Visual Studio Code
 .history/
@@ -360,4 +360,4 @@ hs_err_pid*
 .bloop/
 
 # Temporary disable the generated verilog files
-#generated/
\ No newline at end of file
+generated/
\ No newline at end of file
diff --git a/src/main/scala/hwdbg/configs/configs.scala b/src/main/scala/hwdbg/configs/configs.scala
new file mode 100644
index 0000000..57c70c8
--- /dev/null
+++ b/src/main/scala/hwdbg/configs/configs.scala
@@ -0,0 +1,22 @@
+package hwdbg.configs
+
+import chisel3._
+import chisel3.util._
+
+
+/** @brief
+  *   The constants for min-max tree
+  */
+object DebuggerConfigurations {
+
+  val ENABLE_DEBUG: Boolean = false // whether to enable debug or not
+
+  val NUMBER_OF_INPUT_PINS: Int = 16 // Number of input pins
+
+  val NUMBER_OF_OUTPUT_PINS: Int = 16 // Number of output pins
+
+  val BLOCK_RAM_ADDR_WIDTH: Int = 13 // Address width of the Block RAM (BRAM)
+
+  val BLOCK_RAM_DATA_WIDTH: Int = 32 // Data width of the Block RAM (BRAM)
+
+}
\ No newline at end of file
diff --git a/src/main/scala/top.scala b/src/main/scala/top.scala
index 68391f7..b7ed1b3 100644
--- a/src/main/scala/top.scala
+++ b/src/main/scala/top.scala
@@ -4,10 +4,45 @@ import chisel3._
 import chisel3.util.Counter
 import circt.stage.ChiselStage
 
-class Blinky(freq: Int, startOn: Boolean = false) extends Module {
+import hwdbg.configs._
+
+class DebuggerModule(
+    debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
+    numberOfInputPins: Int = DebuggerConfigurations.NUMBER_OF_INPUT_PINS,
+    numberOfOutputPins: Int = DebuggerConfigurations.NUMBER_OF_OUTPUT_PINS,
+    bramAddrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
+    bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+) extends Module {
   val io = IO(new Bundle {
-    val led0 = Output(Bool())
+
+    //
+    // Chip signals
+    //
+    val en = Input(Bool()) // chip enable signal
+
+    //
+    // Input/Output signals
+    //
+    val inputPin = Input(Vec(numberOfInputPins, UInt((1.W)))) // input pins
+    val outputPin = Output(Vec(numberOfOutputPins, UInt((1.W)))) // output pins
+
+    //
+    // Interrupt signals (lines)
+    //   
+    val plInSignal = Input(Bool()) // PS to PL signal
+    val psOutInterrupt = Output(Bool()) // PL to PS interrupt
+
+    //
+    // BRAM (Block RAM) ports
+    //
+    val rdAddr = Input(UInt(bramAddrWidth.W))
+    val rdData = Output(UInt(bramDataWidth.W))
+    val wrAddr = Input(UInt(bramAddrWidth.W))
+    val wrEna  = Input(Bool())
+    val wrData = Input(UInt(bramDataWidth.W))
+
   })
+
   // Blink LED every second using Chisel built-in util.Counter
   val led = RegInit(startOn.B)
   val (_, counterWrap) = Counter(true.B, freq / 2)