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Release_Notes.html
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<!DOCTYPE html>
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<title>Release Notes for STM32H7xx HAL Drivers</title>
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<center>
<h1 id="release-notes-for-stm32h7xx-hal-drivers"><strong>Release Notes for STM32H7xx HAL Drivers</strong></h1>
<p>Copyright © 2017 STMicroelectronics<br />
</p>
<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a>
</center>
</div>
</div>
<h1 id="purpose">Purpose</h1>
<p>The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.</p>
<p>The portable APIs layer provides a generic, multi instanced and simple set of APIs to interact with the upper layer (application, libraries and stacks). It is composed of native and extended APIs set. It is directly built around a generic architecture and allows the build-upon layers, like the middleware layer, to implement its functions without knowing in-depth the used STM32 device. This improves the library code reusability and guarantees an easy portability on other devices and STM32 families.</p>
<p>The Low Layer (LL) drivers are part of the STM32Cube firmware HAL that provides a basic set of optimized and one shot services. The Low layer drivers, contrary to the HAL ones are not fully portable across the STM32 families; the availability of some functions depends on the physical availability of the relative features on the product. The Low Layer (LL) drivers are designed to offer the following features:</p>
<ul>
<li>New set of inline functions for direct and atomic register access</li>
<li>One-shot operations that can be used by the HAL drivers or from application level</li>
<li>Full independence from HAL and standalone usage (without HAL drivers)</li>
<li>Full features coverage of all the supported peripherals</li>
</ul>
</div>
<div class="col-sm-12 col-lg-8">
<h1 id="update-history"><strong>Update History</strong></h1>
<div class="collapse">
<input type="checkbox" id="collapse-section15" checked aria-hidden="true"> <label for="collapse-section15" aria-hidden="true"><strong>V1.11.0 / 11-February-2022</strong></label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements.</li>
<li><strong>The following changes done on the HAL drivers require an update of the application code based on older HAL versions</strong>
<ul>
<li>Rework of HAL Ethernet driver to resolve problems and improve performance.(compatibility break)</li>
<li>A new HAL Ethernet driver has been redesigned with new APIs, to bypass limitations with previous HAL Ethernet driver version.</li>
<li>The new HAL Ethernet driver is the recommended version. It is located as usual in Drivers/STM32H7xx_HAL_Driver/Src and Drivers/STM32H7xx_HAL_Driver/Inc folders.
<ul>
<li>It can be enabled through switch HAL_ETH_MODULE_ENABLED in stm32h7xx_hal_conf.h</li>
</ul></li>
<li>The legacy HAL Ethernet driver is also present in the release in Drivers/STM32H7xx_HAL_Driver/Src/Legacy and Drivers/STM32F4xx_HAL_Driver/Inc/Legacy folders for software compatibility reasons.
<ul>
<li>Its usage is not recommended as deprecated. It can however be enabled through switch HAL_ETH_LEGACY_MODULE_ENABLED in stm32h7xx_hal_conf.h</li>
</ul></li>
</ul></li>
<li><strong>HAL LTDC</strong>
<ul>
<li>Update HAL_LTDC_DeInit() to fix MCU Hang up during LCD turn OFF.</li>
</ul></li>
<li><strong>HAL QSPI</strong>
<ul>
<li>Update HAL_QSPI_Abort() and HAL_QSPI_Abort_IT() APIs to check on QSPI BUSY flag status before executing the abort procedure.</li>
</ul></li>
<li><strong>LL TIM</strong>
<ul>
<li>__LL_TIM_CALC_PSC() macro update to round up the evaluate value when the fractional part of the division is greater than 0.5.</li>
</ul></li>
<li><strong>HAL NOR</strong>
<ul>
<li>FMC_WRITE_OPERATION_DISABLE for NOR cause Hardfault for Read operations</li>
</ul></li>
<li><strong>HAL OSPI</strong>
<ul>
<li>Remove unsupported Clocked Chip Select High Time feature:
<ul>
<li>ClkChipSelectHighTime parameter removed from the OSPI_InitTypeDef structure</li>
<li>Update HAL_OSPI_Init() API to no longer configure the ClkChipSelectHighTime parameter in the OCTOSPI_DCR1 register</li>
</ul></li>
<li>Fix an MPU issue with OTFDEC examples and STM32H735G-DK BSP example.</li>
<li>Update HAL_OSPI_Init() to fix DelayBlockBypass parameter configuration issue.</li>
</ul></li>
<li><strong>HAL SPI</strong>
<ul>
<li>Update SPI_IRQ_Handler() to overrun error occurrence in full duplex communication.
<ul>
<li>Add clear for transmission flag.</li>
</ul></li>
<li>Update HAL_SPI_Receive() API to avoid hardfault exception in Master RX, Polling mode 8 bits mode when 2 byte are available at the same time.</li>
</ul></li>
<li><strong>HAL SMBUS</strong>
<ul>
<li>stm32h7xx_hal_smbus_ex.c/.h file added to support new <strong>HAL SMBUS extended feature</strong>.
<ul>
<li>Add Support for Fast Mode Plus to be SMBUS rev 3 compliant.
<ul>
<li>Add HAL_SMBUSEx_EnableFastModePlus() and HAL_SMBUSEx_DisableFastModePlus() APIs to manage Fm+.</li>
</ul></li>
<li>Add Support of wake up capability.
<ul>
<li>Add HAL_SMBUSEx_EnableWakeUp() and HAL_SMBUSEx_DisableWakeUp() APIs.</li>
</ul></li>
</ul></li>
</ul></li>
<li><strong>HAL ETH</strong>
<ul>
<li>Entire receive process reworked.</li>
<li>Resolve the problem of received data corruption.</li>
<li>Implement transmission in interrupt mode.</li>
<li>Handle one interrupt for multiple transmitted packets.</li>
<li>Implement APIs to handle PTP feature.</li>
<li>Implement APIs to handle Timestamp feature.</li>
<li>Add support of receive buffer unavailable.</li>
<li>Update HAL_ETH_IRQHandler() to handle receive buffer unavailable.</li>
</ul></li>
<li><strong>HAL/LL USB</strong>
<ul>
<li>Update to report correct received amount of data with USB DMA enabled</li>
<li>Update USB IRQ handler to enable EP OUT disable</li>
<li>Add support of USB IN/OUT Iso incomplete</li>
<li>Fix USB BCD data contact timeout</li>
</ul></li>
</ul>
<h2 id="known-limitations">Known Limitations</h2>
<ul>
<li>None</li>
</ul>
<h2 id="backward-compatibility">Backward compatibility</h2>
<ul>
<li>Compatibility break with HAL ETH driver V1.10.0 available within STM32CubeFW_H7 V1.9.0</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section14" aria-hidden="true"> <label for="collapse-section14" aria-hidden="true"><strong>V1.10.1 / 06-December-2021</strong></label>
<div>
<h2 id="main-changes-1">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements.</li>
<li>All source files: update disclaimer to add reference to the new license agreement.</li>
<li><strong>HAL RCC</strong>
<ul>
<li>Fix issue where HSI is not taken into account in HAL_RCC_OscConfig.</li>
</ul></li>
<li><strong>HAL FLASH</strong>
<ul>
<li>Update to fix error checking issue when optimization is set to high.</li>
</ul></li>
<li><strong>HAL GPIO</strong>
<ul>
<li>Reorder EXTI configuration sequence in order to avoid unexpected level detection.</li>
</ul></li>
<li><strong>HAL EXTI</strong>
<ul>
<li>Update HAL_EXTI_GetConfigLine() API to set default configuration value of Trigger and GPIOSel before checking each corresponding registers.</li>
</ul></li>
<li><strong>HAL/LL ADC</strong>
<ul>
<li>Fix issue where an error state is returned by the IRQ handler in case of injection conversion in IT mode with trigger timer.</li>
<li>Add missing injected external trigger to IS_ADC_EXTTRIGINJEC() macro.</li>
<li>Add two new APIs to simplify internal channel configuration (LL_ADC_SetCommonPathInternalChAdd and LL_ADC_SetCommonPathInternalChRem).</li>
<li>assert_param() now checks for continuous and discontinuous mode exclusivity.</li>
<li>Update LL ADC driver to correctly configure the ADC3 resolution on some devices.</li>
</ul></li>
<li><strong>HAL TIM</strong>
<ul>
<li>Manage the Bi-directional break input feature for the concerned part numbers.</li>
<li>Update input capture measurement in DMA mode to avoid zero return values at high frequencies.</li>
<li>Update HAL_TIMEx_ConfigBreakInput to use CMSIS TIM1_OR2_BKDF1BK0E_Pos definition instead of its hard coded value.</li>
<li>Fix wrong compile switch used in TIM_LL_EC_DMABURST_BASEADDR constant definitions.</li>
</ul></li>
<li><strong>HAL UART</strong>
<ul>
<li>Fix erroneous UART’s handle state in case of error returned after DMA reception start within UART_Start_Receive_DMA().</li>
<li>Correct UART ReceptionType management in case if ReceptionToIdle API being called from RxEvent callback.</li>
<li>Handling of UART concurrent register access in case of race condition between TX and RX transfers (HAL UART and LL LPUART).</li>
<li>Improve header description of UART_WaitOnFlagUntilTimeout() function.</li>
<li>Add a check on the UART parity before enabling the parity error interruption.</li>
<li>Add const qualifier for read only pointers in API prototypes.</li>
<li>Fix wrong cast when computing the USARTDIV value in UART_SetConfig().</li>
</ul></li>
<li><strong>HAL/LL USART</strong>
<ul>
<li>Improve header description of USART_WaitOnFlagUntilTimeout() function.</li>
<li>Add a check on the USART parity before enabling the parity error interrupt.</li>
<li>Add const qualifier for read only pointers for API prototypes.</li>
<li>Handling of UART concurrent register access in case of race condition between TX and RX transfers (HAL UART and LL LPUART).</li>
<li>Fix compilation warnings generated with ARMV6 compiler.</li>
</ul></li>
<li><strong>LL LPUART</strong>
<ul>
<li>Remove TXFECF reference from LL LPUART driver.</li>
</ul></li>
<li><strong>HAL SMBUS</strong>
<ul>
<li>Add Fm+ support to SMBus to be rev3 compliant.</li>
<li>Add the support of wake up capability.</li>
<li>Add new APIs:
<ul>
<li>HAL_SMBUSEx_EnableWakeUp()</li>
<li>HAL_SMBUSEx_DisableWakeUp()</li>
</ul></li>
<li>Update to fix issue of mismatched data received by master in case of data size to be transmitted by the slave is greater than the data size to be received by the master.</li>
<li>Add flush on TX register.</li>
</ul></li>
<li><strong>HAL I2C</strong>
<ul>
<li>Updated I2C_IsAcknowledgeFailed() API to avoid I2C in busy state if NACK received after transmitting register address.</li>
<li>Fix written reserved bit 28 in I2C_CR2 register</li>
<li>Update to handle errors in polling mode.</li>
<li>Rename I2C_IsAcknowledgeFailed() to I2C_IsErrorOccurred() and correctly manage when error occurs.</li>
<li>Update to fix issue detected due to low system frequency execution (HSI).</li>
<li>Declare an internal macro link to DMA macro to check remaining data: I2C_GET_DMA_REMAIN_DATA.</li>
</ul></li>
<li><strong>HAL LPTIM</strong>
<ul>
<li>Add check on PRIMASK register to prevent from enabling unwanted global interrupts within LPTIM_Disable() and LL_LPTIM_Disable().</li>
</ul></li>
<li><strong>HAL Generic</strong>
<ul>
<li>Fix HAL_Init_Tick() priority handling for alternate (non SysTick) time bases.</li>
</ul></li>
<li><strong>HAL IRDA</strong>
<ul>
<li>Improve header description of IRDA_WaitOnFlagUntilTimeout() function.</li>
<li>Add a check on the IRDA parity before enabling the parity error interrupt.</li>
<li>Add const qualifier for read only pointers for API prototypes.</li>
<li>Fix wrong cast when computing the USARTDIV value in IRDA_SetConfig().</li>
</ul></li>
<li><strong>HAL RTC_BKP</strong>
<ul>
<li>Add an exit condition to the RTC_EnterInitMode and HAL_RTC_DeInit functions to avoid the infinite loop when initializing and de-initializing the RTC.</li>
<li>Add use of macros _\_RTC_<>_EXTI_ENABLE_IT() in case of DUAL_CORE configuration inside functions HAL_RTC_SetAlarm_IT(), HAL_RTCEx_SetWakeUpTimer_IT(),HAL_RTCEx_SetTimeStamp_IT(), and HAL_RTCEx_SetTamper_IT().</li>
</ul></li>
<li><strong>HAL DBGMCU</strong>
<ul>
<li>In Legacy/stm32_hal_legacy.h, exclude HAL_EnableDBG<em>Mode() HAL_DisableDBG</em>Mode() declarations as still defined in stm32h7xx_hal.c.</li>
</ul></li>
<li><strong>HAL NOR</strong>
<ul>
<li>Align HAL_NOR_Init() API with core of the function when write operation is disabled to avoid HardFault.</li>
</ul></li>
<li><strong>HAL SDMMC</strong>
<ul>
<li>Fix an issue with HAL_SD_GetCardState().</li>
<li>Fix to take into consideration if the received RCA is 0x0 or not.</li>
</ul></li>
<li><strong>LL RTC_BKP</strong>
<ul>
<li>Fix IS_LL_RTC_MONTH assert check.</li>
</ul></li>
<li><strong>HAL DMA</strong>
<ul>
<li>Update HAL_DMA_IRQHandler() API to set the DMA state before unlocking access to the DMA handle.</li>
<li>Manage the case of an invalid value of CallbackID passed to the HAL_DMA_RegisterCallback() API.</li>
</ul></li>
<li><strong>HAL SMARTCARD</strong>
<ul>
<li>Improve header description of SMARTCARD_WaitOnFlagUntilTimeout() function.</li>
<li>Add const qualifier for read only pointers in API prototypes.</li>
<li>Fix wrong cast when computing the USARTDIV value in SMARTCARD_SetConfig().</li>
</ul></li>
<li><strong>LL HSEM</strong>
<ul>
<li>Fix an issue where LL_HSEM_1StepLock uses HSEM_R_LOCK instead of HSEM_RLR_LOCK while checking the RLR register.</li>
</ul></li>
<li><strong>HAL RNG</strong>
<ul>
<li>Add check to avoid false timeout detection in case of preemption.</li>
</ul></li>
<li><strong>HAL ETH</strong>
<ul>
<li>Correct wrong call to DMAErrorCallback() instead of MACErrorCallback().</li>
</ul></li>
<li><strong>HAL/LL USB</strong>
<ul>
<li>hal_hcd: fix added to avoid compiler otmization on count variable used for USB HAL timeout loop check.</li>
<li>hal_pcd: added missing registered callbacks check for HAL_HCD_HC_NotifyURBChange_Callback().</li>
<li>hal_pcd: New API HAL_PCD_SetTestMode() added to handle USB device high speed Test modes.</li>
<li>hal_pcd: setting SNAK for EPs not required during device reset.</li>
<li>ll_USB: change added in USB_SetCurrentMode to improve required wait timing to change core mode.</li>
<li>ll_USB: remove non required 200ms delay during host initialization.</li>
<li>ll_USB: fix added to USB_FlushRxFifo() and USB_FlushTxFifo() APIs by adding check on AHB master IDLE state before flushing the USB FIFO.</li>
<li>ll_USB: fix added to avoid resetting host channel direction during channel halt.</li>
</ul></li>
<li><strong>HAL USB_OTG</strong>
<ul>
<li>USB LL driver fix on USB_HC_Halt() function, should not clear channel direction during halt.</li>
<li>USB HAL: fix unexpected HAL_TIMEOUT during USB core reset due to compiler optimization.</li>
</ul></li>
<li><strong>HAL IWDG</strong>
<ul>
<li>Add LSI startup time in default IWDG timeout calculation (HAL_IWDG_DEFAULT_TIMEOUT).</li>
</ul></li>
</ul>
<h2 id="known-limitations-1">Known Limitations</h2>
<ul>
<li><strong>HAL/ETH</strong>
<ul>
<li>A full rework of the ETH HAL driver is planned in order to fix several issues including better synchronization with TCPIP stack for instance LwIP</li>
</ul></li>
</ul>
<h2 id="backward-compatibility-1">Backward compatibility</h2>
<ul>
<li>None</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true"><strong>V1.10.0 / 12-February-2021</strong></label>
<div>
<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li><p>General updates to fix known defects and implementation enhancements</p></li>
<li><p>Fix minor issues related to English typo in comments</p></li>
<li>Update stm32h7xx_hal_def.h implementation to support MDK-ARM AC6 compiler
<ul>
<li>Notes:
<ul>
<li>Only HAL and LL driver are compliant with MDK-ARM AC6 compiler. No warning on these drivers when using “AC5-like warning” in MDK-ARM project settings<br />
</li>
<li>Template projects updated with “Use default compiler version 6” setting and “AC5-like warning” setting</li>
</ul></li>
</ul></li>
<li><strong>HAL</strong>:
<ul>
<li>stm32h7xx_hal.h and stm32h7xx_hal.c:
<ul>
<li>Fix implementation values of SYSCFG_VREFBUF_VOLTAGE_SCALE0 to SYSCFG_VREFBUF_VOLTAGE_SCALE3 defines</li>
<li>Delimit “HAL_EnableDomain3DBGStopMode” and “HAL_DisableDomain3DBGStopMode” APIs with the presence of the “DBGMCU_CR_DBG_STOPD3” field definition (from the CMSIS device header file)<br />
</li>
<li>Delimit “HAL_EnableDomain3DBGStandbyMode” and “HAL_DisableDomain3DBGStandbyMode” APIs with the presence of the “DBGMCU_CR_DBG_STANDBYD3” field definition (from the CMSIS device header file)</li>
<li>Update comments of HAL_EnableCompensationCell and HAL_DisableCompensationCell according to the STM32H7 product data-sheet</li>
</ul></li>
<li>stm32h7xx_hal_conf_template.h:
<ul>
<li>Update HSE_STARTUP_TIMEOUT define value to 100 ms instead of 5000 ms</li>
<li>Update USE_SD_TRANSCEIVER define default value to zero Notes: This define shall be set in the target project according to the given board: set to 1 in case of an SD transceiver is present or zero if not</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL ADC</strong>:
<ul>
<li>stm32h7xx_hal_adc.h:
<ul>
<li>stm32h7xx_hal_adc_ex.h: Update IS_ADC_RIGHT_BIT_SHIFT macro implementation to add support for ADC_RIGHTBITSHIFT_9, ADC_RIGHTBITSHIFT_10 and ADC_RIGHTBITSHIFT_11 values</li>
</ul></li>
<li>stm32h7xx_hal_adc.c/stm32h7xx_hal_adc_ex.c:
<ul>
<li>Update timeout mechanism to avoid false timeout detection in case of preemption</li>
</ul></li>
</ul></li>
<li><strong>HAL CEC</strong>:
<ul>
<li>stm32h7xx_hal_cec.c:
<ul>
<li>Update “HAL_CEC_IRQHandler” implementation to avoid extra byte sent with CEC command</li>
</ul></li>
</ul></li>
<li><strong>HAL CRYP</strong>:
<ul>
<li>stm32h7xx_hal_cryp.h:
<ul>
<li>Update CRYP_ConfigTypeDef structure to add “DataWidthUnit” field allowing to set the header width unit</li>
</ul></li>
<li>stm32h7xx_hal_cryp.c:
<ul>
<li>Update the implementation of the “CRYP_GCMCCM_SetHeaderPhase” function to support the header width unit setting</li>
</ul></li>
<li>stm32h7xx_hal_cryp_ex.c:
<ul>
<li>Update the implementation of the “HAL_CRYPEx_AESGCM_GenerateAuthTAG” function to support the header width unit setting</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL EXTI</strong>:
<ul>
<li>stm32h7xx_hal_exti.h:
<ul>
<li>Update IS_EXTI_PROPERTY to IS_EXTI_CONFIG_LINE macros implementation using “<strong>EXTI_LINE</strong>” instead of “<strong>LINE</strong>” o avoid clash with compiler key word “<strong>LINE</strong>”</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL ETH</strong>:
<ul>
<li>stm32h7xx_hal_eth.h:
<ul>
<li>New private fields “PacketAddress”, “CurrentPacketAddress” and “BuffersInUse” added to the “ETH_TxDescListTypeDef” structure</li>
</ul></li>
<li>stm32h7xx_hal_eth.c:
<ul>
<li>Update implementation of “ETH_Prepare_Tx_Descriptors” function to improve TX performance using the above “ETH_TxDescListTypeDef” structure new fields</li>
</ul></li>
<li>Notes:
<ul>
<li>This implementation allows to improve packet transmission performance using NetX Duo TCPIP stack, however a more elaborated implementation will be provided in next release</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL FLASH</strong>:
<ul>
<li>stm32h7xx_hal_flash_ex.h:
<ul>
<li>Remove unused defines “OB_WWDG_SW” and “OB_WWDG_HW” and corresponding “IS_OB_WWDG_SOURCE” macro</li>
<li>Delimit “OB_SWAP_BANK_DISABLE” and “OB_SWAP_BANK_ENABLE” defines with “#if defines (DUAL_BANK)” as swap bank is available for dual bank devices only. same for macro “IS_OB_USER_SWAP_BANK”</li>
<li>Update “OB_USER_ALL” macro implementation with variants for dual bank, single bank, dual core and single core devices</li>
</ul></li>
<li>stm32h7xx_hal_flash.c:
<ul>
<li>Update “HAL_FLASH_Program” description with details for “FlashAddress” and “DataAddress” alignment requirements</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL GPIO</strong>:
<ul>
<li>stm32h7xx_hal_gpio.c:
<ul>
<li>Update and fix HAL_GPIO_TogglePin implementation to allow toggle of multiple pin</li>
</ul></li>
<li>stm32h7xx_ll_gpio.h:
<ul>
<li>Update and fix LL_GPIO_TogglePin implementation to allow toggle of multiple pin</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL HRTIM</strong>:
<ul>
<li>stm32h7xx_hal_hrtim.c:
<ul>
<li>Update HRTIM_HRTIM_ISR implementation to optimize the read flags</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL IWDG</strong>:
<ul>
<li>stm32h7xx_hal_iwdg.c:
<ul>
<li>Update timeout mechanism to avoid false timeout detection in case of preemptio</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL LPTIM</strong>
<ul>
<li>stm32h7xx_hal_lptim.c:
<ul>
<li>Update “HAL_LPTIM_Init” implementation to improve behavior for external clock configuration</li>
</ul></li>
</ul></li>
<li><strong>HAL NAND</strong>:
<ul>
<li>stm32h7xx_hal_nand.c:
<ul>
<li>Update implementation of “HAL_NAND_Read_SpareArea_16b” and “HAL_NAND_Write_SpareArea_16b” to fix an issue with the spare area Column address calculation</li>
<li>Update implementation of “HAL_NAND_Write_Page_16b” and “HAL_NAND_Read_Page_16b” APIs implementation to fix an issue with the page calculation of 8 bits memories</li>
</ul></li>
</ul></li>
<li><strong>HAL NOR</strong>:
<ul>
<li>stm32h7xx_hal_nor.c:
<ul>
<li>Fix “HAL_NOR_ProgramBuffer” API implementation regarding the current and end address calculation</li>
<li>Update NOR APIs implementation to support some specific memories</li>
</ul></li>
</ul></li>
<li><strong>HAL RCC</strong>:
<ul>
<li>stm32h7xx_hal_rcc.c:
<ul>
<li>Update “HAL_RCC_DeInit” implementation to reset “HSEEXT” field</li>
</ul></li>
<li>stm32h7xx_hal_rcc_ex.c:
<ul>
<li>Update “HAL_RCCEx_PeriphCLKConfig” implementation with CEC Configuration</li>
<li>Update “HAL_RCCEx_GetPeriphCLKFreq” implementation to:
<ul>
<li>Check oscillator ready flag</li>
<li>Get FDCAN clock source</li>
</ul></li>
<li>Update implementation of “HAL_RCCEx_GetPLL1ClockFreq” to use HSI in default case as per the specification</li>
</ul></li>
</ul></li>
<li><strong>HAL RNG</strong>:
<ul>
<li>stm32h7xx_hal_rng.h:
<ul>
<li>Add “RNG_RecoverSeedError” function prototype</li>
</ul></li>
<li>stm32h7xx_hal_rng.c:
<ul>
<li>Update “HAL_RNG_GenerateRandomNumber” function implementation to check seed error if any</li>
<li>Update “HAL_RNG_IRQHandler” function implementation to check seed error if any</li>
<li>Add “RNG_RecoverSeedError” function</li>
</ul></li>
<li>stm32h7xx_hal_rng_ex.h:
<ul>
<li>Add “HAL_RNGEx_RecoverSeedError” API prototype</li>
</ul></li>
<li>stm32h7xx_hal_rng_ex.c:
<ul>
<li>Add “HAL_RNGEx_RecoverSeedError” function</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL SDMMC</strong>:
<ul>
<li>stm32h7xx_hal_mmc.c:
<ul>
<li>Update implementation of “HAL_MMC_Init” function to support SDMMC power class</li>
<li>Add “HAL_MMC_GetCardExtCSD” function to get card extended information<br />
</li>
<li>Update “HAL_MMC_ConfigWideBusOperation” function implementation to support SDMMC power class</li>
<li>Update “HAL_MMC_ConfigSpeedBusOperation” function implementation to adapt the speed to the card type</li>
<li>Update “HAL_MMC_GetSupportedSecRemovalType” function implementation to support Secure Removal type</li>
<li>Update “HAL_MMC_InitCard” implementation to avoid potential division by zero</li>
<li>Update to support native 4KB sector size<br />
</li>
</ul></li>
<li>stm32h7xx_hal_mmc_ex.c
<ul>
<li>Update to support native 4KB sector size</li>
</ul></li>
<li>stm32h7xx_hal_mmc.h:
<ul>
<li>Add eMMC_DUAL_VOLTAGE_RANGE and eMMC_LOW_VOLTAGE_RANGE voltage mode</li>
<li>Add prototype for HAL_MMC_GetCardExtCSD API</li>
</ul></li>
<li>stm32h7xx_hal_sd.c:
<ul>
<li>Update “HAL_SD_InitCard” implementation to avoid potential division by zero</li>
</ul></li>
<li>stm32h7xx_ll_sdmmc.c
<ul>
<li>Add “SDMMC_CmdSetRelAddMmc” function to set relative address</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL SPI</strong>
<ul>
<li>Update “HAL_SPI_TransmitReceive_IT” implementation to disable RXP and TXP interrupt when DXP is enabled</li>
<li>Update “HAL_SPI_Init” implementation with NSS Software Management</li>
<li>stm32h7xx_ll_spi.c:
<ul>
<li>Update “LL_SPI_Init” implementation to set the internal SS level</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL TIM</strong>:
<ul>
<li>stm32h7xx_ll_tim.h:
<ul>
<li>Fix “LL_TIM_GetCounterMode” implementation to handle all possible return combinations</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL UART</strong>:
<ul>
<li>stm32h7xx_hal_uart.h:
<ul>
<li>Add “HAL_UART_RxTypeTypeDef” type with possible values HAL_UART_RECEPTION_STANDARD, HAL_UART_RECEPTION_TOIDLE, HAL_UART_RECEPTION_TORTO or HAL_UART_RECEPTION_TOCHARMATCH</li>
<li>Update “UART_HandleTypeDef” structure to add “RxEventCallback”</li>
<li>Add “pUART_RxEventCallbackTypeDef” type</li>
</ul></li>
<li>stm32h7xx_hal_uart_ex.h:
<ul>
<li>Add APIs prototypes: HAL_UARTEx_ReceiveToIdle, HAL_UARTEx_ReceiveToIdle_IT and HAL_UARTEx_ReceiveToIdle_DMA</li>
</ul></li>
<li>stm32h7xx_hal_uart.c:
<ul>
<li>Update “HAL_UART_DeInit” implementation to set the “ReceptionType” to HAL_UART_RECEPTION_STANDARD<br />
</li>
<li>Add “HAL_UART_RegisterRxEventCallback” and “HAL_UART_UnRegisterRxEventCallback” APIs implementation</li>
<li>Update “HAL_UART_Receive”, “HAL_UART_Receive_IT” and “HAL_UART_Receive_DMA” to set the “ReceptionType” to HAL_UART_RECEPTION_STANDARD</li>
<li>Update “HAL_UART_Abort”, “HAL_UART_AbortReceive”, “HAL_UART_Abort_IT” and “HAL_UART_AbortReceive_IT” to disable IDLEIE interrupt in case of reception till IDLE</li>
<li>Update “HAL_UART_IRQHandler” to handle reception till IDLE</li>
<li>Add “HAL_UARTEx_RxEventCallback” weak callback</li>
</ul></li>
<li>stm32h7xx_hal_uart_ex.c:
<ul>
<li>Add “HAL_UARTEx_ReceiveToIdle”, “HAL_UARTEx_ReceiveToIdle_IT” and “HAL_UARTEx_ReceiveToIdle_DMA” APIs implementation</li>
</ul></li>
<li>stm32h7xx_ll_lpuart.h
<ul>
<li>Update “LL_LPUART_SetBaudRate” implementation to avoid potential division by zero</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL USART</strong>:
<ul>
<li>stm32h7xx_ll_usart.h:
<ul>
<li>Update “LL_USART_SetBaudRate” implementation to avoid potential division by zero</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL USB</strong>:
<ul>
<li>Update to ensure to have coherency between USB APIs start and stop which should mainly control device connect and disconnect of the USB RPU</li>
<li>Fix ping with DMA OFF, fix Data toggle issue with DMA multi max packet size transfers and clean up device and core speeds</li>
<li>Enhance Host CH ERR and halt management</li>
<li>Update to notify MW upper layers when transaction completes with an error</li>
<li>Update to fix USB OTG read FIFO packet in stm32h7xx_ll_usb.c file</li>
<li>Update to support USB OTG FIFO with scatter gather</li>
</ul></li>
<li><strong>LL SYSTEM</strong>:
<ul>
<li>stm32h7xx_ll_system.h:
<ul>
<li>Update LL_SYSCFG_EnableCompensationCell and LL_SYSCFG_DisableCompensationCell according to the STM32H7 product data-sheet</li>
</ul></li>
</ul></li>
</ul>
<h2 id="known-limitations-2">Known Limitations</h2>
<ul>
<li><strong>HAL/ETH</strong>
<ul>
<li>A full rework of the ETH HAL driver is planned in order to fix several issues including better synchronization with TCPIP stack for instance LwIP</li>
</ul></li>
</ul>
<h2 id="backward-compatibility-2">Backward compatibility</h2>
<ul>
<li>None</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true"><strong>V1.9.0 / 29-May-2020</strong></label>
<div>
<h2 id="main-changes-3">Main Changes</h2>
<ul>
<li>First official release of the STM32CubeH7 Firmware Package supporting <strong>STM32H72x/3x</strong> new devices</li>
<li>General updates to fix known defects and implementation enhancements</li>
<li><strong>HAL</strong>: generic, Update to support <strong>STM32H72x/3x</strong> new devices
<ul>
<li>stm32h7xx_hal.h:
<ul>
<li>Add SYSCGF defines for Adc2 Alternate Connection on Vinp[16] and Vinp[17]</li>
<li>Add HAL_SYSCFG_ADC2ALT_Rout0Config and HAL_SYSCFG_ADC2ALT_Rout1Config APIs allowing to configure Adc2 Alternate Connection on Vinp[16] or Vinp[17]<br />
</li>
<li>Update EXTI lines definitions for <strong>STM32H72x/3x</strong> devices</li>
<li>Add __HAL_DBGMCU_FREEZE_I2C5/__HAL_DBGMCU_UnFreeze_I2C5, __HAL_DBGMCU_FREEZE_TIM23/__HAL_DBGMCU_UnFreeze_TIM23 and __HAL_DBGMCU_FREEZE_TIM24/__HAL_DBGMCU_UnFreeze_TIM24 macros</li>
</ul></li>
<li>stm32h7xx_hal_conf_template.h:
<ul>
<li>Add CORDIC and FMAC modules enabling (new peripherals in STM32H723xx/33xx/25xx/35xx/30xx devices)</li>
<li>Add CORDIC and FMAC register callback enabling</li>
</ul></li>
<li>stm32h7xx_hal.c:
<ul>
<li>Add implementation of HAL_SYSCFG_ADC2ALT_Rout0Config and HAL_SYSCFG_ADC2ALT_Rout1Config APIs implementation allowing to configure Adc2 Alternate Connection on Vinp[16] or Vinp[17]</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL ADC</strong>: Updated to support <strong>STM32H72x/3x</strong> devices: ADC1/2 (16 bits ADCs in D2 domain) and ADC3 (12 Bits ADC in D3 domain)
<ul>
<li>3 compilations defines are used:
<ul>
<li>ADC_VER_V5_V90 : for <strong>STM32H72x/3x</strong> ADCs : ADC1/2 (16 bits ADCs in D2 domain) and ADC3 (12 Bits ADC in D3 domain)</li>
<li>ADC_VER_V5_3: For STM32H7Ax/Bx : ADC1/2 (16 bits ADCs in D2/CDC domain)</li>
<li>ADC_VER_V5_X: For STM32H74x/5x : ADC1/2 (16 bits ADCs in D2/CDC domain) and ADC3 (16 Bits ADC in D3 domain)
<ul>
<li>supporting rev.Y and rev.V devices</li>
</ul></li>
<li>These defines are available on each CMSIS device header file stm32h723xx.h/stm32h733xx.h …/STM32H7a3xx.h/STM32H7b3xx.h/…/stm32h743xx/stm32h773xx…</li>
</ul></li>
</ul></li>
<li><strong>HAL DFSDM</strong>:
<ul>
<li>stm32h7xx_hal_dfsdm.h:
<ul>
<li>Use conditional define on STM32H7_DEV_ID for external triggers definition instead of device RPN definitions (STM32H7_DEV_ID define available on CMSIS device header files for each STM32H7 line : <strong>STM32H72x/3x</strong>/4x/5x/Ax/Bx)</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL DMA</strong>:
<ul>
<li>stm32h7xx_ll_bdma.h, stm32h7xx_ll_dma.h and stm32h7xx_ll_dmamux.h:
<ul>
<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
<li>Add requests definitions for FMAC, CORDIC, I2C5, TIM23 and TIM24 new peripherals available on <strong>STM32H72x/3x</strong> devices</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL CORDIC</strong>:
<ul>
<li>New HAL and LL drivers to support CORDIC peripheral available on new <strong>STM32H72x/3x</strong> new devices</li>
</ul></li>
<li><strong>HAL CRYP</strong>:
<ul>
<li>stm32h7xx_hal_cryp.c/.h and stm32h7xx_hal_cryp_ex.c: Update doxygen documentation</li>
</ul></li>
<li><strong>HAL DCMI</strong>:
<ul>
<li>stm32h7xx_hal_dcmi.c:
<ul>
<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
</ul></li>
</ul></li>
<li><strong>HAL ETH</strong>:
<ul>
<li>stm32h7xx_hal_eth.h:
<ul>
<li><p>Update ETH_DMADescTypeDef definition: remove useless volatile of the BackupAddr0 and BackupAddr1 fields since they are not used by ETH DMA.</p></li>
<li>stm32h7xx_hal_eth.c:
<ul>
<li>HAL_ETH_Start_IT:
<ul>
<li>Move the update of the ETH gState and RxState after ETH IT Start.</li>
<li>Remove useless INCR_RX_DESC_INDEX(descindex, 1U) when enabling Interrupt on Completion fields</li>
</ul></li>
<li>HAL_ETH_Stop_IT:
<ul>
<li>Clear Fatal bus interrupt and Abnormal Interrupt Summary Enable</li>
<li>Clear interrupt Enabled on Completion for all used descriptors</li>
</ul></li>
<li>HAL_ETH_Transmit:
<ul>
<li>Set ETH gState to HAL_ETH_STATE_ERROR when timeout error occurred</li>
<li>Remove unnecessary set of ETH HAL State to Ready</li>
</ul></li>
<li>HAL_ETH_Transmit_IT:
<ul>
<li>Set ETH ErrorCode to HAL_ETH_ERROR_PARAM when parameter is not valid and use logical OR when updating the ErrorCode</li>
</ul></li>
<li>HAL_ETH_IsRxDataAvailable
<ul>
<li>Updating the CurRxDesc and FirstAppDesc values when building descriptor of an invalid/incomplete</li>
</ul></li>
</ul></li>
</ul></li>
</ul></li>
<li><strong>HAL/LL EXTI</strong>: Updated to support <strong>STM32H72x/3x</strong> devices
<ul>
<li>stm32h7xx_hal_exti.h and stm32h7xx_ll_exti.h:
<ul>
<li>Update EXTI lines definition with according to its availability on STM32H74x/5x STM32Ax/Bx or <strong>STM32H72x/3x</strong> devices</li>
</ul></li>
</ul></li>
<li><strong>HAL FDCAN</strong>:
<ul>
<li>stm32h7xx_hal_fdcan.h:
<ul>
<li>Add guard on FDCAN1 peripheral availability on top of the header file</li>
</ul></li>
<li>stm32h7xx_hal_fdcan.c:
<ul>
<li>Add guard on FDCAN1 peripheral availability on top of the source file</li>
<li>Add FDCAN_TIMEOUT_COUNT private define to be used when a timeout based on number of trials is needed</li>
<li>Fix HAL_FDCAN_GetRxMessage function implementation to discard first message in FIFO when overwrite status is on</li>
</ul></li>
</ul></li>
<li><strong>HAL FLASH</strong>:
<ul>
<li>stm32h7xx_hal_flash.h:
<ul>
<li>Update to use DUAL_BANK define in macros __HAL_FLASH_ENABLE_IT, __HAL_FLASH_DISABLE_IT, __HAL_FLASH_GET_FLAG and __HAL_FLASH_CLEAR_FLAG:
<ul>
<li>Two different implementations depending of dual bank device (STM32H74x/5x/Ax/Bx) of single bank device (<strong>STM32H72x/3x</strong>/50/B0)</li>
</ul></li>
<li>Delimit Bank2 private macros with DUAL_BANK define<br />
</li>
<li>Add IS_FLASH_PROGRAM_ADDRESS_OTP and IS_FLASH_PROGRAM_ADDRESS private macros used within the Flash HAL driver for STM32H7Ax/Bx devices</li>
</ul></li>
<li>stm32h7xx_hal_flash_ex.h:
<ul>
<li>Update to support option bytes TCM_AXI_SHARED and CPUFREQ_BOOST available on <strong>STM32H72x/3x</strong> new devices</li>
</ul></li>
<li>stm32h7xx_hal_flash.c:
<ul>
<li>Update implementation to consider dual bank devices (STM32H74x/5x and STM32H7Ax/Bx) and single bank devices (<strong>STM32H72x/3x</strong>)</li>
</ul></li>
<li>stm32h7xx_hal_flash_ex.c:
<ul>
<li>Update implementation to consider dual bank devices (STM32H74x/5x and STM32H7Ax/Bx) and single bank devices (<strong>STM32H72x/3x</strong>)</li>
<li>Update implementation to to support option bytes TCM_AXI_SHARED and CPUFREQ_BOOST available on <strong>STM32H72x/3x</strong> new devices</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL FMAC</strong>:
<ul>
<li>New HAL and LL drivers to support FMAC peripheral available on new <strong>STM32H72x/3x</strong> new devices</li>
</ul></li>
<li><strong>HAL/LL GPIO</strong>:
<ul>
<li>stm32h7xx_hal_gpio_ex.h:
<ul>
<li>Update Alternate functions definition for new <strong>STM32H72x/3x</strong> devices</li>
</ul></li>
<li>stm32h7xx_hal_gpio.c:
<ul>
<li>Update HAL_GPIO_DeInit implementation to re-order register sequence and avoid inconsistent ISR behavior</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL USB</strong>:
<ul>
<li>stm32h7xx_hal_hcd.h:
<ul>
<li>Update HCD_SPEED_FULL HCD_SPEED_LOW defines values with respect to new defines in stm32h7xx_ll_usb.h (USBH_FSLS_SPEED)</li>
</ul></li>
<li>stm32h7xx_hal_hcd.c:
<ul>
<li>Update HCD_HC_IN_IRQHandler to handle USB_OTG_HCINT_BBERR IT</li>
</ul></li>
<li>stm32h7xx_ll_usb.h:
<ul>
<li>USBH_FS_SPEED define renamed to USBH_FSLS_SPEED (no impact as used by the stm32h7xx_hal_hcd.h that has been updated)</li>
</ul></li>
<li>stm32h7xx_ll_usb.c:
<ul>
<li>Update USB_DeactivateDedicatedEndpoint implementation to ensure to disable EP during deactivation</li>
<li>Update USB_HostInit implementation to fix compilation error when host core is low speed</li>
</ul></li>
</ul></li>
<li>__HAL/LL HRTIM:
<ul>
<li>stm32h7xx_hal_hrtim.c:
<ul>
<li>Update Doxygen documentation</li>
</ul></li>
<li>stm32h7xx_ll_hrtim.h:
<ul>
<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL I2C</strong>:
<ul>
<li>stm32h7xx_hal_i2c_ex.h:
<ul>
<li>Update I2CEx_FastModePlus definition to add I2C_FASTMODEPLUS_I2C5 define allowing to support for I2C5 instance available on <strong>STM32H72x/3x</strong> devices</li>
</ul></li>
<li>stm32h7xx_hal_i2c.c:
<ul>
<li>Fix implementation of HAL_I2C_Master_Seq_Transmit_IT, HAL_I2C_Master_Seq_Transmit_DMA, HAL_I2C_Master_Seq_Receive_IT and HAL_I2C_Master_Seq_Receive_DMA
<ul>
<li>Update xfermode upon MAX_NBYTE_SIZE reached</li>
</ul></li>
<li>Improve implementation of I2C_ITMasterCplt function<br />
</li>
</ul></li>
<li>stm32h7xx_hal_i2c_ex.c:
<ul>
<li>Update doxygen documentation with references to I2C5 instance available on <strong>STM32H72x/3x</strong> devices</li>
</ul></li>
<li>stm32h7xx_ll_i2c.h
<ul>
<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
<li>Fix doxygen documentation</li>
</ul></li>
<li>stm32h7xx_ll_i2c.c
<ul>
<li>Update LL_I2C_DeInit implementation to add support of I2C5 instance available on <strong>STM32H72x/3x</strong> devices</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL I2S</strong>: Update to support <strong>I2S Full Duplex</strong> mode (no backward compatibility break):
<ul>
<li>stm32h7xx_hal_i2s.h:
<ul>
<li>Add HAL_I2S_STATE_BUSY_TX_RX state</li>
<li>Add I2S_IT_DXP IT and I2S_FLAG_DXP flag definitions</li>
<li>Update value of I2S_FLAG_MASK define</li>
<li>Add extension <strong>Full Duplex</strong> APIs Transmit/Receive APIs (Polling, IT and DMA)
<ul>
<li>HAL_I2SEx_TransmitReceive,HAL_I2SEx_TransmitReceive_IT and HAL_I2SEx_TransmitReceive_DMA</li>
</ul></li>
<li>Add extension <strong>Full Duplex</strong> callbacks: HAL_I2SEx_TxRxHalfCpltCallback and HAL_I2SEx_TxRxCpltCallback</li>
<li>Update register callback defines to support <strong>Full Duplex</strong> TxRx complete callbacks</li>
<li>Add IS_I2S_FULLDUPLEX private macro use in the HAL I2S driver</li>
</ul></li>
<li>stm32h7xx_hal_i2s.c:
<ul>
<li>Update HAL_I2S_Init, HAL_I2S_RegisterCallback and HAL_I2S_UnRegisterCallback implementation to consider TxRxCpltCallback and TxRxHalfCpltCallback callbacks</li>
<li>Add HAL_I2SEx_TransmitReceive, HAL_I2SEx_TransmitReceive_IT and HAL_I2SEx_TransmitReceive_DMA APIs implementation</li>
<li>Update HAL_I2S_IRQHandler implementation to consider full duplex mode</li>
<li>Add HAL_I2SEx_TxRxHalfCpltCallback and HAL_I2SEx_TxRxCpltCallback weak callbacks<br />
</li>
<li>Add I2SEx_DMATxRxCplt and I2SEx_DMATxRxHalfCplt private functions</li>
<li>Update implementation of I2S_Transmit_16Bit_IT and I2S_Transmit_32Bit_IT functions</li>
<li>Update implementation of I2S_Receive_16Bit_IT and I2S_Receive_32Bit_IT functions</li>
<li>Update doxygen documentation</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL IWDG</strong>:
<ul>
<li>stm32h7xx_hal_iwdg.c:
<ul>
<li>Update HAL_IWDG_DEFAULT_TIMEOUT define value to consider LSI value instead of hardcoded value</li>
<li>Update doxygen documentation</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL MDMA</strong>:
<ul>
<li>stm32h7xx_hal_mdma.h:
<ul>
<li>Add __HAL_MDMA_SET_COUNTER and __HAL_MDMA_GET_COUNTER macros (same macros as the HAL DMA)</li>
</ul></li>
<li>stm32h7xx_ll_mdma.h
<ul>
<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL SD/MMC</strong>: Add support for Sanitize and Discard functions:
<ul>
<li>stm32h7xx_hal_mmc.h:
<ul>
<li>Added APIs: HAL_MMC_EraseSequence, HAL_MMC_Sanitize, HAL_MMC_ConfigSecRemovalType and HAL_MMC_GetSupportedSecRemovalType</li>
<li>added defines:
<ul>
<li>defines used for HAL_MMC_EraseSequence API:
<ul>
<li>HAL_MMC_ERASE, HAL_MMC_TRIM, HAL_MMC_DISCARD, HAL_MMC_SECURE_ERASE, HAL_MMC_SECURE_TRIM_STEP1 and HAL_MMC_SECURE_TRIM_STEP2</li>
</ul></li>
<li>defines used for HAL_MMC_ConfigSecRemovalType/HAL_MMC_GetSupportedSecRemovalType API:
<ul>
<li>HAL_MMC_SRT_ERASE, HAL_MMC_SRT_WRITE_CHAR_ERASE, HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM and HAL_MMC_SRT_VENDOR_DEFINED</li>
</ul></li>
</ul></li>
</ul></li>
<li>stm32h7xx_hal_mmc.c:
<ul>
<li>Add implementation of APIs HAL_MMC_EraseSequence, HAL_MMC_Sanitize, HAL_MMC_ConfigSecRemovalType and HAL_MMC_GetSupportedSecRemovalType</li>
<li>Update implementation of MMC_HighSpeed, MMC_DDR_Mode private functions</li>
<li>Update HAL_MMC_InitCard to allow upper to 200MHz SDMM Clock<br />
</li>
</ul></li>
<li>stm32h7xx_hal_sd.c:
<ul>
<li>Update HAL_SD_Erase implementation to consider private SDMMC_CmdErase function update</li>
<li>Update HAL_SD_InitCard to allow upper to 200MHz SDMM Clock<br />
</li>
</ul></li>
<li>stm32h7xx_ll_sdmmc.h (HAL core driver, not a user driver)
<ul>
<li>Update SDMMC_CmdErase function to add EraseType parameter</li>
</ul></li>
<li>stm32h7xx_ll_sdmmc.c:
<ul>
<li>Update implementation of SDMMC_CmdErase to add EraseType parameter</li>
<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL OPAMP</strong>:
<ul>
<li>stm32h7xx_ll_opamp.h:
<ul>
<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL OTFDEC</strong>:
<ul>
<li>stm32h7xx_hal_otfdec.h
<ul>
<li>Add implementation of macros __HAL_OTFDEC_GET_FLAG and __HAL_OTFDEC_CLEAR_FLAG</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL PWR</strong>:
<ul>
<li>stm32h7xx_hal_pwr.h:
<ul>
<li>Update __HAL_PWR_VOLTAGESCALING_CONFIG, __HAL_PWR_GET_FLAG, __HAL_PWR_GET_WAKEUPFLAG and __HAL_PWR_CLEAR_WAKEUPFLAG macros implementation to support <strong>STM32H72x/3x</strong> devices</li>
</ul></li>
<li>stm32h7xx_hal_pwr_ex.h:
<ul>
<li>Update to delimit wakeup pins 3 and 5 definitions according to their availability (not available on <strong>STM32H72x/3x</strong> devices)<br />
</li>
</ul></li>
<li>stm32h7xx_hal_pwr.c:
<ul>
<li>Update Doxygen documentation to consider <strong>STM32H72x/3x</strong> devices</li>
</ul></li>
<li>stm32h7xx_hal_pwr_ex.c:
<ul>
<li>Update HAL_PWREx_ControlVoltageScaling implementation for <strong>STM32H72x/3x</strong> devices<br />
</li>
<li>Update HAL_PWREx_EnterSTOPMode implementation to domain Deep sleep entry foe each Core (CM7/CM4)</li>
<li>Update HAL_PWREx_WAKEUP_PIN_IRQHandler implementation to delimit wakeup pins 3 and 5 usage according to their availability (not available on <strong>STM32H72x/3x</strong> devices)</li>
</ul></li>
<li>stm32h7xx_ll_pwr.h
<ul>
<li>Update to delimit wakeup pins 3 and 5 definitions according to their availability (not available on <strong>STM32H72x/3x</strong> devices)</li>
<li>Update LL_PWR_REGU_VOLTAGE_SCALE0 value to support <strong>STM32H72x/3x</strong> devices</li>
<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
</ul></li>
<li>stm32h7xx_ll_pwr.c
<ul>
<li>Update LL_PWR_DeInit implementation to delimit wakeup pins 3 and 5 usage according to their availability (not available on <strong>STM32H72x/3x</strong> devices)</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL RCC</strong>:
<ul>
<li>stm32h7xx_hal_rcc.h:
<ul>
<li>Fix RCC_HSICALIBRATION_DEFAULT and RCC_CSICALIBRATION_DEFAULT values for STM32H74x/5x rev.V and update __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST and __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST macros implementation to consider STM32H74x/7x rev.Y**</li>
<li>Add FMAC anc CORDIC peripherals Clock enable/disable macros</li>
<li>GPIOI not available on <strong>STM32H72x/3x</strong>, corresponding RCC macro are delimited with GPIOI availability check</li>
<li>Add I2C5, TIM23,TIM24 clock enable/disable macros</li>
<li>SAI2 not available on <strong>STM32H72x/3x</strong>, corresponding RCC macro are delimited with SAI2 availability check</li>
<li>Update __HAL_RCC_AHB3_FORCE_RESET implementation to consider STM32H72x/3x (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)<br />
</li>
<li>Update __HAL_RCC_AHB1_FORCE_RESET implementation to consider STM32H72x/3x (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)<br />
</li>
<li>Update __HAL_RCC_AHB2_FORCE_RESET implementation to consider STM32H72x/3x (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)</li>
<li>Update __HAL_RCC_AHB4_FORCE_RESET implementation to consider STM32H72x/3x (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)</li>
<li>Update __HAL_RCC_APB3_FORCE_RESET implementation to consider STM32H72x/3x (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)</li>
<li>Update __HAL_RCC_APB1L_FORCE_RESET and __HAL_RCC_APB1H_FORCE_RESET implementation to consider <strong>STM32H72x/3x</strong> (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)</li>
<li>Update __HAL_RCC_APB2_FORCE_RESET implementation to consider STM32H72x/3x (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)</li>
<li>Update __HAL_RCC_APB4_FORCE_RESET implementation to consider STM32H72x/3x (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)</li>
<li>Update __HAL_RCC_APB4_FORCE_RESET implementation to consider STM32H72x/3x (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)</li>
<li>Add __HAL_RCC_DTS_CLKAM_ENABLE and __HAL_RCC_DTS_CLKAM_DISABLE macro</li>
</ul></li>
<li>stm32h7xx_hal_rcc_ex.h:
<ul>
<li>Update to support I2C5, TIM23,TIM24 clock setting</li>