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MSX2 TECHNICAL HANDBOOK
-----------------------
Edited by: ASCII Systems Division
Published by: ASCII Coprporation - JAPAN
First edition: March 1987
Text files typed by: Nestor Soriano (Konami Man) - SPAIN
March 1997
Changes from the original:
- In Figure 4.3, "Port#17" indication is corrected to "R#17".
- In Figure 4.4, "00" field in R#17 is corrected to "10".
- In section 3.2.2, subsection "Pattern name table", text "12 low order bits
o the address (A9 to A0)" is corrected to "12 low order bits of the address
(A11 to A0)"
- In Figure 4.17, the numerations of the two last rows in the Screen
correspondence table, originally "22" and "23", are corrected to "25" and
"26" respectively.
- In section 3.2.2, subsection "Blink table", the text "the 9 low order bits
of the address (A9 to A0)" is corrected to "the 8 low order bits of the
address (A8 to A0)".
- In Figure 4.25, indication "Specifies the value of the screen (0 to 15)" is
changed to "Specifies the border colour (0-15)".
- In Figure 4.34, in the screen correspondance table, the three stages of the
screen are named "Upper stage of screen" in the original. This is corrected,
and the stages are named "Upper", "Middle" and "Lower".
- The title of section 3.6.3 is "Screen colour mode specification" in the
original. The word "mode" is erased.
- In section 3.8.2, the text "by writing the 2 high order bits" is corrected
to "by writing the high order bit".
- The title of Figure 4.63 is "Judging the conflict (sprite mode 2)" in the
original. This is corrected to "Judging the conflict (sprite mode 1)".
- In Figure 4.68, indication "Color code = 8 or 4 or 12" is changed to "Color
code = 8 or 4 = 12".
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
CHAPTER 4 - VDP AND DISPLAY SCREEN (Parts 1 to 5)
The MSX2 machines uses an advanced VDP (video display processor) for its
display screen, the V9938 (MSX-VIDEO). This LSI chip allows for several new
graphics features to be accessed by the MSX2 video display. It is also fully
compatible with the TMS9918A used in the MSX1.
Chapter 4 describes how to use this video display processor. It describes
functions not accessible by BASIC. For mode details (e.g. hardware
specifications), see V9938 MSX-VIDEO Technical Data Book (ASCII).
1. MSX-VIDEO CONFIGURATION
The following features of the MSX-VIDEO give it a better display capabilities
than the TMS9918A:
* 512 colours with a 9-bit colour palette
* Max. 512 x 424 dot resolution (when using the interlace)
* Max. 256 colours at the same time
* Full bitmap mode which makes graphic operations easy
* Text display mode of 80 characters per line
* LINE, SEARCH, AREA-MOVE executable by hardware
* Up to 8 sprites on the same horizontal line
* Different colours can be specified for each line in a sprite
* Video signal digitizing feature built-in
* Superimpose feature built-in
1.1 Registers
MSX-VIDEO uses 49 internal registers for its screen operations. These
registers are referred to as "VDP registers" in this book. VDP registers are
classified by function into three groups as described below. The control
register group and status register group can be referred to using VDP(n)
system variables from BASIC.
(1) Control register group (R#0 to R#23, R#32 to R#46)
This is a write-only 8-bit register group controlling MSX-VIDEO actions.
Registers are expressed using the notation R#n. R#0 to R#23 are used to set
the screen mode. R#32 to R#46 are used to execute VDP commands. These VDP
commands will be described in detail in section 5. Control registers R#24 to
R#31 do not exist. The roles of the different control registers are listed in
Table 4.1.
Table 4.1 Control register list
-----------------------------------------------------------------------------
| | Corres- | |
| R#n | ponding | Function |
| | VDP(n) | |
|------+---------+----------------------------------------------------------|
| R#0 | VDP(0) | mode register #0 |
| R#1 | VDP(1) | mode register #1 |
| R#2 | VDP(2) | pattern name table |
| R#3 | VDP(3) | colour table (LOW) |
| R#4 | VDP(4) | pattern generator table |
| R#5 | VDP(5) | sprite attribute table (LOW) |
| R#6 | VDP(6) | sprite pattern generator table |
| R#7 | VDP(7) | border colour/character colour at text mode |
| R#8 | VDP(9) | mode register #2 |
| R#9 | VDP(10) | mode register #3 |
| R#10 | VDP(11) | colour table (HIGH) |
| R#11 | VDP(12) | sprite attribute table (HIGH) |
| R#12 | VDP(13) | character colour at text blinks |
| R#13 | VDP(14) | blinking period |
| R#14 | VDP(15) | VRAM access address (HIGH) |
| R#15 | VDP(16) | indirect specification of S#n |
| R#16 | VDP(17) | indirect specification of P#n |
| R#17 | VDP(18) | indirect specification of R#n |
| R#18 | VDP(19) | screen location adjustment (ADJUST) |
| R#19 | VDP(20) | scanning line number when the interrupt occurs |
| R#20 | VDP(21) | colour burst signal 1 |
| R#21 | VDP(22) | colour burst signal 2 |
| R#22 | VDP(23) | colour burst signal 3 |
| R#23 | VDP(24) | screen hard scroll |
| | | |
| R#32 | VDP(33) | SX: X-coordinate to be transferred (LOW) |
| R#33 | VDP(34) | SX: X-coordinate to be transferred (HIGH) |
| R#34 | VDP(35) | SY: Y-coordinate to be transferred (LOW) |
| R#35 | VDP(36) | SY: Y-coordinate to be transferred (HIGH) |
| R#36 | VDP(37) | DX: X-coordinate to be transferred to (LOW) |
| R#37 | VDP(38) | DX: X-coordinate to be transferred to (HIGH) |
| R#38 | VDP(39) | DY: Y-coordinate to be transferred to (LOW) |
| R#39 | VDP(40) | DY: Y-coordinate to be transferred to (HIGH) |
| R#40 | VDP(41) | NX: num. of dots to be transferred in X direction (LOW) |
| R#41 | VDP(42) | NX: num. of dots to be transferred in X direction (HIGH) |
| R#42 | VDP(43) | NY: num. of dots to be transferred in Y direction (LOW) |
| R#43 | VDP(44) | NY: num. of dots to be transferred in Y direction (HIGH) |
| R#44 | VDP(45) | CLR: for transferring data to CPU |
| R#45 | VDP(46) | ARG: bank switching between VRAM and expanded VRAM |
| R#46 | VDP(47) | CMR: send VDP command |
-----------------------------------------------------------------------------
(2) Status register (S#0 to S#9)
This is a read-only 8-bit register group which reads data from MSX-VIDEO.
Registers are expressed using the notation S#n. The functions of the
registers are listed in Table 4.2.
Table 4.2 Status register list
-----------------------------------------------------------------------------
| | Corres- | |
| S#n | ponding | Function |
| | VDP(n) | |
|------+---------+----------------------------------------------------------|
| S#0 | VDP(8) | interrupt information |
| S#1 | VDP(-1) | interrupt information |
| S#2 | VDP(-2) | DP command control information/etc. |
| S#3 | VDP(-3) | coordinate detected (LOW) |
| S#4 | VDP(-4) | coordinate detected (HIGH) |
| S#5 | VDP(-5) | coordinate detected (LOW) |
| S#6 | VDP(-6) | coordinate detected (HIGH) |
| S#7 | VDP(-7) | data obtained by VDP command |
| S#8 | VDP(-8) | X-coordinate obtained by search command (LOW) |
| S#9 | VDP(-9) | X-coordinate obtained by search command (HIGH) |
-----------------------------------------------------------------------------
(3) Colour palette register group (P#0 to P#15)
These registers are used to set the colour palette. Registers are expressed
using the notation P#n where 'n' is the palette number which represents one
of 512 colours. Each palette register has 9 bits allowing three bits to be
used for each RGB colour (red, green, and blue).
1.2 VRAM
MSX-VIDEO can be connected with 128K bytes VRAM (Video RAM) and 64K bytes
expanded RAM. MSX-VIDEO has a 17-bit counter for accessing this 128K bytes
address area. Note that this memory is controlled by MSX-VIDEO and cannot be
directly accessed by the CPU.
Expanded RAM memory cannot be directly displayed to the screen as can that of
VRAM. However, it can be manipulated the same as VRAM when using the video
processor commands. This large work area is very useful when processing
screen data. Note that the MSX standard does not include instructions
regarding expanded RAM, so taking advantage of this in program design could
result in compatibility problems with other MSX machines.
Figure 4.1 VRAM and expanded RAM
Address counter
----------------- 00000H -----------------
| | | | |
| | | | |
| | | | |
| | | | |
|---------------| 0FFFFH -----------------
| | | RAM
| | | (data use)
| | |
| | |
----------------- 1FFFFH
VRAM
(screen use)
1.3 I/O ports
MSX-VIDEO has four I/O ports that send data back and forth the CPU. The
functions of these ports are listed in Table 4.3. The ports are accessed by
the CPU through its I/O addresses in the table below, addresses expressed as
n, n' are stored at address locations 6 and 7 in MAIN-ROM. Although n = n' =
98H normally, this can be different on some machines, so port addresses
should be obtained from these addresses for reliable results.
It is generally recommended that BIOS be used for I/O operations for purposes
of compatibility. However, the screen display often requires high speed, so
these I/O ports are capable of accessing MSX-VIDEO directly.
Table 4.3 MSX-VIDEO ports
----------------------------------------------------------------------
| Port | Address | Function |
|-----------------+---------+----------------------------------------|
| port #0 (READ) | n | read data from VRAM |
| port #0 (WRITE) | n' | write data to VRAM |
| port #1 (READ) | n + 1 | read status register |
| port #1 (WRITE) | n'+ 1 | write to control register |
| port #2 (WRITE) | n'+ 2 | write to palette register |
| port #3 (WRITE) | n'+ 3 | write to indirectly specified register |
----------------------------------------------------------------------
Note: The value of n should be obtained by referring to address 6 in MAIN-ROM
The value of n'should be obtained by referring to address 7 in MAIN-ROM
2. ACCESS TO MSX-VIDEO
MSX-VIDEO can be accessed directly through the I/O ports without going
through BIOS. This section describes how to do this.
2.1 Access to Registers
2.1.1 Writing data to control registers
The control registers are write-only registers. As described above, the
partial contents of control registers (R#0 to R#23) can be obtained by
referring to VDP(n) from BASIC. This only reads the value which has been
written in the work area of RAM (F3DFH to F3E6H, FFE7H to FFF6H) used for
writing to registers.
There are three ways, described below, to write data to control registers.
Since MSX accesses MSX-VIDEO inside the timer interrupt routine to examine
the occurrence of sprite conflicts, note that access procedure will not
inhibiting the interrupt when the registers are accessed in the proper way as
described below.
(1) Direct access
The first way is to directly specify the data and where it is to be written
to. Figure 4.2 illustrates the procedure. The data is first written to port#1
and then the destination register number is written to port#1 using the five
least significant bits. The most significant bit is set to 1 and the second
bit is set to 0. Thus the value would be 10XXXXXB in binary notation where
XXXXX is the destination register number.
Figure 4.2 Direct access to R#n
MSB 7 6 5 4 3 2 1 0 LSB
-----------------------------------------
Port #1 | : : : Data : : : | 1.Puts data to port #1.
-----------------------------------------
-----------------------------------------
Port #1 | 1 | 0 | R5 | R4 | R3 | R2 | R1 | R0 | 2. Then puts register
----------------------------------------- number with two
| | | high bits set to
+---------+-----------------------------+ "10" to port #1.
fixed register number (0 to 46)
at "10"
Port#1 is also used to set VRAM addresses and is described in section 2.2.
The most significant bit of the second byte sent to this port is the
address/register flag and determines the operation to take place. When the
bit is set to "1", writing data to a control register as described here will
take place.
(2) Indirect Access (non-autoincrement mode)
The second way is to write data to the register specified as the objective
register (R#17 contains the objective pointer). To begin with, store the
register number to be accessed in R#17 by direct access. The most significant
bit is set to 1 and the second bit to 0. Thus the value would be 10XXXXXB in
binary notation where XXXXX is the objective register number. After this is
done, data can be written to the objective register by sending data to
port#3. This method is used for sending data to the same register
continuously. An example would be for the execution of VDP commands.
Figure 4.3 Indirect access to R#n (non-autoincrement mode)
First byte
MSB 7 6 5 4 3 2 1 0 LSB
-----------------------------------------
R#17 | 1 | 0 | R5 | R4 | R3 | R2 | R1 | R0 | 1.Set register number n
----------------------------------------- to R#17, with two high
| | | order bits set to "10".
+---------+-----------------------------+
fixed n (0 to 46)
at "10"
-----------------------------------------
Port#3 | : : : Data : : : | 2.Send data to port#3.
----------------------------------------- The data is stored
in register R#n.
Following bytes
-----------------------------------------
Port#3 | : : : Data : : : | 3.After these are done,
----------------------------------------- data can be written to
register R#n only by
sending to port #3.
(3) Indirect Access (autoincrement mode)
The third way is to write date to the register indicated by R#17. R#17 is
incremented each time data is sent to port#3. To begin with, store the
beginning register number to be accessed in R#17 by direct access. The two
most significant bits are set to 0. Thus the value would be 00XXXXXB in
binary notation where XXXXX is the beginning register number.
Since this method allows writing data to continuous control registers
effectively, it is useful when several continuous registers are to be changed
at once. One example would be when the screen mode is changed.
Figure 4.4 Indirect access to R#n (autoincrement mode)
MSB 7 6 5 4 3 2 1 0 LSB
-----------------------------------------
R#17 | 0 | 0 | R5 | R4 | R3 | R2 | R1 | R0 | 1.Set register number n
----------------------------------------- to R#17, with two high
| | | order bits set to "00".
+---------+-----------------------------+
fixed n (0 to 46)
at "00"
-----------------------------------------
Port#3 | : : : Data : : : | 2.Send data to port#3.
----------------------------------------- The data is stored
in register R#n.
-----------------------------------------
Port#3 | : : : Data : : : | 3.Data sent to next
----------------------------------------- port#3 is stored to
register R#(n+1).
. .
. .
. .
2.1.2 Setting a palette
To set data in the MSX-VIDEO palette registers (P#0 to P#15), specify the
palette register number in the four lowest significant bits of R#16 (color
palette pointer), and then send the data to port#2. Since palette registers
have a length of 9 bits, data must be sent twice; red brightness and blue
brightness first, then green brightness. Brightness is specified in the lower
three bits of a four bit segment. Refer to Figure 4.5 for details.
After data is sent to port#2 twice, R#16 is automatically incremented. This
feature makes it easy to initialize all the palettes.
Figure 4.5 Setting a colour palette register
MSB 7 6 5 4 3 2 1 0 LSB
-----------------------------------------
R#16 | 0 | 0 | 0 | 0 | R3 | R2 | R1 | R0 | 1.Set palette number n
----------------------------------------- to R#16, with four
| | | high order bits set
+---------------------------------------+ to "0000".
fixed at "0000" n (0 to 15)
-----------------------------------------
Port#2 | | Red bright. | | Blue bright. | 2.Send red and blue
----------------------------------------- brightness to port#2.
| | | |
+--------------+ +--------------+
0 to 7 0 to 7
-----------------------------------------
Port#2 | | | | | | Green bright.| 2.Send green brightness
----------------------------------------- to port#2. (*)
| |
+--------------+
0 to 7
(*) Since R#16 is incremented at this point, setting next palette can be done
by sending data to port#2 continuously.
2.1.3 Reading status registers
Status registers are read-only registers. Their contents can be read from
port#1 by setting the status register number in the least significant four
bits of R#15 (status register pointer) as shown in Figure 4.6. The four most
significant bits are set to 0. Thus the value would be 0000XXXXB in binary
notation where XXXX is the status register number. Interrupts should be
inhibited before the status register is accessed. After the desired task is
completed, R#15 should be set to 0 and the interrupts released.
Figure 4.6 Acessing status registers
MSB 7 6 5 4 3 2 1 0 LSB
-----------------------------------------
R#15 | 0 | 0 | 0 | 0 | R3 | R2 | R1 | R0 | 1.Set register number n
----------------------------------------- to R#15, with four
| | | high order bits set
+-------------------+-------------------+ to "0000".
fixed at "0000" n (0 to 9)
-----------------------------------------
Port#1 | : : : Data : : : | 2.Read data from port#1.
-----------------------------------------
2.2 VRAM Access From the CPU
When a VRAM address is to be accessed from the CPU, follow the procedure
described below.
(1) Bank switching
The first 64K bytes of VRAM (00000H to 0FFFFH) and the 64K bytes of expanded
RAM both reside at the same address space as viewed by MSX-VIDEO. Bank
switching is used so that they can both be online at the same time. Since
MSX2 does not to use expanded VRAM, always select the VRAM bank. Bank
switching is controlled by bit 6 of R#45.
Figure 4.7 VRAM/expanded RAM bank switching
MSB 7 6 5 4 3 2 1 0 LSB
-----------------------------------------
R#45 | . | X | . | . | . | . | . | . | When bit 6 of R#45 is "0"
----------------------------------------- VRAM is selected; when it
| 0:VRAM is 1, expanded RAM is
+--> selected.
1:Expanded RAM
(2) Setting the VRAM page (three high order bits)
The 17-bit address for accessing the 128K bytes of VRAM is set in the address
counter (A16 to A0). R#14 contains the three high order bits (A16 to A14). So
this register can be viewed as switching between eight 16K byte pages of
VRAM.
Figure 4.8 Setting the VRAM page (3 high order bits)
MSB 7 6 5 4 3 2 1 0 LSB
-----------------------------------------
R#14 | 0 | 0 | 0 | 0 | 0 | A16| A15| A14| Set 3 high order bits of
----------------------------------------- address counter in the
field from bit 2 to bit 0
on R#14.
(3) Setting the VRAM address (14 low order bits)
The 14 low order bits of the address should be sent to port#1 in two bytes.
Figure 4.9 shows the details. Make sure that the most significant bit of the
second byte sent is set to 0. This sets the address/register flag to address
mode. The second most significant bit sets the read/write flag. 1 signifies
writing to VRAM and 0 signifies reading from VRAM.
Figure 4.9 Setting 14 low order bits
MSB 7 6 5 4 3 2 1 0 LSB
-----------------------------------------
Port#1 | A7 | A6 | A5 | A4 | A3 | A2 | A1 | A0 | 1.Send A7 to A0 to
----------------------------------------- port#1.
-----------------------------------------
Port#1 | 0 | | A13| A12| A11| A10| A9 | A8 | 2.Send A13 to A8 to
----------------------------------------- port#1, continuously.
| | 0:reading VRAM Bit 7 must be set to
"0" +--> "0". Bit 6 determines
1:writing VRAM reading/writing data.
(4) Reading/writing VRAM
After setting the value in the address counter, read or write data through
port#0. The read/write flag is set the same time as A13 to A8 of the address
counter, as described above.
The address counter is automatically incremented each time a byte of data is
read or written to port #0. This feature allows for easy access of continuous
memory in VRAM.
Figure 4.10 Access to VRAM through port#0
MSB 7 6 5 4 3 2 1 0 LSB
-----------------------------------------
Port#0 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | Access to VRAM is done
----------------------------------------- through port#0. Address
counter is automatically
incremented.
3. SCREEN MODES OF THE MSX2
The MSX2 has ten different modes as shown in Table 4.4. Six screen modes
marked with "*" in the table below (TEXT 2 and GRAPHIC 3 to GRAPHIC 7) have
been introduced for the MSX2. The other modes have been improved due to the
change from TMS9918A to MSX-VIDEO. Fetures of these ten screen modes and how
to use them are described below.
Table 4.4 Screen modes listing of MSX2
--------------------------------------------------------------------------
| Mode Name | SCREEN mode | Description |
|-------------+-------------+--------------------------------------------|
| TEXT 1 | SCREEN 0 | 40 characters per line of text, one colour |
| | (width=40) | for each character |
|-------------+-------------+--------------------------------------------|
| * TEXT 2 | SCREEN 0 | 80 characters per line of text, |
| | (width=80) | character blinkable selection |
|-------------+-------------+--------------------------------------------|
| MULTI-COLOR | SCREEN 3 | pseudo-graphic, one character |
| | | divided into four block |
|-------------+-------------+--------------------------------------------|
| GRAPHIC 1 | SCREEN 1 | 32 characters per one line of |
| | | text, the COLOURed character available |
|-------------+-------------+--------------------------------------------|
| GRAPHIC 2 | SCREEN 2 | 256 x 192, the colour is |
| | | specififed for each 8 dots |
|-------------+-------------+--------------------------------------------|
| * GRAPHIC 3 | SCREEN 4 | GRAPHIC 2 which can use sprite |
| | | mode 2 |
|-------------+-------------+--------------------------------------------|
| * GRAPHIC 4 | SCREEN 5 | 256 x 212; 16 colours are |
| | | available for each dot |
|-------------+-------------+--------------------------------------------|
| * GRAPHIC 5 | SCREEN 6 | 512 x 212; 4 colours are |
| | | available for each dot |
|-------------+-------------+--------------------------------------------|
| * GRAPHIC 6 | SCREEN 7 | 512 x 212; 16 colours are |
| | | available for each dot |
|-------------+-------------+--------------------------------------------|
| * GRAPHIC 7 | SCREEN 8 | 256 x 212; 256 colours are |
| | | available for each dot |
--------------------------------------------------------------------------
3.1 TEXT 1 Mode
TEXT 1 screen mode has the following features:
----------------------------------------------------------------------------
| |
| screen: 40 (horizontal) x 24 (vertical) |
| background/character colours can be selected from |
| 512 colours |
| character: 256 characters available |
| character size: 6 (horizontal) x 8 (vertical) |
| memory requirements: for character font ... 2048 bytes |
| (8 bytes x 256 characters) |
| for display ........... 960 bytes |
| (40 characters x 24 lines) |
| BASIC: compatible with SCREEN 0 (WIDTH 40) |
| |
----------------------------------------------------------------------------
3.1.1 Setting TEXT 1 mode
MSX-VIDEO screen modes are set by using 5 bits of R#0 and R#1. Figure 4.11
shows the details. The 3-bit mask in R#0 is 000B and the 2-bit mask in R#1 is
10B when using the TEXT 1 mode.
Figure 4.11 Setting TEXT1 mode
MSB 7 6 5 4 3 2 1 0 LSB
-----------------------------------------
R#0 | . | . | . | . | 0 | 0 | 0 | . |
-----------------------------------------
-----------------------------------------
R#1 | . | . | . | 1 | 0 | . | . | . |
-----------------------------------------
3.1.2 Screen structure of TEXT 1 mode
* Pattern generator table
The area in which character fonts are stored is called the pattern generator
table. This table is located in VRAM, and, although the font is defined by
using 8 bytes for each character from the top of the table, the 2 low order
bits of each byte representing the right two columns are not displayed on the
screen. Thus, the size of one character is 6 x 8 pixels. Each character font
set contains 256 different characters numbered from 0 to 255. Use this code
to specify which character should be displayed on the screen.
Specify the location of the pattern generator table in R#4. Note that the 6
high order bits of the address (A16 to A11) are specified and the 11 low
order bits of the address (A10 to A0) are always 0 ("00000000000B"). So the
address in which the pattern generator table can be set always begins at a
multiple of 2K bytes from 00000H. This address can be found using the system
variable BASE(2) from BASIC. Figure 4.12 shows the structure of the pattern
generator table.
Figure 4.12 Structure of the pattern generator table
MSB 7 6 5 4 3 2 1 0 LSB
-----------------------------------------
R#4 | 0 | 0 | A16| A15| A14| A13| A12| A11| ---+
----------------------------------------- |
|
+--------------------------------------------+
|
| MSB 7 6 5 4 3 2 1 0 LSB
| ----------------------------------------- --+
+---> 0 | | | # | | | | | | |
|----+----+----+----+----+----+----+----| |
1 | | # | | # | | | | | |
|----+----+----+----+----+----+----+----| |
2 | # | | | | # | | | | |
|----+----+----+----+----+----+----+----| |
3 | # | | | | # | | | | | Pattern #0
|----+----+----+----+----+----+----+----| |
4 | # | # | # | # | # | | | | |
|----+----+----+----+----+----+----+----| |
5 | # | | | | # | | | | |
|----+----+----+----+----+----+----+----| | ------
6 | # | | | | # | | | | | | | = 0
|----+----+----+----+----+----+----+----| | ------
7 | | | | | | | | | |
|----+----+----+----+----+----+----+----| --+
8 | # | # | # | # | | | | | |
|----+----+----+----+----+----+----+----| | ------
9 | # | | | | # | | | | | | # | = 1
|----+----+----+----+----+----+----+----| | ------
10 | # | | | | # | | | | |
|----+----+----+----+----+----+----+----| |
11 | # | # | # | # | | | | | |
|----+----+----+----+----+----+----+----| | Pattern #1
12 | # | | | | # | | | | |
|----+----+----+----+----+----+----+----| |
13 | # | | | | # | | | | |
|----+----+----+----+----+----+----+----| |
14 | # | # | # | # | | | | | |
|----+----+----+----+----+----+----+----| |
15 | | | | | | | | | |
----------------------------------------- --+
. .
. .
. .
----------------------------------------- --+
2040 | # | | # | | # | | | | |
|----+----+----+----+----+----+----+----| |
2041 | | # | | # | | # | | | |
|----+----+----+----+----+----+----+----| |
2042 | # | | # | | # | | | | |
|----+----+----+----+----+----+----+----| |
2043 | | # | | # | | # | | | |
|----+----+----+----+----+----+----+----| | Pattern #255
2044 | # | | # | | # | | | | |
|----+----+----+----+----+----+----+----| |
2045 | | # | | # | | # | | | |
|----+----+----+----+----+----+----+----| |
2046 | # | | # | | # | | | | |
|----+----+----+----+----+----+----+----| |
2047 | | # | | # | | # | | | |
----------------------------------------- --+
| |
+---------+
2 low order bits are not displayed
Pattern generator table
* Pattern name table
The pattern name table stores the characters to be displayed at each position
on the screen. One byte of memory is used for each character to be displayed.
Figure 4.13 shows the correspondence between memory location and screen
location.
Specify the location of the pattern generator table in R#2. Note that the 7
high order bits of the address (A16 to A10) are specified and that the 10 low
order bits of the address (A9 to A0) are always 0 ("0000000000B"). So the
address in which the name table can be set always begins at a multiple of 1K
bytes from 00000H. This address can be found by using the system variable
BASE(0) from BASIC. Figure 4.13 shows the structure of the pattern generator
table.
Figure 4.13 Structure of TEXT1 pattern name table
MSB 7 6 5 4 3 2 1 0 LSB
-----------------------------------------
R#2 | 0 | A16| A15| A14| A13| A12| A11| A10| ---+
----------------------------------------- |
|
+--------------------------------------------+
|
| | |
| -----------
+---> 0 | (0,0) | 0 1 2 3 39 X
|---------| ---------------------- -------
1 | (1,0) | 0 | 0 | 1 | 2 | 3 | . . . | 39 |
|---------| |----+----+----+----+- -+----|
2 | (2,0) | 1 | 40 | 41 | 42 | 43 | . . . | 79 |
|---------| |----+----+----+----+- -+----|
. | . | | | | | | . . . | |
. . . . .
. . . . .
| | . . .
|---------| | | | | |
39 | (39,0) | ------------ -------
|---------| 22 | 880| 881| | 919|
40 | (0,1) | |----+----+- -+----|
|---------| 23 | 920| 921| | 959|
. | . | ------------ . . . . .-------
. . Y
. .
| | Screen correspondence table
|---------|
959 | (39,23) |
|---------|
| |
Pattern Name Table
3.1.3 Specifying screen colour
The screen colour is specified by R#7. The background colour is the palette
specified by the 4 low-order bits of R#7; the 4 high-order bits specify the
foreground colour (see Figure 4.14). A "0" in the font pattern is displayed
in the background colour and a "1" is displayed in the foreground colour.
Note that in TEXT 1 the border colour of the screen cannot be set and it is
the same as the background colour.
Figure 4.14 Colour specification in TEXT 1
MSB 7 6 5 4 3 2 1 0 LSB
-----------------------------------------
R#7 | : : : | : : : |
-----------------------------------------
| | |
+-------------------+-------------------+
Specifies the colour of "1" Specifies the colour of "0" of the pattern
of the pattern (0 to 15) and of the background colour (0 to 15)
3.2 TEXT 2 Mode
The screen mode TEXT 2 has the following features:
----------------------------------------------------------------------------
| |
| screen: 80 (horizontal) x 24 (vertical) or 26.5 (vertical) |
| background colour/character colour can be selected |
| from 512 colours |
| character: 256 characters available |
| character size: 6 (horizontal) x 8 (vertical) |
| each character blinkable |
| memory requirements: 24 lines |
| for character font ... 2048 bytes |
| (8 bytes x 256 characters) |
| for display .......... 1920 bytes |
| (80 characters x 24 lines) |
| for blinking ......... 240 bytes (= 1920 bits) |
| 26.5 lines |
| for character font ... 2048 bytes |
| (8 bytes x 256 characters) |
| for display .......... 2160 bytes |
| (80 characters x 27 lines) |
| for blinking ......... 270 bytes (= 2160 bits) |
| BASIC: compatible with SCREEN 0 (WIDTH 80) |
| |
----------------------------------------------------------------------------
3.2.1 Setting TEXT 2 mode
Set TEXT2 mode as shown in Figure 4.15.
Figure 4.15 Setting TEXT2 mode
MSB 7 6 5 4 3 2 1 0 LSB
-----------------------------------------
R#0 | . | . | . | . | 0 | 1 | 0 | . |
-----------------------------------------
-----------------------------------------
R#1 | . | . | . | 1 | 0 | . | . | . |
-----------------------------------------
* Setting number of lines (24 lines/26.5 lines)
TEXT2 mode can switch the screen to 24 lines or 26.5 lines depending on the
value of bit 7 in R#9. Note that, when the screen is set to 26.5 lines, only
the upper half of the characters at the bottom of the screen are displayed.
This mode is not supported by BASIC.
Figure 4.16 Switching number of lines
MSB 7 6 5 4 3 2 1 0 LSB
-----------------------------------------
R#9 | LN | . | . | . | . | . | . | . |
-----------------------------------------
| 0:24 lines
+-->
1:26.5 lines
3.2.2 Screen structure of TEXT 2
* Pattern generator table
The pattern generator table has the same structure and function as the one of
TEXT1. See the descriptions for TEXT1.
* Pattern name table
Since the number of characters to be displayed in the screen has been
increased to 2160 (80 x 27) characters maximum, the maximum area occupied by
the pattern name table is 2160 bytes.
Specify the location of the pattern name table in R#2. The 5 high order bits
of the address (A16 to A12) are specified and the 12 low order bits of the
address (A11 to A0) are always 0 ("000000000000B"). So the address in which
the pattern name table can be set always begins at a multiple of 4K bytes
from 00000H.
Figure 4.17 Structure of TEXT2 pattern name table
MSB 7 6 5 4 3 2 1 0 LSB
-----------------------------------------
R#2 | 0 | A16| A15| A14| A13| A12| 1 | 1 | ---+
----------------------------------------- |
|
+--------------------------------------------+
|
| | |
| -----------
+---> 0 | (0,0) | 0 1 2 3 79 X
|---------| ---------------------- -------
1 | (1,0) | 0 | 0 | 1 | 2 | 3 | . . . | 79 |
|---------| |----+----+----+----+- -+----|
2 | (2,0) | 1 | 80 | 81 | 82 | 83 | . . . | 159|
|---------| |----+----+----+----+- -+----|
. | . | | | | | | . . . | |
. . . . .
. . . . .
| | . . .
|---------| | | | | |
79 | (79,0) | |----+----+- -+----|
|---------| 25 |2000|2001| |2079|
80 | (0,1) | |----+----+- -+----|
|---------| 26 |2080|2081| |2159|
. | . | ------------ . . . . .-------
. . Y
. .
| | Screen correspondence table
|---------|
2159 | (79,26) |
|---------|
| |
Pattern Name Table
* Blink table
In TEXT2 mode, it is possible to set the blink attribute for each character.
The blink table stores the information of the screen location of the
characters blinked. One bit of the blink table corresponds to one character
on the screen (that is, on the pattern name table). When the bit is set to
"1" blinking is enabled for the corresponding character; when the bit is "0"
blinking is disabled.
Figure 4.18 Blink table structure of TEXT2
MSB 7 6 5 4 3 2 1 0 LSB
----------------------------------------- --+
R#3 | A13| A12| A11| A10| A9 | 1 | 1 | 1 | |
----------------------------------------- |
+--+
----------------------------------------- | |
R#10 | 0 | 0 | 0 | 0 | 0 | A16| A15| A14| | |
----------------------------------------- --+ |
|
+------------------------------------------------------+
|
| MSB 7 6 5 4 3 2 1 0 LSB
| -----------------------------------------------------------------
+---> 0 | (0,0) | (1,0) | (2,0) | (3,0) | (4,0) | (5,0) | (6,0) | (7,0) |
|-------+-------+-------+-------+-------+-------+-------+-------|
1 | (8,0) | (9,0) |(10,0) |(11,0) |(12,0) |(13,0) |(14,0) |(15,0) |
|-------+-------+-------+-------+-------+-------+-------+-------|
| . | . | . | . | . | . | . | . |
. . . . . . . .
. . . . . . . .
| | | | | | | | |
|-------+-------+-------+-------+-------+-------+-------+-------|
269 |(72,26)|(73,26)|(74,26)|(75,26)|(76,26)|(77,26)|(78,26)|(79,26)|
-----------------------------------------------------------------
Blink table
Specify the starting address of the blink table by setting the 8 high order
bits (A16 to A9) in R#3 and R#10. The location of the blink table is set by
writing the 8 high order bits of the address (A16 to A9) in R#3 and R#10. The
9 low order bits of the address (A8 to A0) are always 0 ("000000000B"). So
the address in which the blink table can be set always begins at a multiple
of 512 bytes from 00000H.
3.2.3 Screen colour and character blink specification
The foreground colour is specified by the 4 high order bits of R#7 and the
background colour by the 4 low order bits of R#7. Characters with a blink
attribute of 1 defined by the blink table alternate between the blink colour
and the colour specified in R#12.
Figure 4.19 Setting screen colour and blink colour
MSB 7 6 5 4 3 2 1 0 LSB
-----------------------------------------
R#7 | : : : | : : : | <-- original character
----------------------------------------- colour
| | |
+-------------------+-------------------+
Specifies the colour Specifies the colour of "0" of the pattern
of "1" of the pattern and of the background colour
-----------------------------------------
R#12 | : : : | : : : | <-- character colour
----------------------------------------- when blinking
| | |
+-------------------+-------------------+
Specifies the colour of "1" Specifies the colour of "0" of
of the pattern when blinking the pattern when blinking
The blinking rate is set in R#13. The 4 high order bits define the display
time in the original colour, and the 4 low order bits define the display time
in the blink colour. The period of time is defined in units of 1/6 seconds.
Figure 4.20 Setting blink rate