RISCV32 Physical memory mapping ?

[Navko]

Hi
Am trying to figure out the Physical memory mapping for the RISCV32 simulation
Where can I find those details?

[pavelkryukov]

We don't model virtual memory so far, memory accesses are performed by physical addresses.

[Navko]

Thanks for the reply
Does MIPT-V simulate any specific CPU model and address space? RAM , I/O
Am new here and looking for how 2^32 address space and Memory mapping is done.
found some base defines in https://github.com/MIPT-ILab/riscv-opcodes/blob/866852e37738147979069b322fac8eb6227cbb54/encoding.h
Is it possible to explain how it reflects?

[pavelkryukov]

No, it does not simulate any specific CPU. The main goal is to provide a generic performance model.
These defines are provided by RISC-V community along with opcodes. We don't use them at the moment.

[pavelkryukov]

@Navko Could you please give an insight how you would like to use the simulator?

[Navko]

Am trying to add Axi bus for memory access simulate for cycle accurate

[pavelkryukov]

Sorry, I'm afraid we won't model that for a long time. Our primary goal is precision model of CPU uarch internals, since they bring the most of performance impact. In that setting, buses are used quite rarely and/or in shadow of generic computations.