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rshim.c
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rshim.c
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// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only
/*
* rshim.c - BlueField SoC host-side driver for RShim
*
* Copyright (c) 2020 NVIDIA Corporation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kref.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/poll.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/version.h>
#include <linux/uaccess.h>
#include <linux/ioctl.h>
#include <linux/termios.h>
#include <linux/workqueue.h>
#include <linux/sched.h>
#include <asm/termbits.h>
#include <linux/circ_buf.h>
#include <linux/delay.h>
#include <linux/virtio_ids.h>
#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0)
#include <linux/sched/signal.h>
#endif
#include "rshim.h"
/* Maximum number of devices controlled by this driver. */
int rshim_nr_devs = 64;
module_param(rshim_nr_devs, int, 0444);
MODULE_PARM_DESC(rshim_nr_devs, "Maximum number of supported devices");
static char *backend_driver = "";
module_param(backend_driver, charp, 0444);
MODULE_PARM_DESC(backend_driver, "Rshim backend driver to use");
static int rshim_keepalive_period = 300;
module_param(rshim_keepalive_period, int, 0644);
MODULE_PARM_DESC(rshim_keepalive_period, "Keepalive period in milliseconds");
static int rshim_sw_reset_skip;
module_param(rshim_sw_reset_skip, int, 0644);
MODULE_PARM_DESC(rshim_sw_reset_skip, "Skip SW_RESET during booting");
int rshim_boot_timeout = 300;
module_param(rshim_boot_timeout, int, 0644);
MODULE_PARM_DESC(rshim_boot_timeout, "Boot timeout in seconds");
EXPORT_SYMBOL(rshim_boot_timeout);
#define RSH_KEEPALIVE_MAGIC_NUM 0x5089836482ULL
/* Circular buffer macros. */
#define read_empty(bd, chan) \
(CIRC_CNT((bd)->read_fifo[chan].head, \
(bd)->read_fifo[chan].tail, READ_FIFO_SIZE) == 0)
#define read_full(bd, chan) \
(CIRC_SPACE((bd)->read_fifo[chan].head, \
(bd)->read_fifo[chan].tail, READ_FIFO_SIZE) == 0)
#define read_space(bd, chan) \
CIRC_SPACE((bd)->read_fifo[chan].head, \
(bd)->read_fifo[chan].tail, READ_FIFO_SIZE)
#define read_cnt(bd, chan) \
CIRC_CNT((bd)->read_fifo[chan].head, \
(bd)->read_fifo[chan].tail, READ_FIFO_SIZE)
#define read_cnt_to_end(bd, chan) \
CIRC_CNT_TO_END((bd)->read_fifo[chan].head, \
(bd)->read_fifo[chan].tail, READ_FIFO_SIZE)
#define read_data_ptr(bd, chan) \
((bd)->read_fifo[chan].data + \
((bd)->read_fifo[chan].tail & (READ_FIFO_SIZE - 1)))
#define read_consume_bytes(bd, chan, nbytes) \
((bd)->read_fifo[chan].tail = \
((bd)->read_fifo[chan].tail + (nbytes)) & \
(READ_FIFO_SIZE - 1))
#define read_space_to_end(bd, chan) \
CIRC_SPACE_TO_END((bd)->read_fifo[chan].head, \
(bd)->read_fifo[chan].tail, READ_FIFO_SIZE)
#define read_space_offset(bd, chan) \
((bd)->read_fifo[chan].head & (READ_FIFO_SIZE - 1))
#define read_space_ptr(bd, chan) \
((bd)->read_fifo[chan].data + read_space_offset(bd, (chan)))
#define read_add_bytes(bd, chan, nbytes) \
((bd)->read_fifo[chan].head = \
((bd)->read_fifo[chan].head + (nbytes)) & \
(READ_FIFO_SIZE - 1))
#define read_reset(bd, chan) \
((bd)->read_fifo[chan].head = (bd)->read_fifo[chan].tail = 0)
#define write_empty(bd, chan) \
(CIRC_CNT((bd)->write_fifo[chan].head, \
(bd)->write_fifo[chan].tail, WRITE_FIFO_SIZE) == 0)
#define write_full(bd, chan) \
(CIRC_SPACE((bd)->write_fifo[chan].head, \
(bd)->write_fifo[chan].tail, WRITE_FIFO_SIZE) == 0)
#define write_space(bd, chan) \
CIRC_SPACE((bd)->write_fifo[chan].head, \
(bd)->write_fifo[chan].tail, WRITE_FIFO_SIZE)
#define write_cnt(bd, chan) \
CIRC_CNT((bd)->write_fifo[chan].head, \
(bd)->write_fifo[chan].tail, WRITE_FIFO_SIZE)
#define write_cnt_to_end(bd, chan) \
CIRC_CNT_TO_END((bd)->write_fifo[chan].head, \
(bd)->write_fifo[chan].tail, WRITE_FIFO_SIZE)
#define write_data_offset(bd, chan) \
((bd)->write_fifo[chan].tail & (WRITE_FIFO_SIZE - 1))
#define write_data_ptr(bd, chan) \
((bd)->write_fifo[chan].data + write_data_offset(bd, (chan)))
#define write_consume_bytes(bd, chan, nbytes) \
((bd)->write_fifo[chan].tail = \
((bd)->write_fifo[chan].tail + (nbytes)) & \
(WRITE_FIFO_SIZE - 1))
#define write_space_to_end(bd, chan) \
CIRC_SPACE_TO_END((bd)->write_fifo[chan].head, \
(bd)->write_fifo[chan].tail, WRITE_FIFO_SIZE)
#define write_space_ptr(bd, chan) \
((bd)->write_fifo[chan].data + \
((bd)->write_fifo[chan].head & (WRITE_FIFO_SIZE - 1)))
#define write_add_bytes(bd, chan, nbytes) \
((bd)->write_fifo[chan].head = \
((bd)->write_fifo[chan].head + (nbytes)) & \
(WRITE_FIFO_SIZE - 1))
#define write_reset(bd, chan) \
((bd)->write_fifo[chan].head = (bd)->write_fifo[chan].tail = 0)
/* Arguments to an fsync entry point. */
#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35)
#define FSYNC_ARGS struct file *file, struct dentry *dentry, int datasync
#define FSYNC_CALL file, dentry, datasync
#elif LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0)
#define FSYNC_ARGS struct file *file, int datasync
#define FSYNC_CALL file, datasync
#else
#define FSYNC_ARGS struct file *file, loff_t start, loff_t end, int datasync
#define FSYNC_CALL file, start, end, datasync
#endif
/*
* Tile-to-host bits (UART 0 scratchpad).
*/
/*
* Output write pointer mask. Note that this is the maximum size; the
* write pointer may be smaller if requested by the host.
*/
#define CONS_RSHIM_T2H_OUT_WPTR_MASK 0x3FF
/* Tile is done mask. */
#define CONS_RSHIM_T2H_DONE_MASK 0x400
/*
* Input read pointer mask. Note that this is the maximum size; the read
* pointer may be smaller if requested by the host.
*/
#define CONS_RSHIM_T2H_IN_RPTR_MASK 0x1FF800
/* Input read pointer shift. */
#define CONS_RSHIM_T2H_IN_RPTR_SHIFT 11
/* Tile is done mask. */
#define CONS_RSHIM_T2H_DONE_MASK 0x400
/* Number of words to send as sync-data (calculated by packet MTU). */
#define TMFIFO_MAX_SYNC_WORDS (1536 / 8)
/* Terminal characteristics for newly created consoles. */
#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 20)
static struct termios init_console_termios = {
#else
static struct ktermios init_console_termios = {
#endif
.c_iflag = INLCR | ICRNL,
.c_oflag = OPOST | ONLCR,
.c_cflag = B115200 | HUPCL | CLOCAL | CREAD | CS8,
.c_lflag = ISIG | ICANON | ECHOE | ECHOK | ECHOCTL | ECHOKE | IEXTEN,
.c_line = 0,
.c_cc = INIT_C_CC,
};
/* Completion initialization. */
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 13, 0)
#define reinit_completion(x) INIT_COMPLETION(*(x))
#endif
static DEFINE_MUTEX(rshim_mutex);
/*
* Array of all of the rshim devices. The high bits of our minor number
* index into this table to find the relevant device.
*/
struct rshim_backend **rshim_devs;
/*
* Work queue. Right now we have one for the whole driver; we might
* eventually decide that we need one per device, but we'll see.
*/
struct workqueue_struct *rshim_wq;
EXPORT_SYMBOL(rshim_wq);
/*
* Array of pointers to kmalloc'ed strings, holding the path name for
* all of the devices we've seen. If rshim_devs[i] is non-NULL, then
* rshim_dev_names[i] is its path name. If rshim_devs[i] is NULL, then
* rshim_dev_names[i] is the name that was last used for that device.
* When we see a new device, we look it up in this table; this allows us to
* use the same device index we did last time we saw the device. The
* strings within the array persist until the driver is unloaded.
*/
char **rshim_dev_names;
/* Name of the sub-device types. */
char *rshim_dev_minor_names[RSH_DEV_TYPES] = {
[RSH_DEV_TYPE_RSHIM] = "rshim",
[RSH_DEV_TYPE_BOOT] = "boot",
[RSH_DEV_TYPE_CONSOLE] = "console",
[RSH_DEV_TYPE_NET] = "net",
[RSH_DEV_TYPE_MISC] = "misc",
};
/* dev_t base index. */
static dev_t rshim_dev_base;
/* Class structure for our device class. */
static struct class *rshim_class;
/* Registered services. */
static struct rshim_service *rshim_svc[RSH_SVC_MAX];
/* FIFO reset. */
static void rshim_fifo_reset(struct rshim_backend *bd);
/* Display level of the misc device file. */
static int rshim_misc_level;
/* Global lock / unlock. */
void rshim_lock(void)
{
mutex_lock(&rshim_mutex);
}
EXPORT_SYMBOL(rshim_lock);
void rshim_unlock(void)
{
mutex_unlock(&rshim_mutex);
}
EXPORT_SYMBOL(rshim_unlock);
/*
* Read some bytes from RShim.
*
* The provided buffer size should be multiple of 8 bytes. If not, the
* leftover bytes (which presumably were sent as NUL bytes by the sender)
* will be discarded.
*/
static ssize_t rshim_read_default(struct rshim_backend *bd, int devtype,
char *buf, size_t count)
{
int retval, total = 0, avail = 0;
u64 word;
/* Read is only supported for RShim TMFIFO. */
if (devtype != RSH_DEV_TYPE_NET && devtype != RSH_DEV_TYPE_CONSOLE) {
ERROR("bad devtype %d", devtype);
return -EINVAL;
}
if (bd->is_boot_open)
return 0;
while (total < count) {
if (avail == 0) {
retval = bd->read_rshim(bd, RSHIM_CHANNEL,
RSH_TM_TILE_TO_HOST_STS, &word);
if (retval < 0)
break;
avail = word & RSH_TM_TILE_TO_HOST_STS__COUNT_MASK;
if (avail == 0)
break;
}
retval = bd->read_rshim(bd, RSHIM_CHANNEL,
RSH_TM_TILE_TO_HOST_DATA, &word);
if (retval < 0)
break;
/*
* Convert it to little endian before sending to RShim. The
* other side should decode it as little endian as well which
* is usually the default case.
*/
word = le64_to_cpu(word);
if (total + sizeof(word) <= count) {
*(u64 *)buf = word;
buf += sizeof(word);
total += sizeof(word);
} else {
/* Copy the rest data which is less than 8 bytes. */
memcpy(buf, &word, count - total);
total = count;
break;
}
avail--;
}
return total;
}
/*
* Write some bytes to the RShim backend.
*
* If count is not multiple of 8-bytes, the data will be padded to 8-byte
* aligned which is required by RShim HW.
*/
static ssize_t rshim_write_delayed(struct rshim_backend *bd, int devtype,
const char *buf, size_t count)
{
u64 word;
char pad_buf[sizeof(u64)] = { 0 };
int size_addr, size_mask, data_addr, max_size;
int retval, avail = 0, byte_cnt = 0;
unsigned long timeout, cur_time;
switch (devtype) {
case RSH_DEV_TYPE_NET:
case RSH_DEV_TYPE_CONSOLE:
if (bd->is_boot_open)
return count;
size_addr = RSH_TM_HOST_TO_TILE_STS;
size_mask = RSH_TM_HOST_TO_TILE_STS__COUNT_MASK;
data_addr = RSH_TM_HOST_TO_TILE_DATA;
retval = bd->read_rshim(bd, RSHIM_CHANNEL,
RSH_TM_HOST_TO_TILE_CTL, &word);
if (retval < 0) {
ERROR("read_rshim error %d", retval);
return retval;
}
max_size = (word >> RSH_TM_HOST_TO_TILE_CTL__MAX_ENTRIES_SHIFT)
& RSH_TM_HOST_TO_TILE_CTL__MAX_ENTRIES_RMASK;
break;
case RSH_DEV_TYPE_BOOT:
size_addr = RSH_BOOT_FIFO_COUNT;
size_mask = RSH_BOOT_FIFO_COUNT__BOOT_FIFO_COUNT_MASK;
data_addr = RSH_BOOT_FIFO_DATA;
max_size = RSH_BOOT_FIFO_SIZE;
break;
default:
ERROR("bad devtype %d", devtype);
return -EINVAL;
}
timeout = msecs_to_jiffies(rshim_boot_timeout * 1000);
while (byte_cnt < count) {
/* Check the boot cancel condition. */
if (devtype == RSH_DEV_TYPE_BOOT && !bd->boot_work_buf)
break;
/* Add padding if less than 8 bytes left. */
if (byte_cnt + sizeof(u64) > count) {
memcpy(pad_buf, buf, count - byte_cnt);
buf = (const char *)pad_buf;
}
cur_time = jiffies + timeout;
while (avail <= 0) {
/* Calculate available space in words. */
retval = bd->read_rshim(bd, RSHIM_CHANNEL, size_addr,
&word);
if (retval < 0) {
ERROR("read_rshim error %d", retval);
break;
}
avail = max_size - (int)(word & size_mask) - 8;
if (avail > 0)
break;
/* Return failure if the peer is not responding. */
if (time_after(jiffies, cur_time))
return -ETIMEDOUT;
mutex_unlock(&bd->mutex);
msleep_interruptible(1);
mutex_lock(&bd->mutex);
/* Drop and return if driver untached. */
if (!bd->has_rshim)
return count;
if (signal_pending(current))
return -ERESTARTSYS;
}
word = *(u64 *)buf;
/*
* Convert to little endian before sending to RShim. The
* receiving side should call le64_to_cpu() to convert
* it back.
*/
word = cpu_to_le64(word);
retval = bd->write_rshim(bd, RSHIM_CHANNEL, data_addr, word);
if (retval < 0) {
ERROR("write_rshim error %d", retval);
break;
}
buf += sizeof(word);
byte_cnt += sizeof(word);
avail--;
}
/* Return number shouldn't count the padded bytes. */
return (byte_cnt > count) ? count : byte_cnt;
}
static ssize_t rshim_write_default(struct rshim_backend *bd, int devtype,
const char *buf, size_t count)
{
int retval;
switch (devtype) {
case RSH_DEV_TYPE_NET:
case RSH_DEV_TYPE_CONSOLE:
if (bd->is_boot_open)
return count;
/* Set the flag so there is only one outstanding request. */
bd->spin_flags |= RSH_SFLG_WRITING;
/* Wake up the worker. */
bd->fifo_work_buf = (char *)buf;
bd->fifo_work_buf_len = count;
bd->fifo_work_devtype = devtype;
wmb();
bd->has_fifo_work = 1;
queue_delayed_work(rshim_wq, &bd->work, 0);
return 0;
case RSH_DEV_TYPE_BOOT:
reinit_completion(&bd->boot_write_complete);
bd->boot_work_buf_len = count;
bd->boot_work_buf_actual_len = 0;
wmb();
bd->boot_work_buf = (char *)buf;
queue_delayed_work(rshim_wq, &bd->work, 0);
mutex_unlock(&bd->mutex);
retval = wait_for_completion_interruptible(
&bd->boot_write_complete);
/* Cancel the request if interrupted. */
if (retval)
bd->boot_work_buf = NULL;
mutex_lock(&bd->mutex);
return bd->boot_work_buf_actual_len;
default:
ERROR("bad devtype %d", devtype);
return -EINVAL;
}
}
/*
* Write to the RShim reset control register.
*/
static int rshim_write_reset_control(struct rshim_backend *bd)
{
int ret;
u64 word;
u32 val;
u8 shift;
ret = bd->read_rshim(bd, RSHIM_CHANNEL, RSH_RESET_CONTROL, &word);
if (ret < 0) {
ERROR("failed to read rshim reset control error %d", ret);
return ret;
}
val = RSH_RESET_CONTROL__RESET_CHIP_VAL_KEY;
shift = RSH_RESET_CONTROL__RESET_CHIP_SHIFT;
word &= ~((u64) RSH_RESET_CONTROL__RESET_CHIP_MASK);
word |= (val << shift);
/*
* The reset of the ARM can be blocked when the DISABLED bit
* is set. The big assumption is that the DISABLED bit would
* be hold high for a short period and only the platform code
* can reset that bit. Thus the ARM reset can be delayed and
* in theory this should not impact the behavior of the RShim
* driver.
*/
ret = bd->write_rshim(bd, RSHIM_CHANNEL, RSH_RESET_CONTROL, word);
if (ret < 0) {
ERROR("failed to write rshim reset control error %d", ret);
return ret;
}
return 0;
}
/* Boot file operations routines */
/*
* Wait for boot to complete, if necessary. Return 0 if the boot is done
* and it's safe to continue, an error code if something went wrong. Note
* that this routine must be called with the device mutex held. If it
* returns successfully, the mutex will still be held (although it may have
* been dropped and reacquired); if it returns unsuccessfully the mutex
* will have been dropped.
*/
static int wait_for_boot_done(struct rshim_backend *bd)
{
int retval;
if (!bd->has_reprobe || rshim_sw_reset_skip)
return 0;
if (!bd->has_rshim || bd->is_booting) {
while (bd->is_booting) {
pr_info("boot write, waiting for re-probe\n");
/* We're booting, and the backend isn't ready yet. */
mutex_unlock(&bd->mutex);
/*
* FIXME: might we want a timeout here, too? If
* the reprobe takes a very long time, something's
* probably wrong. Maybe a couple of minutes?
*/
retval = wait_for_completion_interruptible(
&bd->booting_complete);
if (retval)
return retval;
mutex_lock(&bd->mutex);
}
if (!bd->has_rshim) {
mutex_unlock(&bd->mutex);
return -ENODEV;
}
}
return 0;
}
static ssize_t rshim_boot_write(struct file *file, const char *user_buffer,
size_t count, loff_t *ppos)
{
struct rshim_backend *bd = file->private_data;
int retval = 0, whichbuf = 0, len;
size_t bytes_written = 0;
mutex_lock(&bd->mutex);
if (bd->is_in_boot_write) {
mutex_unlock(&bd->mutex);
return -EBUSY;
}
retval = wait_for_boot_done(bd);
if (retval) {
pr_err("boot_write: wait for boot failed, err %d\n", retval);
/* wait_for_boot_done already dropped mutex */
return retval;
}
/*
* We're going to drop the mutex while we wait for any outstanding
* write to complete; this keeps another thread from getting in here
* while we do that.
*/
bd->is_in_boot_write = 1;
/* Loop as long as there is 8 bytes (minimum size for rshim write). */
while (count + bd->boot_rem_cnt >= sizeof(u64)) {
size_t buf_bytes = min((size_t)BOOT_BUF_SIZE,
(count + bd->boot_rem_cnt) & (-((size_t)8)));
char *buf = bd->boot_buf[whichbuf];
whichbuf ^= 1;
/* Copy the previous remaining data first. */
if (bd->boot_rem_cnt)
memcpy(buf, &bd->boot_rem_data, bd->boot_rem_cnt);
if (copy_from_user(buf + bd->boot_rem_cnt, user_buffer,
buf_bytes - bd->boot_rem_cnt)) {
retval = -EFAULT;
pr_err("boot_write: copy from user failed\n");
break;
}
retval = bd->write(bd, RSH_DEV_TYPE_BOOT, buf, buf_bytes);
if (retval > bd->boot_rem_cnt) {
len = retval - bd->boot_rem_cnt;
count -= len;
user_buffer += len;
bytes_written += len;
bd->boot_rem_cnt = 0;
} else if (retval == 0) {
/* Wait for some time instead of busy polling. */
msleep_interruptible(1);
if (signal_pending(current)) {
retval = -ERESTARTSYS;
break;
}
continue;
}
if (retval != buf_bytes)
break;
}
/* Buffer the remaining data. */
if (count + bd->boot_rem_cnt < sizeof(bd->boot_rem_data)) {
if (copy_from_user((u8*)&bd->boot_rem_data + bd->boot_rem_cnt,
user_buffer, count))
return -EFAULT;
bd->boot_rem_cnt += count;
bytes_written += count;
}
bd->is_in_boot_write = 0;
mutex_unlock(&bd->mutex);
return bytes_written ? bytes_written : retval;
}
static int rshim_boot_release(struct inode *inode, struct file *file)
{
struct rshim_backend *bd = file->private_data;
struct module *owner;
int retval;
/* Restore the boot mode register. */
retval = bd->write_rshim(bd, RSHIM_CHANNEL,
RSH_BOOT_CONTROL,
RSH_BOOT_CONTROL__BOOT_MODE_VAL_EMMC);
if (retval)
ERROR("couldn't set boot_control, err %d", retval);
mutex_lock(&bd->mutex);
/* Flush the leftover data with zeros padded. */
if (bd->boot_rem_cnt) {
memset((u8*)&bd->boot_rem_data + bd->boot_rem_cnt, 0,
sizeof(u64) - bd->boot_rem_cnt);
bd->write_rshim(bd, RSHIM_CHANNEL, RSH_BOOT_FIFO_DATA,
bd->boot_rem_data);
}
bd->is_boot_open = 0;
queue_delayed_work(rshim_wq, &bd->work, HZ);
mutex_unlock(&bd->mutex);
rshim_lock();
owner = RSHIM_READ_ONCE(bd->owner);
kref_put(&bd->kref, bd->destroy);
module_put(owner);
rshim_unlock();
return 0;
}
static const struct file_operations rshim_boot_fops = {
.owner = THIS_MODULE,
.write = rshim_boot_write,
.release = rshim_boot_release,
};
int rshim_boot_open(struct file *file)
{
int retval;
int i;
struct rshim_backend *bd = file->private_data;
#if RSH_RESET_MUTEX
unsigned long devs_locked = 0;
#endif
file->f_op = &rshim_boot_fops;
#if RSH_RESET_MUTEX
/*
* We're going to prevent resets and operations from running in
* parallel with other resets. Our method for this is to grab
* every device's mutex before doing the reset, and then holding
* onto them until the device we reset is reprobed, or a timeout
* expires; the latter is mostly paranoia. Anyway, in order to
* find all of the other devices, we're going to need to walk the
* device table, so we need to grab its mutex. We have to do it
* before we get our own device's mutex for lock ordering reasons.
*/
rshim_lock();
#endif
mutex_lock(&bd->mutex);
if (bd->is_boot_open) {
INFO("can't boot, boot file already open");
mutex_unlock(&bd->mutex);
#if RSH_RESET_MUTEX
rshim_unlock();
#endif
return -EBUSY;
}
if (!bd->has_rshim) {
mutex_unlock(&bd->mutex);
#if RSH_RESET_MUTEX
rshim_unlock();
#endif
return -ENODEV;
}
pr_info("begin booting\n");
reinit_completion(&bd->booting_complete);
bd->is_booting = 1;
bd->boot_rem_cnt = 0;
/*
* Before we reset the chip, make sure we don't have any
* outstanding writes, and flush the write and read FIFOs. (Note
* that we can't have any outstanding reads, since we kill those
* upon release of the TM FIFO file.)
*/
if (bd->cancel)
bd->cancel(bd, RSH_DEV_TYPE_NET, true);
bd->read_buf_bytes = 0;
bd->read_buf_pkt_rem = 0;
bd->read_buf_pkt_padding = 0;
spin_lock_irq(&bd->spinlock);
/* FIXME: should we be waiting for WRITING to go off, instead? */
bd->spin_flags &= ~RSH_SFLG_WRITING;
for (i = 0; i < TMFIFO_MAX_CHAN; i++) {
read_reset(bd, i);
write_reset(bd, i);
}
spin_unlock_irq(&bd->spinlock);
/* Set RShim (external) boot mode. */
retval = bd->write_rshim(bd, RSHIM_CHANNEL, RSH_BOOT_CONTROL,
RSH_BOOT_CONTROL__BOOT_MODE_VAL_NONE);
if (retval) {
ERROR("boot_open: error %d writing boot control", retval);
bd->is_booting = 0;
mutex_unlock(&bd->mutex);
#if RSH_RESET_MUTEX
rshim_unlock();
#endif
return retval;
}
if (rshim_sw_reset_skip) {
bd->is_boot_open = 1;
mutex_unlock(&bd->mutex);
#if RSH_RESET_MUTEX
rshim_unlock();
#endif
return 0;
}
#if RSH_RESET_MUTEX
/*
* Acquire all of the other devices' mutexes, to keep them from
* doing anything while we're performing the reset. Also kill
* any outstanding boot urbs; that way we'll restart them, after
* the reset is done, and not report errors to the writers.
*/
for (i = 0; i < rshim_nr_devs; i++) {
if (rshim_devs[i] && rshim_devs[i] != bd) {
mutex_lock(&rshim_devs[i]->mutex);
devs_locked |= 1UL << i;
if (rshim_devs[i]->cancel) {
rshim_devs[i]->cancel(rshim_devs[i],
RSH_DEV_TYPE_BOOT, true);
}
}
}
reinit_completion(&bd->reset_complete);
#endif
bd->is_boot_open = 1;
/*
* Disable the watchdog. The channel and offset are the same on all
* the BlueField SoC so far.
*/
bd->write_rshim(bd, RSH_MMIO_ADDRESS_SPACE__CHANNEL_VAL_WDOG1,
RSH_ARM_WDG_CONTROL_WCS, 0);
/* SW reset. */
retval = rshim_write_reset_control(bd);
/* Reset the TmFifo. */
rshim_fifo_reset(bd);
/*
* Note that occasionally, we get various errors on writing to
* the reset register. This appears to be caused by the chip
* actually resetting before the response goes out, or perhaps by
* our noticing the device unplug before we've seen the response.
* Either way, the chip _does_ actually reset, so we just ignore
* the error. Should we ever start getting these errors without
* the chip being reset, we'll have to figure out how to handle
* this more intelligently. (One potential option is to not reset
* directly, but to set up a down counter to do the reset, but that
* seems kind of kludgy, especially since Tile software might also
* be trying to use the down counter.)
*/
if (retval && retval != -EPROTO && retval != -ESHUTDOWN &&
#ifdef RSH_USB_BMC
/*
* The host driver on the BMC sometimes produces EOVERFLOW on
* reset. It also seems to have seems to have some sort of bug
* which makes it return more bytes than we actually wrote! In
* that case we're returning EBADE.
*/
retval != -EOVERFLOW && retval != -EBADE &&
#endif
retval != -ETIMEDOUT && retval != -EPIPE) {
ERROR("boot_open: error %d writing reset control", retval);
mutex_unlock(&bd->mutex);
#if RSH_RESET_MUTEX
while (devs_locked) {
int i = __builtin_ctzl(devs_locked);
mutex_unlock(&rshim_devs[i]->mutex);
devs_locked &= ~(1UL << i);
}
rshim_unlock();
#endif
bd->is_boot_open = 0;
return retval;
}
if (retval)
pr_err("boot_open: got error %d on reset write\n", retval);
mutex_unlock(&bd->mutex);
#if RSH_RESET_MUTEX
rshim_unlock();
/*
* We wait for reset_complete (signaled by probe), or for an
* interrupt, or a timeout (set to 5s because of no re-probe
* in the PCIe case). Note that we dropped dev->mutex above
* so that probe can run; the BOOT_OPEN flag should keep our device
* from trying to do anything before the device is reprobed.
*/
retval = wait_for_completion_interruptible_timeout(&bd->reset_complete,
5 * HZ);
if (retval == 0 && bd->has_reprobe)
ERROR("timed out waiting for device reprobe after reset");
while (devs_locked) {
int i = __builtin_ctz(devs_locked);
mutex_unlock(&rshim_devs[i]->mutex);
devs_locked &= ~(1UL << i);
}
#endif
return 0;
}
/* FIFO common routines */
/*
* Signal an error on the FIFO, and wake up anyone who might need to know
* about it.
*/
static void rshim_fifo_err(struct rshim_backend *bd, int err)
{
int i;
bd->tmfifo_error = err;
wake_up_interruptible_all(&bd->write_completed);
for (i = 0; i < TMFIFO_MAX_CHAN; i++) {
wake_up_interruptible_all(&bd->read_fifo[i].operable);
wake_up_interruptible_all(&bd->write_fifo[i].operable);
}
}
static int rshim_fifo_tx_avail(struct rshim_backend *bd)
{
u64 word;
int ret, max_size, avail;
/* Get FIFO max size. */
ret = bd->read_rshim(bd, RSHIM_CHANNEL,
RSH_TM_HOST_TO_TILE_CTL, &word);
if (ret < 0) {
ERROR("read_rshim error %d", ret);
return ret;
}
max_size = (word >> RSH_TM_HOST_TO_TILE_CTL__MAX_ENTRIES_SHIFT)
& RSH_TM_HOST_TO_TILE_CTL__MAX_ENTRIES_RMASK;
/* Calculate available size. */
ret = bd->read_rshim(bd, RSHIM_CHANNEL, RSH_TM_HOST_TO_TILE_STS, &word);
if (ret < 0) {
ERROR("read_rshim error %d", ret);
return ret;
}
avail = max_size - (int)(word & RSH_TM_HOST_TO_TILE_STS__COUNT_MASK)
- 1;
return avail;
}
static int rshim_fifo_sync(struct rshim_backend *bd)
{
int i, avail, ret;
union rshim_tmfifo_msg_hdr hdr;
avail = rshim_fifo_tx_avail(bd);
if (avail < 0)
return avail;
hdr.data = 0;
hdr.type = VIRTIO_ID_NET;
for (i = 0; i < avail; i++) {
ret = bd->write_rshim(bd, RSHIM_CHANNEL,
RSH_TM_HOST_TO_TILE_DATA, hdr.data);
if (ret < 0)
return ret;
}
return 0;
}
/* Just adds up all the bytes of the header. */
static u8 rshim_fifo_ctrl_checksum(union rshim_tmfifo_msg_hdr *hdr)
{
u8 checksum = 0;
int i;
for (i = 0; i < sizeof(*hdr); i++)
checksum += ((u8 *)hdr)[i];
return checksum;
}
static void rshim_fifo_ctrl_update_checksum(union rshim_tmfifo_msg_hdr *hdr)
{
u8 checksum;
hdr->checksum = 0;
checksum = rshim_fifo_ctrl_checksum(hdr);
hdr->checksum = ~checksum + 1;
}
static bool rshim_fifo_ctrl_verify_checksum(union rshim_tmfifo_msg_hdr *hdr)
{
u8 checksum = rshim_fifo_ctrl_checksum(hdr);
return checksum ? false : true;
}
static void rshim_fifo_ctrl_rx(struct rshim_backend *bd,
union rshim_tmfifo_msg_hdr *hdr)
{
if (!rshim_fifo_ctrl_verify_checksum(hdr))
return;
switch (hdr->type) {
case TMFIFO_MSG_MAC_1:
memcpy(bd->peer_mac, hdr->mac, 3);
break;
case TMFIFO_MSG_MAC_2:
memcpy(bd->peer_mac + 3, hdr->mac, 3);
break;
case TMFIFO_MSG_VLAN_ID:
bd->vlan[0] = ntohs(hdr->vlan[0]);
bd->vlan[1] = ntohs(hdr->vlan[1]);
break;
case TMFIFO_MSG_PXE_ID:
bd->pxe_client_id = ntohl(hdr->pxe_id);
/* Last info to receive, set the flag. */
bd->peer_ctrl_resp = 1;
wake_up_interruptible_all(&bd->ctrl_wait);
break;
default:
return;
}
}
static int rshim_fifo_ctrl_tx(struct rshim_backend *bd)
{
union rshim_tmfifo_msg_hdr hdr;
int len = 0;
if (bd->peer_mac_set) {
bd->peer_mac_set = 0;
hdr.data = 0;
hdr.type = TMFIFO_MSG_MAC_1;
memcpy(hdr.mac, bd->peer_mac, 3);
rshim_fifo_ctrl_update_checksum(&hdr);
memcpy(bd->write_buf, &hdr.data, sizeof(hdr.data));
hdr.type = TMFIFO_MSG_MAC_2;
memcpy(hdr.mac, bd->peer_mac + 3, 3);
rshim_fifo_ctrl_update_checksum(&hdr);
memcpy(bd->write_buf + sizeof(hdr.data), &hdr.data,
sizeof(hdr.data));
len = sizeof(hdr.data) * 2;