From 44d4af5eacfdb1920157780ef719397a2e7dce7d Mon Sep 17 00:00:00 2001 From: Unknown Date: Mon, 19 Jul 2021 11:29:51 +0200 Subject: [PATCH] changed TIm1 ISR to proces only CC or Overflow --- Inc/FreeRTOSConfig.h | 2 +- Inc/tim64extender.h | 5 + Src/freertos.cpp | 1 + Src/stm32f7xx_it.c | 18 +-- Src/tim.c | 4 +- Src/tim64extender.c | 269 +++++++++++++++++++++++++------------------ met4FOF_SSU_V2.ioc | 45 ++++---- 7 files changed, 201 insertions(+), 143 deletions(-) diff --git a/Inc/FreeRTOSConfig.h b/Inc/FreeRTOSConfig.h index 14573a5..13ec985 100755 --- a/Inc/FreeRTOSConfig.h +++ b/Inc/FreeRTOSConfig.h @@ -104,7 +104,7 @@ function. */ routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER PRIORITY THAN THIS! (higher priorities are lower numeric values. */ -#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 4 /* Interrupt priorities used by the kernel port layer itself. These are generic to all Cortex-M ports, and do not rely on any particular library functions. */ diff --git a/Inc/tim64extender.h b/Inc/tim64extender.h index da2927a..b3df0d9 100755 --- a/Inc/tim64extender.h +++ b/Inc/tim64extender.h @@ -19,6 +19,11 @@ uint64_t TIM_Get_64Bit_TimeStamp_IC(TIM_HandleTypeDef * htim); uint64_t TIM_Get_64Bit_TimeStamp_Base(TIM_HandleTypeDef * htim); +void TIM1_Increase_Upper_bitmask(); +void HAL_TIM_IRQHandlerOnlyCC(TIM_HandleTypeDef *htim); + + + #ifdef __cplusplus } #endif diff --git a/Src/freertos.cpp b/Src/freertos.cpp index 7ebc155..c460199 100644 --- a/Src/freertos.cpp +++ b/Src/freertos.cpp @@ -960,6 +960,7 @@ void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef * htim) { if (GPSUARTDMA_START_result != HAL_OK) { SEGGER_RTT_printf(0, "DMA start ERROR "); switch(GPSUARTDMA_START_result){ + case HAL_OK: break; case HAL_ERROR: SEGGER_RTT_printf(0, "HAL_ERROR\n");HAL_DMA_Abort(&hdma_uart7_rx); break; case HAL_BUSY: SEGGER_RTT_printf(0, "HAL_BUSY\n");HAL_DMA_Abort(&hdma_uart7_rx); break; case HAL_TIMEOUT:SEGGER_RTT_printf(0, "HAL_TIMEOUT\n");HAL_DMA_Abort(&hdma_uart7_rx); break; diff --git a/Src/stm32f7xx_it.c b/Src/stm32f7xx_it.c index 82569c1..eca841f 100755 --- a/Src/stm32f7xx_it.c +++ b/Src/stm32f7xx_it.c @@ -22,6 +22,7 @@ #include "main.h" #include "stm32f7xx_it.h" #include "cmsis_os.h" +#include "tim64extender.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ @@ -112,11 +113,8 @@ void MemManage_Handler(void) /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ - /* USER CODE END W1_MemoryManagement_IRQn 0 */ - } + SEGGER_RTT_printf(0,"Oh no MemManageFault :( Reseting MCU"); + NVIC_SystemReset(); } /** @@ -128,7 +126,8 @@ void BusFault_Handler(void) HAL_GPIO_WritePin(SIG_HARDFAULT_GPIO_Port, SIG_HARDFAULT_Pin, GPIO_PIN_SET); /* USER CODE END HardFault_IRQn 0 */ /* USER CODE BEGIN W1_HardFault_IRQn 0 */ - SEGGER_RTT_printf(0,"Oh no BusFault :( Doing noting"); + SEGGER_RTT_printf(0,"Oh no BusFault :( Reseting MCU"); + NVIC_SystemReset(); /* USER CODE END W1_HardFault_IRQn 0 */ } @@ -137,7 +136,6 @@ void BusFault_Handler(void) */ void UsageFault_Handler(void) { - SEGGER_SYSVIEW_RecordEnterISR(); /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ @@ -218,7 +216,9 @@ void TIM1_UP_TIM10_IRQHandler(void) /* USER CODE BEGIN TIM1_UP_TIM10_IRQn 0 */ /* USER CODE END TIM1_UP_TIM10_IRQn 0 */ - HAL_TIM_IRQHandler(&htim1); + //HAL_TIM_IRQHandler(&htim1); + __HAL_TIM_CLEAR_IT(&htim1, TIM_IT_UPDATE);// clear update status bit + TIM1_Increase_Upper_bitmask(); /* USER CODE BEGIN TIM1_UP_TIM10_IRQn 1 */ /* USER CODE END TIM1_UP_TIM10_IRQn 1 */ @@ -232,7 +232,7 @@ void TIM1_CC_IRQHandler(void) /* USER CODE BEGIN TIM1_CC_IRQn 0 */ /* USER CODE END TIM1_CC_IRQn 0 */ - HAL_TIM_IRQHandler(&htim1); + HAL_TIM_IRQHandlerOnlyCC(&htim1); /* USER CODE BEGIN TIM1_CC_IRQn 1 */ /* USER CODE END TIM1_CC_IRQn 1 */ diff --git a/Src/tim.c b/Src/tim.c index e560632..53d4d8b 100755 --- a/Src/tim.c +++ b/Src/tim.c @@ -163,9 +163,9 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); /* TIM1 interrupt Init */ - HAL_NVIC_SetPriority(TIM1_UP_TIM10_IRQn, 5, 0); + HAL_NVIC_SetPriority(TIM1_UP_TIM10_IRQn, 4, 0);// tim1 higher prio than tim2 since its overflowing more often HAL_NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn); - HAL_NVIC_SetPriority(TIM1_CC_IRQn, 5, 0); + HAL_NVIC_SetPriority(TIM1_CC_IRQn, 4, 0);// tim1 higher prio than tim2 since its overflowing more often HAL_NVIC_EnableIRQ(TIM1_CC_IRQn); /* USER CODE BEGIN TIM1_MspInit 1 */ diff --git a/Src/tim64extender.c b/Src/tim64extender.c index 0b4675b..ddfab24 100755 --- a/Src/tim64extender.c +++ b/Src/tim64extender.c @@ -7,12 +7,12 @@ /* Includes ------------------------------------------------------------------*/ #include "tim64extender.h" -//Top 32 bit for timer2 inputcapture values -static uint64_t tim2_update_counts=0; -static uint64_t tim2_upper_bits_mask=0; -//Top 48 bit for timer2 inputcapture values -static uint64_t tim1_update_counts=0; -static uint64_t tim1_upper_bits_mask=0; + //Top 32 bit for timer2 inputcapture values + static uint64_t tim2_update_counts=0; + static uint64_t tim2_upper_bits_mask=0; + //Top 48 bit for timer2 inputcapture values + static uint64_t tim1_update_counts=0; + static uint64_t tim1_upper_bits_mask=0; uint64_t TIM_Get_64Bit_TimeStamp_Base(TIM_HandleTypeDef * htim){ uint64_t timestamp=0; @@ -47,38 +47,9 @@ uint64_t TIM_Get_64Bit_TimeStamp_Base(TIM_HandleTypeDef * htim){ } } } - uint64_t tim1_upper_bits_mask_race_condition = 0; - bool tim1_race_condition_up_date = false; if (htim->Instance == TIM1) { - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); - //the flag gets cleared to prevent HAL_TIM_PeriodElapsedCallback() calling and therfore double increasment - //DEBUG_MSG("WARNING!!! TIMER OVERFLOW DETECTED OUTSIDE OF UPDATEEVENTHANDLER\n START SPECIAL HANDLING CHECK RESULTS OF THIS MESURMENT CYCLE"); - tim1_race_condition_up_date = true; - tim1_upper_bits_mask_race_condition = tim1_upper_bits_mask; - tim1_update_counts++; - tim1_upper_bits_mask = (uint64_t)(tim1_update_counts-2) << 16;//timer gets initaled with set upodateflag but we want to start at zero therfore -1 - } - } - } - if (htim->Instance == TIM1) { - if (tim1_race_condition_up_date == false) { - //this is the nromal case - timestamp = tim1_upper_bits_mask - + (uint64_t) __HAL_TIM_GetCounter(&htim1)+1; - } else { - uint32_t timestamp_raw = __HAL_TIM_GetCounter(&htim1); - if (timestamp_raw < TIM16OLDTIMERVALMIN) - //the timer has overflowen tak the updateted bitmask - { - timestamp = tim1_upper_bits_mask + (uint64_t) timestamp_raw+1; - } else { - //this is an old value using the old bitmask - timestamp = tim1_upper_bits_mask_race_condition - + (uint64_t) timestamp_raw+1; - } - } + // there can't be a race condition here since TIM1 has an an independent interupt for update, so the pending isr are in the right order in the NVIC + timestamp = tim1_upper_bits_mask+ (uint64_t) __HAL_TIM_GetCounter(&htim1)+1; } @@ -126,8 +97,6 @@ uint64_t TIM_Get_64Bit_TimeStamp_IC(TIM_HandleTypeDef * htim){ #define TIM16OLDTIMERVALMIN 0xF000 // if an inputcaputure value is biger than this its prppably an old one uint64_t tim2_upper_bits_mask_race_condition = 0; bool tim2_race_condition_up_date = false; - uint64_t tim1_upper_bits_mask_race_condition = 0; - bool tim1_race_condition_up_date = false; if (htim->Instance == TIM2) { if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) { @@ -210,78 +179,31 @@ uint64_t TIM_Get_64Bit_TimeStamp_IC(TIM_HandleTypeDef * htim){ if (htim->Instance == TIM1) { - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); - //the flag gets cleared to prevent HAL_TIM_PeriodElapsedCallback() calling and therfore double increasment - //DEBUG_MSG("WARNING!!! TIMER OVERFLOW DETECTED OUTSIDE OF UPDATEEVENTHANDLER\n START SPECIAL HANDLING CHECK RESULTS OF THIS MESURMENT CYCLE"); - tim1_race_condition_up_date = true; - tim1_upper_bits_mask_race_condition = tim1_upper_bits_mask; - tim1_update_counts++; - tim1_upper_bits_mask = (uint64_t)(tim1_update_counts-2) << 16;//timer gets initaled with set upodateflag but we want to start at zero therfore -1 - } - } - + // there can't be a race condition here since TIM1 has an an independent interupt for update, so the pending isr are in the right order in the NVIC if (htim->Channel == HAL_TIM_ACTIVE_CHANNEL_1) { - if (tim1_race_condition_up_date == false) { //this is the nromal case - timestamp = tim1_upper_bits_mask - + (uint64_t) HAL_TIM_ReadCapturedValue(&htim1, - TIM_CHANNEL_1)+1; - } else { - uint32_t timestamp_raw = HAL_TIM_ReadCapturedValue(&htim1, - TIM_CHANNEL_1); - if (timestamp_raw < TIM16OLDTIMERVALMIN) - //the timer has overflowen tak the updateted bitmask - { - timestamp = tim1_upper_bits_mask + (uint64_t) timestamp_raw+1; - } else { - //this is an old value using the old bitmask - timestamp = tim1_upper_bits_mask_race_condition - + (uint64_t) timestamp_raw+1; - } - } + timestamp = tim1_upper_bits_mask+ (uint64_t) HAL_TIM_ReadCapturedValue(&htim1,TIM_CHANNEL_1)+1; } if (htim->Channel == HAL_TIM_ACTIVE_CHANNEL_2) { - if (tim1_race_condition_up_date == false) { - //this is the nromal case - timestamp = tim1_upper_bits_mask - + (uint64_t) HAL_TIM_ReadCapturedValue(&htim1, - TIM_CHANNEL_2)+1; - } else { - uint32_t timestamp_raw = HAL_TIM_ReadCapturedValue(&htim1, - TIM_CHANNEL_1); - if (timestamp_raw < TIM16OLDTIMERVALMIN) - //the timer has overflowen tak the updateted bitmask - { - timestamp = tim1_upper_bits_mask + (uint64_t) timestamp_raw+1; - } else { - //this is an old value using the old bitmask - timestamp = tim1_upper_bits_mask_race_condition - + (uint64_t) timestamp_raw+1; - } - } + //this is the nromal case + timestamp = tim1_upper_bits_mask+ (uint64_t) HAL_TIM_ReadCapturedValue(&htim1,TIM_CHANNEL_2)+1; } if (htim->Channel == HAL_TIM_ACTIVE_CHANNEL_3) { - if (tim1_race_condition_up_date == false) { - //this is the nromal case - timestamp = tim1_upper_bits_mask - + (uint64_t) HAL_TIM_ReadCapturedValue(&htim1, - TIM_CHANNEL_3)+1; - } else { - uint32_t timestamp_raw = HAL_TIM_ReadCapturedValue(&htim1, - TIM_CHANNEL_1); - if (timestamp_raw < TIM16OLDTIMERVALMIN) - //the timer has overflowen tak the updateted bitmask - { - timestamp = tim1_upper_bits_mask + (uint64_t) timestamp_raw+1; - } else { - //this is an old value using the old bitmask - timestamp = tim1_upper_bits_mask_race_condition - + (uint64_t) timestamp_raw+1; - } - } + //this is the nromal case + timestamp = tim1_upper_bits_mask+ (uint64_t) HAL_TIM_ReadCapturedValue(&htim1,TIM_CHANNEL_3)+1; + } + if (htim->Channel == HAL_TIM_ACTIVE_CHANNEL_4) { + //this is the nromal case + timestamp = tim1_upper_bits_mask+ (uint64_t) HAL_TIM_ReadCapturedValue(&htim1,TIM_CHANNEL_4)+1; + } + if (htim->Channel == HAL_TIM_ACTIVE_CHANNEL_5) { + //this is the nromal case + timestamp = tim1_upper_bits_mask+ (uint64_t) HAL_TIM_ReadCapturedValue(&htim1,TIM_CHANNEL_5)+1; + } + if (htim->Channel == HAL_TIM_ACTIVE_CHANNEL_6) { + //this is the nromal case + timestamp = tim1_upper_bits_mask+ (uint64_t) HAL_TIM_ReadCapturedValue(&htim1,TIM_CHANNEL_6)+1; } } @@ -308,15 +230,140 @@ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { tim2_update_counts++; tim2_upper_bits_mask = (uint64_t)(tim2_update_counts - 1) << 32;//timer gets initaled with set upodateflag but we want to start at zero therfore -1 - } - if (htim->Instance == TIM1) { - { - tim1_update_counts++; - tim1_upper_bits_mask = (uint64_t)(tim1_update_counts-2) << 16;//timer gets initaled with set upodateflag but we want to start at zero therfore -1 - - } } /* USER CODE BEGIN Callback 1 */ /* USER CODE END Callback 1 */ } + +void TIM1_Increase_Upper_bitmask(){ + tim1_update_counts++; + tim1_upper_bits_mask = (uint64_t)(tim1_update_counts-2) << 16;//timer gets initaled with set upodateflag but we want to start at zero therfore -1 +} + +void HAL_TIM_IRQHandlerOnlyCC(TIM_HandleTypeDef *htim) +{ + /* Capture compare 1 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + { + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + } + /* Capture compare 2 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } +} diff --git a/met4FOF_SSU_V2.ioc b/met4FOF_SSU_V2.ioc index c1f1e2d..0f75e03 100755 --- a/met4FOF_SSU_V2.ioc +++ b/met4FOF_SSU_V2.ioc @@ -67,12 +67,12 @@ ETH.MediaInterface=ETH_MEDIA_INTERFACE_RMII ETH.PHY_Name=LAN8742A_PHY_ADDRESS ETH.PHY_Value=0 ETH.PhyAddress=1 -FREERTOS.Events01= FREERTOS.FootprintOK=true -FREERTOS.IPParameters=Tasks01,configUSE_TRACE_FACILITY,configMINIMAL_STACK_SIZE,configQUEUE_REGISTRY_SIZE,configMAX_TASK_NAME_LEN,configTOTAL_HEAP_SIZE,configUSE_COUNTING_SEMAPHORES,configCHECK_FOR_STACK_OVERFLOW,MEMORY_ALLOCATION,FootprintOK,Events01 +FREERTOS.IPParameters=Tasks01,configUSE_TRACE_FACILITY,configMINIMAL_STACK_SIZE,configQUEUE_REGISTRY_SIZE,configMAX_TASK_NAME_LEN,configTOTAL_HEAP_SIZE,configUSE_COUNTING_SEMAPHORES,configCHECK_FOR_STACK_OVERFLOW,MEMORY_ALLOCATION,FootprintOK,configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY FREERTOS.MEMORY_ALLOCATION=0 FREERTOS.Tasks01=defaultTask,0,512,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL FREERTOS.configCHECK_FOR_STACK_OVERFLOW=2 +FREERTOS.configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY=4 FREERTOS.configMAX_TASK_NAME_LEN=32 FREERTOS.configMINIMAL_STACK_SIZE=512 FREERTOS.configQUEUE_REGISTRY_SIZE=32 @@ -111,8 +111,9 @@ Mcu.IP18=SYS Mcu.IP19=TIM1 Mcu.IP2=ADC3 Mcu.IP20=TIM2 -Mcu.IP21=UART7 -Mcu.IP22=USART3 +Mcu.IP21=TIM8 +Mcu.IP22=UART7 +Mcu.IP23=USART3 Mcu.IP3=CORTEX_M7 Mcu.IP4=DMA Mcu.IP5=ETH @@ -120,7 +121,7 @@ Mcu.IP6=FREERTOS Mcu.IP7=I2C1 Mcu.IP8=LWIP Mcu.IP9=NVIC -Mcu.IPNb=23 +Mcu.IPNb=24 Mcu.Name=STM32F767ZITx Mcu.Package=LQFP144 Mcu.Pin0=PE2 @@ -214,22 +215,23 @@ Mcu.Pin88=VP_TIM1_VS_ClockSourceINT Mcu.Pin89=VP_TIM1_VS_ClockSourceITR Mcu.Pin9=PF1 Mcu.Pin90=VP_TIM2_VS_ClockSourceINT -Mcu.PinsNb=91 +Mcu.Pin91=VP_TIM8_VS_ClockSourceINT +Mcu.PinsNb=92 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F767ZITx MxCube.Version=5.2.1 MxDb.Version=DB.5.0.21 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:false -NVIC.DMA1_Stream0_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true -NVIC.DMA1_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true -NVIC.DMA1_Stream6_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true +NVIC.DMA1_Stream0_IRQn=true\:4\:0\:false\:false\:true\:true\:false\:true +NVIC.DMA1_Stream3_IRQn=true\:4\:0\:false\:false\:true\:true\:false\:true +NVIC.DMA1_Stream6_IRQn=true\:4\:0\:false\:false\:true\:true\:false\:true NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:false -NVIC.ETH_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true +NVIC.ETH_IRQn=true\:4\:0\:false\:false\:true\:true\:false\:true NVIC.ForceEnableDMAVector=true NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:false -NVIC.I2C1_ER_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true -NVIC.I2C1_EV_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true +NVIC.I2C1_ER_IRQn=true\:4\:0\:false\:false\:true\:true\:true\:true +NVIC.I2C1_EV_IRQn=true\:4\:0\:false\:false\:true\:true\:true\:true NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:false NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:false NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:true\:false @@ -239,13 +241,13 @@ NVIC.SavedPendsvIrqHandlerGenerated=true NVIC.SavedSvcallIrqHandlerGenerated=true NVIC.SavedSystickIrqHandlerGenerated=true NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:true\:true -NVIC.TIM1_CC_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true -NVIC.TIM1_UP_TIM10_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true -NVIC.TIM2_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true +NVIC.TIM1_CC_IRQn=true\:4\:0\:false\:false\:true\:true\:true\:true +NVIC.TIM1_UP_TIM10_IRQn=true\:4\:0\:false\:false\:true\:true\:true\:true +NVIC.TIM2_IRQn=true\:4\:0\:false\:false\:true\:true\:true\:true NVIC.TIM8_TRG_COM_TIM14_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true NVIC.TimeBase=TIM8_TRG_COM_TIM14_IRQn NVIC.TimeBaseIP=TIM14 -NVIC.UART7_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true +NVIC.UART7_IRQn=true\:4\:0\:false\:false\:true\:true\:true\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:false PA0/WKUP.Signal=S_TIM2_CH1_ETR PA1.GPIOParameters=GPIO_Label @@ -548,7 +550,7 @@ ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=STM32CubeIDE ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_USART3_UART_Init-USART3-false-HAL-true,5-MX_TIM1_Init-TIM1-false-HAL-true,6-MX_TIM2_Init-TIM2-false-HAL-true,7-MX_ADC3_Init-ADC3-false-HAL-true,8-MX_SPI3_Init-SPI3-false-HAL-true,9-MX_SPI1_Init-SPI1-false-HAL-true,10-MX_I2C1_Init-I2C1-false-HAL-true,11-MX_ADC1_Init-ADC1-false-HAL-true,12-MX_ADC2_Init-ADC2-false-HAL-true,13-MX_UART7_Init-UART7-false-HAL-true,14-MX_LWIP_Init-LWIP-false-HAL-false,15-MX_RTC_Init-RTC-false-HAL-true,16-MX_RNG_Init-RNG-false-HAL-true,17-MX_SPI2_Init-SPI2-false-HAL-true,18-MX_SPI4_Init-SPI4-false-HAL-true,19-MX_SPI5_Init-SPI5-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_USART3_UART_Init-USART3-false-HAL-true,5-MX_TIM1_Init-TIM1-false-HAL-true,6-MX_TIM2_Init-TIM2-false-HAL-true,7-MX_ADC3_Init-ADC3-false-HAL-true,8-MX_SPI3_Init-SPI3-false-HAL-true,9-MX_SPI1_Init-SPI1-false-HAL-true,10-MX_I2C1_Init-I2C1-false-HAL-true,11-MX_ADC1_Init-ADC1-false-HAL-true,12-MX_ADC2_Init-ADC2-false-HAL-true,13-MX_UART7_Init-UART7-false-HAL-true,14-MX_LWIP_Init-LWIP-false-HAL-false,15-MX_RTC_Init-RTC-false-HAL-true,16-MX_RNG_Init-RNG-false-HAL-true,17-MX_SPI2_Init-SPI2-false-HAL-true,18-MX_SPI4_Init-SPI4-false-HAL-true,19-MX_SPI5_Init-SPI5-false-HAL-true,20-MX_TIM8_Init-TIM8-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true RCC.48MHZClocksFreq_Value=24000000 RCC.ADC12outputFreq_Value=72000000 RCC.ADC34outputFreq_Value=72000000 @@ -703,9 +705,10 @@ SPI5.VirtualType=VM_MASTER TIM1.Channel-Input_Capture1_from_TI1=TIM_CHANNEL_1 TIM1.Channel-Input_Capture2_from_TI2=TIM_CHANNEL_2 TIM1.Channel-Input_Capture3_from_TI3=TIM_CHANNEL_3 -TIM1.IPParameters=Channel-Input_Capture1_from_TI1,Channel-Input_Capture2_from_TI2,Channel-Input_Capture3_from_TI3,Period,Prescaler,TIM_MasterSlaveMode,TIM_MasterOutputTrigger,TIM_MasterOutputTrigger2 +TIM1.ClockDivision=TIM_CLOCKDIVISION_DIV2 +TIM1.IPParameters=Channel-Input_Capture1_from_TI1,Channel-Input_Capture2_from_TI2,Channel-Input_Capture3_from_TI3,Period,Prescaler,TIM_MasterSlaveMode,TIM_MasterOutputTrigger,TIM_MasterOutputTrigger2,ClockDivision TIM1.Period=0xFFFF -TIM1.Prescaler=1 +TIM1.Prescaler=0 TIM1.TIM_MasterOutputTrigger=TIM_TRGO_RESET TIM1.TIM_MasterOutputTrigger2=TIM_TRGO2_RESET TIM1.TIM_MasterSlaveMode=TIM_MASTERSLAVEMODE_ENABLE @@ -739,6 +742,8 @@ VP_TIM1_VS_ControllerModeCombinedResetTrigger.Mode=Combined_Reset_Trigger_Mode VP_TIM1_VS_ControllerModeCombinedResetTrigger.Signal=TIM1_VS_ControllerModeCombinedResetTrigger VP_TIM2_VS_ClockSourceINT.Mode=Internal VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT +VP_TIM8_VS_ClockSourceINT.Mode=Internal +VP_TIM8_VS_ClockSourceINT.Signal=TIM8_VS_ClockSourceINT board=NUCLEO-F767ZI boardIOC=true -isbadioc=false +isbadioc=true