diff --git a/pcsx2/Dmac.h b/pcsx2/Dmac.h index 803b42cfae1d2c..843225deb21ac2 100644 --- a/pcsx2/Dmac.h +++ b/pcsx2/Dmac.h @@ -336,6 +336,7 @@ union tDMAC_CTRL { tDMAC_CTRL(u32 val) { _u32 = val; } bool test(u32 flags) const { return !!(_u32 & flags); } + bool is_mfifo(bool is_vif) const { return (is_vif) ? (MFD == MFD_VIF1) : (MFD == MFD_GIF); } void set_flags(u32 flags) { _u32 |= flags; } void clear_flags(u32 flags) { _u32 &= ~flags; } void reset() { _u32 = 0; } diff --git a/pcsx2/Vif1_MFIFO.cpp b/pcsx2/Vif1_MFIFO.cpp index 8fb1300ae6b846..d477d7819d03d7 100644 --- a/pcsx2/Vif1_MFIFO.cpp +++ b/pcsx2/Vif1_MFIFO.cpp @@ -300,7 +300,7 @@ void vifMFIFOInterrupt() { GUNIT_WARN("vifMFIFOInterrupt() - Waiting for Path 2 to be ready"); CPU_INT(DMAC_MFIFO_VIF, 128); - CPU_SET_DMASTALL(DMAC_VIF1, true); + CPU_SET_DMASTALL(DMAC_MFIFO_VIF, true); return; } } @@ -308,7 +308,7 @@ void vifMFIFOInterrupt() { //DevCon.Warning("Waiting on VU1 MFIFO"); CPU_INT(VIF_VU1_FINISH, std::max(16, cpuGetCycles(VU_MTVU_BUSY))); - CPU_SET_DMASTALL(DMAC_VIF1, true); + CPU_SET_DMASTALL(DMAC_MFIFO_VIF, true); return; } @@ -341,7 +341,7 @@ void vifMFIFOInterrupt() { vif1Regs.stat.VPS = VPS_DECODING; //If there's more data you need to say it's decoding the next VIF CMD (Onimusha - Blade Warriors) VIF_LOG("VIF1 MFIFO Stalled"); - CPU_SET_DMASTALL(DMAC_VIF1, true); + CPU_SET_DMASTALL(DMAC_MFIFO_VIF, true); return; } } @@ -361,7 +361,7 @@ void vifMFIFOInterrupt() if (vif1.inprogress & 0x10) { FireMFIFOEmpty(); - CPU_SET_DMASTALL(DMAC_VIF1, true); + CPU_SET_DMASTALL(DMAC_MFIFO_VIF, true); return; } @@ -412,6 +412,6 @@ void vifMFIFOInterrupt() vif1ch.chcr.STR = false; hwDmacIrq(DMAC_VIF1); DMA_LOG("VIF1 MFIFO DMA End"); - CPU_SET_DMASTALL(DMAC_VIF1, false); + CPU_SET_DMASTALL(DMAC_MFIFO_VIF, false); vif1Regs.stat.FQC = 0; } diff --git a/pcsx2/Vif_Codes.cpp b/pcsx2/Vif_Codes.cpp index 27a78e202455b8..79392eab59416c 100644 --- a/pcsx2/Vif_Codes.cpp +++ b/pcsx2/Vif_Codes.cpp @@ -66,6 +66,11 @@ __ri void vifExecQueue(int idx) }*/ } +static __fi EE_EventType vif1InternalIrq() +{ + return dmacRegs.ctrl.is_mfifo(true) ? DMAC_MFIFO_VIF : DMAC_VIF1; +} + static __fi void vifFlush(int idx) { vifExecQueue(idx); @@ -85,7 +90,7 @@ static __fi void vuExecMicro(int idx, u32 addr, bool requires_wait) vifFlush(idx); if (GetVifX.waitforvu) { - CPU_SET_DMASTALL(idx ? DMAC_VIF1 : DMAC_VIF0, true); + CPU_SET_DMASTALL(idx ? vif1InternalIrq() : DMAC_VIF0, true); return; } @@ -225,7 +230,7 @@ vifOp(vifCode_Flush) if (vif1.waitforvu || vif1Regs.stat.VGW) { - CPU_SET_DMASTALL(DMAC_VIF1, true); + CPU_SET_DMASTALL(vif1InternalIrq(), true); return 0; } @@ -258,7 +263,7 @@ vifOp(vifCode_FlushA) if (vif1.waitforvu || vif1Regs.stat.VGW) { - CPU_SET_DMASTALL(DMAC_VIF1, true); + CPU_SET_DMASTALL(vif1InternalIrq(), true); return 0; } @@ -279,7 +284,7 @@ vifOp(vifCode_FlushE) if (vifX.waitforvu) { - CPU_SET_DMASTALL(idx ? DMAC_VIF1 : DMAC_VIF0, true); + CPU_SET_DMASTALL(idx ? vif1InternalIrq() : DMAC_VIF0, true); return 0; } @@ -387,7 +392,7 @@ vifOp(vifCode_MPG) if (vifX.waitforvu) { - CPU_SET_DMASTALL(idx ? DMAC_VIF1 : DMAC_VIF0, true); + CPU_SET_DMASTALL(idx ? vif1InternalIrq() : DMAC_VIF0, true); return 0; } else @@ -435,7 +440,7 @@ vifOp(vifCode_MSCAL) if (vifX.waitforvu) { - CPU_SET_DMASTALL(idx ? DMAC_VIF1 : DMAC_VIF0, true); + CPU_SET_DMASTALL(idx ? vif1InternalIrq() : DMAC_VIF0, true); return 0; } @@ -474,7 +479,7 @@ vifOp(vifCode_MSCALF) if (vifX.waitforvu || vif1Regs.stat.VGW) { - CPU_SET_DMASTALL(idx ? DMAC_VIF1 : DMAC_VIF0, true); + CPU_SET_DMASTALL(idx ? vif1InternalIrq() : DMAC_VIF0, true); return 0; } @@ -496,7 +501,7 @@ vifOp(vifCode_MSCNT) if (vifX.waitforvu) { - CPU_SET_DMASTALL(idx ? DMAC_VIF1 : DMAC_VIF0, true); + CPU_SET_DMASTALL(idx ? vif1InternalIrq() : DMAC_VIF0, true); return 0; }