diff --git a/pcsx2/Dmac.h b/pcsx2/Dmac.h index 803b42cfae1d2..843225deb21ac 100644 --- a/pcsx2/Dmac.h +++ b/pcsx2/Dmac.h @@ -336,6 +336,7 @@ union tDMAC_CTRL { tDMAC_CTRL(u32 val) { _u32 = val; } bool test(u32 flags) const { return !!(_u32 & flags); } + bool is_mfifo(bool is_vif) const { return (is_vif) ? (MFD == MFD_VIF1) : (MFD == MFD_GIF); } void set_flags(u32 flags) { _u32 |= flags; } void clear_flags(u32 flags) { _u32 &= ~flags; } void reset() { _u32 = 0; } diff --git a/pcsx2/GS.cpp b/pcsx2/GS.cpp index 2878ad480be0a..064750531279d 100644 --- a/pcsx2/GS.cpp +++ b/pcsx2/GS.cpp @@ -50,6 +50,7 @@ static __fi void gsCSRwrite( const tGS_CSR& csr ) //gifUnit.Reset(true); // Don't think gif should be reset... gifUnit.gsSIGNAL.queued = false; gifUnit.gsFINISH.gsFINISHFired = true; + gifUnit.gsFINISH.gsFINISHPending = false; // Privilage registers also reset. std::memset(g_RealGSMem, 0, sizeof(g_RealGSMem)); GSIMR.reset(); @@ -84,6 +85,7 @@ static __fi void gsCSRwrite( const tGS_CSR& csr ) if (csr.FINISH) { CSRreg.FINISH = false; gifUnit.gsFINISH.gsFINISHFired = false; //Clear the previously fired FINISH (YS, Indiecar 2005, MGS3) + gifUnit.gsFINISH.gsFINISHPending = false; } if(csr.HSINT) CSRreg.HSINT = false; if(csr.VSINT) CSRreg.VSINT = false; diff --git a/pcsx2/Gif_Unit.cpp b/pcsx2/Gif_Unit.cpp index 3ca7c67d33018..1ec6adb93aab8 100644 --- a/pcsx2/Gif_Unit.cpp +++ b/pcsx2/Gif_Unit.cpp @@ -84,8 +84,8 @@ bool Gif_HandlerAD(u8* pMem) else if (reg == GIF_A_D_REG_FINISH) { // FINISH GUNIT_WARN("GIF Handler - FINISH"); - CSRreg.FINISH = true; gifUnit.gsFINISH.gsFINISHFired = false; + gifUnit.gsFINISH.gsFINISHPending = true; } else if (reg == GIF_A_D_REG_LABEL) { // LABEL @@ -188,6 +188,11 @@ bool Gif_HandlerAD_Debug(u8* pMem) void Gif_FinishIRQ() { + if (gifUnit.gsFINISH.gsFINISHPending) + { + CSRreg.FINISH = true; + gifUnit.gsFINISH.gsFINISHPending = false; + } if (CSRreg.FINISH && !GSIMR.FINISHMSK && !gifUnit.gsFINISH.gsFINISHFired) { gsIrq(); diff --git a/pcsx2/Gif_Unit.h b/pcsx2/Gif_Unit.h index 9d89503dc66a8..024aa81ae4d20 100644 --- a/pcsx2/Gif_Unit.h +++ b/pcsx2/Gif_Unit.h @@ -177,6 +177,7 @@ struct GS_SIGNAL struct GS_FINISH { bool gsFINISHFired; + bool gsFINISHPending; void Reset() { std::memset(this, 0, sizeof(*this)); } }; @@ -838,7 +839,8 @@ struct Gif_Unit FlushToMTGS(); } - Gif_FinishIRQ(); + if(!checkPaths(true, true, true, true)) + Gif_FinishIRQ(); //Path3 can rewind the DMA, so we send back the amount we go back! if (isPath3) diff --git a/pcsx2/IPU/IPU.cpp b/pcsx2/IPU/IPU.cpp index 3c745277758d6..036397dc31cf3 100644 --- a/pcsx2/IPU/IPU.cpp +++ b/pcsx2/IPU/IPU.cpp @@ -27,6 +27,7 @@ alignas(16) tIPU_cmd ipu_cmd; alignas(16) tIPU_BP g_BP; alignas(16) decoder_t decoder; +IPUStatus IPUCoreStatus; static void (*IPUWorker)(); @@ -92,15 +93,8 @@ void tIPU_cmd::clear() __fi void IPUProcessInterrupt() { - if (ipuRegs.ctrl.BUSY && !CommandExecuteQueued) + if (ipuRegs.ctrl.BUSY) IPUWorker(); - - if (ipuRegs.ctrl.BUSY && !IPU1Status.DataRequested && !(cpuRegs.interrupt & 1 << IPU_PROCESS)) - { - CPU_INT(IPU_PROCESS, ProcessedData ? ProcessedData : 64); - } - else - ProcessedData = 0; } ///////////////////////////////////////////////////////// @@ -112,6 +106,9 @@ void ipuReset() std::memset(&ipuRegs, 0, sizeof(ipuRegs)); std::memset(&g_BP, 0, sizeof(g_BP)); std::memset(&decoder, 0, sizeof(decoder)); + IPUCoreStatus.DataRequested = false; + IPUCoreStatus.WaitingOnIPUFrom= false; + IPUCoreStatus.WaitingOnIPUTo = false; decoder.picture_structure = FRAME_PICTURE; //default: progressive...my guess:P @@ -149,6 +146,7 @@ bool SaveStateBase::ipuFreeze() Freeze(coded_block_pattern); Freeze(decoder); Freeze(ipu_cmd); + Freeze(IPUCoreStatus); return IsOkay(); } @@ -471,7 +469,6 @@ __fi void IPUCMD_WRITE(u32 val) { // don't process anything if currently busy //if (ipuRegs.ctrl.BUSY) Console.WriteLn("IPU BUSY!"); // wait for thread - ProcessedData = 0; ipuRegs.ctrl.ECD = 0; ipuRegs.ctrl.SCD = 0; ipu_cmd.clear(); @@ -538,9 +535,10 @@ __fi void IPUCMD_WRITE(u32 val) // Have a short delay immitating the time it takes to run IDEC/BDEC, other commands are near instant. // Mana Khemia/Metal Saga start IDEC then change IPU0 expecting there to be a delay before IDEC sends data. - if (!CommandExecuteQueued && (ipu_cmd.CMD == SCE_IPU_IDEC || ipu_cmd.CMD == SCE_IPU_BDEC)) + if (ipu_cmd.CMD == SCE_IPU_IDEC || ipu_cmd.CMD == SCE_IPU_BDEC) { - CommandExecuteQueued = true; + IPUCoreStatus.WaitingOnIPUFrom = false; + IPUCoreStatus.WaitingOnIPUTo = false; CPU_INT(IPU_PROCESS, 64); } else diff --git a/pcsx2/IPU/IPU.h b/pcsx2/IPU/IPU.h index 2b180d87a6966..c135c8290ce64 100644 --- a/pcsx2/IPU/IPU.h +++ b/pcsx2/IPU/IPU.h @@ -132,7 +132,7 @@ struct alignas(16) tIPU_BP { // be possible -- so if the fill fails we'll only return 0 if we don't have enough // remaining bits in the FIFO to fill the request. // Used to do ((FP!=0) && (BP + bits) <= 128) if we get here there's defo not enough data now though - + IPUCoreStatus.WaitingOnIPUTo = true; return false; } @@ -293,8 +293,6 @@ extern bool EnableFMV; alignas(16) extern tIPU_cmd ipu_cmd; extern uint eecount_on_last_vdec; -extern bool CommandExecuteQueued; -extern u32 ProcessedData; extern void ipuReset(); diff --git a/pcsx2/IPU/IPU_Fifo.cpp b/pcsx2/IPU/IPU_Fifo.cpp index 8c73ab149526e..d0a39aac15dbd 100644 --- a/pcsx2/IPU/IPU_Fifo.cpp +++ b/pcsx2/IPU/IPU_Fifo.cpp @@ -40,7 +40,7 @@ void IPU_Fifo_Input::clear() writepos = 0; // Because the FIFO is drained it will request more data immediately - IPU1Status.DataRequested = true; + IPUCoreStatus.DataRequested = true; if (ipu1ch.chcr.STR && cpuRegs.eCycle[4] == 0x9999) { @@ -91,9 +91,7 @@ int IPU_Fifo_Input::write(const u32* pMem, int size) g_BP.IFC += transfer_size; if (g_BP.IFC == 8) - IPU1Status.DataRequested = false; - - CPU_INT(IPU_PROCESS, transfer_size * BIAS); + IPUCoreStatus.DataRequested = false; return transfer_size; } @@ -104,7 +102,7 @@ int IPU_Fifo_Input::read(void *value) if (g_BP.IFC <= 1) { // IPU FIFO is empty and DMA is waiting so lets tell the DMA we are ready to put data in the FIFO - IPU1Status.DataRequested = true; + IPUCoreStatus.DataRequested = true; if(ipu1ch.chcr.STR && cpuRegs.eCycle[4] == 0x9999) { @@ -142,7 +140,7 @@ int IPU_Fifo_Output::write(const u32 *value, uint size) ipuRegs.ctrl.OFC += transfer_size; if(ipu0ch.chcr.STR) - IPU_INT_FROM(ipuRegs.ctrl.OFC * BIAS); + IPU_INT_FROM(1); return transfer_size; } @@ -181,12 +179,13 @@ void WriteFIFO_IPUin(const mem128_t* value) IPU_LOG( "WriteFIFO/IPUin <- 0x%08X.%08X.%08X.%08X", value->_u32[0], value->_u32[1], value->_u32[2], value->_u32[3]); //committing every 16 bytes - if( ipu_fifo.in.write(value->_u32, 1) == 0 ) + if( ipu_fifo.in.write(value->_u32, 1) > 0 ) { - if (ipuRegs.ctrl.BUSY && !CommandExecuteQueued) + if (ipuRegs.ctrl.BUSY && IPUCoreStatus.WaitingOnIPUTo) { - CommandExecuteQueued = false; - CPU_INT(IPU_PROCESS, 8); + IPUCoreStatus.WaitingOnIPUFrom = false; + IPUCoreStatus.WaitingOnIPUTo = false; + CPU_INT(IPU_PROCESS, 2 * BIAS); } } } diff --git a/pcsx2/IPU/IPU_MultiISA.cpp b/pcsx2/IPU/IPU_MultiISA.cpp index 86faebf846a97..c49db385231f6 100644 --- a/pcsx2/IPU/IPU_MultiISA.cpp +++ b/pcsx2/IPU/IPU_MultiISA.cpp @@ -1010,6 +1010,7 @@ __ri static bool mpeg2sliceIDEC() // IPU0 isn't ready for data, so let's wait for it to be if ((!ipu0ch.chcr.STR || ipuRegs.ctrl.OFC || ipu0ch.qwc == 0) && ipu_cmd.pos[1] <= 2) { + IPUCoreStatus.WaitingOnIPUFrom = true; return false; } macroblock_8& mb8 = decoder.mb8; @@ -1123,6 +1124,8 @@ __ri static bool mpeg2sliceIDEC() if (ready_to_decode == true) { ready_to_decode = false; + IPUCoreStatus.WaitingOnIPUFrom = false; + IPUCoreStatus.WaitingOnIPUTo = false; CPU_INT(IPU_PROCESS, 64); // Should probably be much higher, but myst 3 doesn't like it right now. ipu_cmd.pos[1] = 2; return false; @@ -1134,6 +1137,7 @@ __ri static bool mpeg2sliceIDEC() if (decoder.ipu0_data != 0) { // IPU FIFO filled up -- Will have to finish transferring later. + IPUCoreStatus.WaitingOnIPUFrom = true; ipu_cmd.pos[1] = 2; return false; } @@ -1141,6 +1145,7 @@ __ri static bool mpeg2sliceIDEC() mbaCount = 0; if (read) { + IPUCoreStatus.WaitingOnIPUFrom = true; ipu_cmd.pos[1] = 3; return false; } @@ -1308,6 +1313,7 @@ __fi static bool mpeg2_slice() // IPU0 isn't ready for data, so let's wait for it to be if ((!ipu0ch.chcr.STR || ipuRegs.ctrl.OFC || ipu0ch.qwc == 0) && ipu_cmd.pos[0] <= 3) { + IPUCoreStatus.WaitingOnIPUFrom = true; return false; } @@ -1514,6 +1520,8 @@ __fi static bool mpeg2_slice() { ipu_cmd.pos[0] = 3; ready_to_decode = false; + IPUCoreStatus.WaitingOnIPUFrom = false; + IPUCoreStatus.WaitingOnIPUTo = false; CPU_INT(IPU_PROCESS, 64); // Should probably be much higher, but myst 3 doesn't like it right now. return false; } @@ -1525,6 +1533,7 @@ __fi static bool mpeg2_slice() if (decoder.ipu0_data != 0) { // IPU FIFO filled up -- Will have to finish transferring later. + IPUCoreStatus.WaitingOnIPUFrom = true; ipu_cmd.pos[0] = 3; return false; } @@ -1532,6 +1541,7 @@ __fi static bool mpeg2_slice() mbaCount = 0; if (read) { + IPUCoreStatus.WaitingOnIPUFrom = true; ipu_cmd.pos[0] = 4; return false; } @@ -1801,12 +1811,20 @@ __ri static bool ipuCSC(tIPU_CMD_CSC csc) if (csc.OFM) { ipu_cmd.pos[1] += ipu_fifo.out.write(((u32*) & decoder.rgb16) + 4 * ipu_cmd.pos[1], 32 - ipu_cmd.pos[1]); - if (ipu_cmd.pos[1] < 32) return false; + if (ipu_cmd.pos[1] < 32) + { + IPUCoreStatus.WaitingOnIPUFrom = true; + return false; + } } else { ipu_cmd.pos[1] += ipu_fifo.out.write(((u32*) & decoder.rgb32) + 4 * ipu_cmd.pos[1], 64 - ipu_cmd.pos[1]); - if (ipu_cmd.pos[1] < 64) return false; + if (ipu_cmd.pos[1] < 64) + { + IPUCoreStatus.WaitingOnIPUFrom = true; + return false; + } } ipu_cmd.pos[0] = 0; @@ -1834,12 +1852,20 @@ __ri static bool ipuPACK(tIPU_CMD_CSC csc) if (csc.OFM) { ipu_cmd.pos[1] += ipu_fifo.out.write(((u32*) & decoder.rgb16) + 4 * ipu_cmd.pos[1], 32 - ipu_cmd.pos[1]); - if (ipu_cmd.pos[1] < 32) return false; + if (ipu_cmd.pos[1] < 32) + { + IPUCoreStatus.WaitingOnIPUFrom = true; + return false; + } } else { ipu_cmd.pos[1] += ipu_fifo.out.write(((u32*)g_ipu_indx4) + 4 * ipu_cmd.pos[1], 8 - ipu_cmd.pos[1]); - if (ipu_cmd.pos[1] < 8) return false; + if (ipu_cmd.pos[1] < 8) + { + IPUCoreStatus.WaitingOnIPUFrom = true; + return false; + } } ipu_cmd.pos[0] = 0; diff --git a/pcsx2/IPU/IPUdma.cpp b/pcsx2/IPU/IPUdma.cpp index c3f33be299b7e..378308378270d 100644 --- a/pcsx2/IPU/IPUdma.cpp +++ b/pcsx2/IPU/IPUdma.cpp @@ -19,16 +19,12 @@ #include "IPU/IPUdma.h" #include "IPU/IPU_MultiISA.h" -IPUStatus IPU1Status; -bool CommandExecuteQueued; -u32 ProcessedData; +IPUDMAStatus IPU1Status; void ipuDmaReset() { IPU1Status.InProgress = false; IPU1Status.DMAFinished = true; - CommandExecuteQueued = false; - ProcessedData = 0; } bool SaveStateBase::ipuDmaFreeze() @@ -37,7 +33,6 @@ bool SaveStateBase::ipuDmaFreeze() return false; Freeze(IPU1Status); - Freeze(CommandExecuteQueued); return IsOkay(); } @@ -83,11 +78,18 @@ void IPU1dma() return; } - if (IPU1Status.DataRequested == false) + if (IPUCoreStatus.DataRequested == false) { // IPU isn't expecting any data, so put it in to wait mode. cpuRegs.eCycle[4] = 0x9999; CPU_SET_DMASTALL(DMAC_TO_IPU, true); + + // Shouldn't Happen. + if (IPUCoreStatus.WaitingOnIPUTo) + { + IPUCoreStatus.WaitingOnIPUTo = false; + CPU_INT(IPU_PROCESS, 4 * BIAS); + } return; } @@ -127,26 +129,22 @@ void IPU1dma() if (IPU1Status.InProgress) totalqwc += IPU1chain(); - //Do this here to prevent double settings on Chain DMA's - if((totalqwc == 0 && g_BP.IFC < 8) || (IPU1Status.DMAFinished && !IPU1Status.InProgress)) + // Nothing has been processed except maybe a tag, or the DMA is ending + if(totalqwc == 0 || (IPU1Status.DMAFinished && !IPU1Status.InProgress) || IPUCoreStatus.DataRequested) { totalqwc = std::max(4, totalqwc) + tagcycles; IPU_INT_TO(totalqwc * BIAS); } else { - IPU1Status.DataRequested = false; - - if (!(IPU1Status.DMAFinished && !IPU1Status.InProgress)) - { - cpuRegs.eCycle[4] = 0x9999;//IPU_INT_TO(2048); + cpuRegs.eCycle[4] = 0x9999; CPU_SET_DMASTALL(DMAC_TO_IPU, true); - } - else - { - totalqwc = std::max(4, totalqwc) + tagcycles; - IPU_INT_TO(totalqwc * BIAS); - } + } + + if (IPUCoreStatus.WaitingOnIPUTo && g_BP.IFC >= 1) + { + IPUCoreStatus.WaitingOnIPUTo = false; + CPU_INT(IPU_PROCESS, totalqwc * BIAS); } IPU_LOG("Completed Call IPU1 DMA QWC Remaining %x Finished %d In Progress %d tadr %x", ipu1ch.qwc, IPU1Status.DMAFinished, IPU1Status.InProgress, ipu1ch.tadr); @@ -156,8 +154,12 @@ void IPU0dma() { if(!ipuRegs.ctrl.OFC) { - if(!CommandExecuteQueued) + // This shouldn't happen. + if (IPUCoreStatus.WaitingOnIPUFrom) + { + IPUCoreStatus.WaitingOnIPUFrom = false; IPUProcessInterrupt(); + } CPU_SET_DMASTALL(DMAC_FROM_IPU, true); return; } @@ -168,6 +170,12 @@ void IPU0dma() if ((!(ipu0ch.chcr.STR) || (cpuRegs.interrupt & (1 << DMAC_FROM_IPU))) || (ipu0ch.qwc == 0)) { DevCon.Warning("How??"); + // This shouldn't happen. + if (IPUCoreStatus.WaitingOnIPUFrom) + { + IPUCoreStatus.WaitingOnIPUFrom = false; + CPU_INT(IPU_PROCESS, ipuRegs.ctrl.OFC * BIAS); + } return; } @@ -195,11 +203,12 @@ void IPU0dma() if (!ipu0ch.qwc) IPU_INT_FROM(readsize * BIAS); - if (ipuRegs.ctrl.BUSY && !CommandExecuteQueued) + CPU_SET_DMASTALL(DMAC_FROM_IPU, true); + + if (ipuRegs.ctrl.BUSY && IPUCoreStatus.WaitingOnIPUFrom) { - CommandExecuteQueued = false; - CPU_SET_DMASTALL(DMAC_FROM_IPU, true); - IPUProcessInterrupt(); + IPUCoreStatus.WaitingOnIPUFrom = false; + CPU_INT(IPU_PROCESS, readsize * BIAS); } } @@ -259,29 +268,19 @@ __fi void dmaIPU1() // toIPU IPU1Status.DMAFinished = false; } } - - if(IPU1Status.DataRequested) - IPU1dma(); - else - cpuRegs.eCycle[4] = 0x9999; } else // Normal Mode { IPU_LOG("Setting up IPU1 Normal mode"); IPU1Status.InProgress = true; IPU1Status.DMAFinished = true; - - if (IPU1Status.DataRequested) - IPU1dma(); - else - cpuRegs.eCycle[4] = 0x9999; } + + IPU1dma(); } void ipuCMDProcess() { - CommandExecuteQueued = false; - ProcessedData = 0; IPUProcessInterrupt(); } diff --git a/pcsx2/IPU/IPUdma.h b/pcsx2/IPU/IPUdma.h index 9f7db0f37e6ff..f8065af891d38 100644 --- a/pcsx2/IPU/IPUdma.h +++ b/pcsx2/IPU/IPUdma.h @@ -17,10 +17,15 @@ #include "IPU.h" -struct IPUStatus { +struct IPUDMAStatus { bool InProgress; bool DMAFinished; +}; + +struct IPUStatus { bool DataRequested; + bool WaitingOnIPUFrom; + bool WaitingOnIPUTo; }; extern void ipuCMDProcess(); @@ -33,4 +38,5 @@ extern void IPU0dma(); extern void IPU1dma(); extern void ipuDmaReset(); -extern IPUStatus IPU1Status; +extern IPUDMAStatus IPU1Status; +extern IPUStatus IPUCoreStatus; diff --git a/pcsx2/MTVU.cpp b/pcsx2/MTVU.cpp index 96727fe4c9f47..dc55ee7f8d566 100644 --- a/pcsx2/MTVU.cpp +++ b/pcsx2/MTVU.cpp @@ -400,10 +400,10 @@ void VU_Thread::Get_MTVUChanges() { mtvuInterrupts.fetch_and(~InterruptFlagFinish, std::memory_order_relaxed); GUNIT_WARN("Finish firing"); - CSRreg.FINISH = true; gifUnit.gsFINISH.gsFINISHFired = false; + gifUnit.gsFINISH.gsFINISHPending = true; - if (!gifRegs.stat.APATH) + if (!gifUnit.checkPaths(true, true, true, true)) Gif_FinishIRQ(); } if (interrupts & InterruptFlagLabel) diff --git a/pcsx2/SaveState.h b/pcsx2/SaveState.h index bb2a1228507b0..722b091671284 100644 --- a/pcsx2/SaveState.h +++ b/pcsx2/SaveState.h @@ -37,7 +37,7 @@ enum class FreezeAction // [SAVEVERSION+] // This informs the auto updater that the users savestates will be invalidated. -static const u32 g_SaveVersion = (0x9A3F << 16) | 0x0000; +static const u32 g_SaveVersion = (0x9A41 << 16) | 0x0000; // the freezing data between submodules and core diff --git a/pcsx2/Vif0_Dma.cpp b/pcsx2/Vif0_Dma.cpp index 4a52b4563eeac..26dc9f2598794 100644 --- a/pcsx2/Vif0_Dma.cpp +++ b/pcsx2/Vif0_Dma.cpp @@ -137,8 +137,15 @@ __fi void vif0SetupTransfer() __fi void vif0VUFinish() { // Sync up VU0 so we don't errantly wait. - while (static_cast(cpuRegs.cycle - VU0.cycle) > 0 && (VU0.VI[REG_VPU_STAT].UL & 0x1)) + while (VU0.VI[REG_VPU_STAT].UL & 0x1) + { + const int cycle_diff = static_cast(cpuRegs.cycle - VU0.cycle); + + if ((EmuConfig.Gamefixes.VUSyncHack && cycle_diff < VU0.nextBlockCycles) || cycle_diff <= 0) + break; + CpuVU0->ExecuteBlock(); + } if (VU0.VI[REG_VPU_STAT].UL & 0x5) { diff --git a/pcsx2/Vif1_Dma.cpp b/pcsx2/Vif1_Dma.cpp index 33472892c8c3a..73409bda7d4e1 100644 --- a/pcsx2/Vif1_Dma.cpp +++ b/pcsx2/Vif1_Dma.cpp @@ -232,8 +232,15 @@ __fi void vif1SetupTransfer() __fi void vif1VUFinish() { // Sync up VU1 so we don't errantly wait. - while (!THREAD_VU1 && static_cast(cpuRegs.cycle - VU1.cycle) > 0 && (VU0.VI[REG_VPU_STAT].UL & 0x100)) + while (!THREAD_VU1 && (VU0.VI[REG_VPU_STAT].UL & 0x100)) + { + const int cycle_diff = static_cast(cpuRegs.cycle - VU1.cycle); + + if ((EmuConfig.Gamefixes.VUSyncHack && cycle_diff < VU1.nextBlockCycles) || cycle_diff <= 0) + break; + CpuVU1->ExecuteBlock(); + } if (VU0.VI[REG_VPU_STAT].UL & 0x500) { diff --git a/pcsx2/Vif1_MFIFO.cpp b/pcsx2/Vif1_MFIFO.cpp index 8fb1300ae6b84..d477d7819d03d 100644 --- a/pcsx2/Vif1_MFIFO.cpp +++ b/pcsx2/Vif1_MFIFO.cpp @@ -300,7 +300,7 @@ void vifMFIFOInterrupt() { GUNIT_WARN("vifMFIFOInterrupt() - Waiting for Path 2 to be ready"); CPU_INT(DMAC_MFIFO_VIF, 128); - CPU_SET_DMASTALL(DMAC_VIF1, true); + CPU_SET_DMASTALL(DMAC_MFIFO_VIF, true); return; } } @@ -308,7 +308,7 @@ void vifMFIFOInterrupt() { //DevCon.Warning("Waiting on VU1 MFIFO"); CPU_INT(VIF_VU1_FINISH, std::max(16, cpuGetCycles(VU_MTVU_BUSY))); - CPU_SET_DMASTALL(DMAC_VIF1, true); + CPU_SET_DMASTALL(DMAC_MFIFO_VIF, true); return; } @@ -341,7 +341,7 @@ void vifMFIFOInterrupt() { vif1Regs.stat.VPS = VPS_DECODING; //If there's more data you need to say it's decoding the next VIF CMD (Onimusha - Blade Warriors) VIF_LOG("VIF1 MFIFO Stalled"); - CPU_SET_DMASTALL(DMAC_VIF1, true); + CPU_SET_DMASTALL(DMAC_MFIFO_VIF, true); return; } } @@ -361,7 +361,7 @@ void vifMFIFOInterrupt() if (vif1.inprogress & 0x10) { FireMFIFOEmpty(); - CPU_SET_DMASTALL(DMAC_VIF1, true); + CPU_SET_DMASTALL(DMAC_MFIFO_VIF, true); return; } @@ -412,6 +412,6 @@ void vifMFIFOInterrupt() vif1ch.chcr.STR = false; hwDmacIrq(DMAC_VIF1); DMA_LOG("VIF1 MFIFO DMA End"); - CPU_SET_DMASTALL(DMAC_VIF1, false); + CPU_SET_DMASTALL(DMAC_MFIFO_VIF, false); vif1Regs.stat.FQC = 0; } diff --git a/pcsx2/Vif_Codes.cpp b/pcsx2/Vif_Codes.cpp index 27a78e202455b..79392eab59416 100644 --- a/pcsx2/Vif_Codes.cpp +++ b/pcsx2/Vif_Codes.cpp @@ -66,6 +66,11 @@ __ri void vifExecQueue(int idx) }*/ } +static __fi EE_EventType vif1InternalIrq() +{ + return dmacRegs.ctrl.is_mfifo(true) ? DMAC_MFIFO_VIF : DMAC_VIF1; +} + static __fi void vifFlush(int idx) { vifExecQueue(idx); @@ -85,7 +90,7 @@ static __fi void vuExecMicro(int idx, u32 addr, bool requires_wait) vifFlush(idx); if (GetVifX.waitforvu) { - CPU_SET_DMASTALL(idx ? DMAC_VIF1 : DMAC_VIF0, true); + CPU_SET_DMASTALL(idx ? vif1InternalIrq() : DMAC_VIF0, true); return; } @@ -225,7 +230,7 @@ vifOp(vifCode_Flush) if (vif1.waitforvu || vif1Regs.stat.VGW) { - CPU_SET_DMASTALL(DMAC_VIF1, true); + CPU_SET_DMASTALL(vif1InternalIrq(), true); return 0; } @@ -258,7 +263,7 @@ vifOp(vifCode_FlushA) if (vif1.waitforvu || vif1Regs.stat.VGW) { - CPU_SET_DMASTALL(DMAC_VIF1, true); + CPU_SET_DMASTALL(vif1InternalIrq(), true); return 0; } @@ -279,7 +284,7 @@ vifOp(vifCode_FlushE) if (vifX.waitforvu) { - CPU_SET_DMASTALL(idx ? DMAC_VIF1 : DMAC_VIF0, true); + CPU_SET_DMASTALL(idx ? vif1InternalIrq() : DMAC_VIF0, true); return 0; } @@ -387,7 +392,7 @@ vifOp(vifCode_MPG) if (vifX.waitforvu) { - CPU_SET_DMASTALL(idx ? DMAC_VIF1 : DMAC_VIF0, true); + CPU_SET_DMASTALL(idx ? vif1InternalIrq() : DMAC_VIF0, true); return 0; } else @@ -435,7 +440,7 @@ vifOp(vifCode_MSCAL) if (vifX.waitforvu) { - CPU_SET_DMASTALL(idx ? DMAC_VIF1 : DMAC_VIF0, true); + CPU_SET_DMASTALL(idx ? vif1InternalIrq() : DMAC_VIF0, true); return 0; } @@ -474,7 +479,7 @@ vifOp(vifCode_MSCALF) if (vifX.waitforvu || vif1Regs.stat.VGW) { - CPU_SET_DMASTALL(idx ? DMAC_VIF1 : DMAC_VIF0, true); + CPU_SET_DMASTALL(idx ? vif1InternalIrq() : DMAC_VIF0, true); return 0; } @@ -496,7 +501,7 @@ vifOp(vifCode_MSCNT) if (vifX.waitforvu) { - CPU_SET_DMASTALL(idx ? DMAC_VIF1 : DMAC_VIF0, true); + CPU_SET_DMASTALL(idx ? vif1InternalIrq() : DMAC_VIF0, true); return 0; }