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Describe the bug
When in Mode 15 there are visual glitches when running under RISC OS 2.
To Reproduce
Steps to reproduce the behaviour:
Start up the emulator
Change to Mode 15
Observe on scan lines visual glitches after the line changes colour
Expected behaviour
The picture should be stable.
Please complete the following information
Current HEAD
Additional context
It's thought that the machine is taking too long to service video DMA requests.
The current thinking is that RISC OS 2 runs most of its code from ROM which at best has a 200ns documented access time. (RISC OS 3, designed to run on a faster ARM 3 which could access RAM at 42ns would benefit more from copying portions of the OS into RAM which is maybe why this issue doesn't appear to manifest under RISC OS 3).
However, when doing the initial exploration of this issue it was found that the MEMC had selected a 450ns access time, which was somewhat surprising. Forcing the MEMC to have an access time of 200ns also didn't resolve the issue.
The text was updated successfully, but these errors were encountered:
Tried an experiment with a stripped down VIDC/MEMC implementation with the 200ns ROM access time.
This appears to work okay but then that does open the question as to why there are visual glitches in the emulator even when we ignore the ROM speed settings and use a 200ns access time.
Describe the bug
When in Mode 15 there are visual glitches when running under RISC OS 2.
To Reproduce
Steps to reproduce the behaviour:
Expected behaviour
The picture should be stable.
Please complete the following information
Additional context
It's thought that the machine is taking too long to service video DMA requests.
The current thinking is that RISC OS 2 runs most of its code from ROM which at best has a 200ns documented access time. (RISC OS 3, designed to run on a faster ARM 3 which could access RAM at 42ns would benefit more from copying portions of the OS into RAM which is maybe why this issue doesn't appear to manifest under RISC OS 3).
However, when doing the initial exploration of this issue it was found that the MEMC had selected a 450ns access time, which was somewhat surprising. Forcing the MEMC to have an access time of 200ns also didn't resolve the issue.
The text was updated successfully, but these errors were encountered: