From 07249b5f1f509a29f9f11390adfa4a3b08c5cb0d Mon Sep 17 00:00:00 2001 From: Simo <136233872+Simo3ds@users.noreply.github.com> Date: Sat, 9 Mar 2024 17:56:01 +0100 Subject: [PATCH] sync to latest commit Signed-off-by: Simo <136233872+Simo3ds@users.noreply.github.com> --- arm9/source/emunand_patch.s | 8 ++--- arm9/source/itcm.h | 4 +-- arm9/source/memcpy.s | 70 +++++++++++++++++++++++++++++++++++++ 3 files changed, 76 insertions(+), 6 deletions(-) create mode 100644 arm9/source/memcpy.s diff --git a/arm9/source/emunand_patch.s b/arm9/source/emunand_patch.s index 23a49a77..8d7c637c 100644 --- a/arm9/source/emunand_patch.s +++ b/arm9/source/emunand_patch.s @@ -1,4 +1,4 @@ -.section .emunand_patch, "aw", %progbits +.section .emunand_patch, "awx", %progbits .thumb .align 2 @@ -55,9 +55,9 @@ emunandPatch: .global emunandPatchNcsdHeaderOffset .balign 4 -emunandPatchSdmmcStructPtr: .word 0 @ Indirizza alla struttura sdmmc -emunandPatchNandOffset: .word 0 @ Per la rednand, questa dovrebbe essere 1 -emunandPatchNcsdHeaderOffset: .word 0 @ Dipende dal creatore della nand + tipo di emunand (GW/RED) +emunandPatchSdmmcStructPtr: .word 0 @ Pointer to sdmmc struct +emunandPatchNandOffset: .word 0 @ For rednand this should be 1 +emunandPatchNcsdHeaderOffset: .word 0 @ Depends on nand manufacturer + emunand type (GW/RED) .pool .balign 4 diff --git a/arm9/source/itcm.h b/arm9/source/itcm.h index 38f39fe9..9e5de092 100644 --- a/arm9/source/itcm.h +++ b/arm9/source/itcm.h @@ -259,8 +259,8 @@ STATIC_ASSERT(sizeof(Arm9Itcm) == 0x8000); // Default path for the OTP is in the luma directory of SDCARD. #define OTP_PATH "sdmc:/luma/otp.bin" -void patchITCM(void); +__attribute__((section(".patchITCM"), target("arm"), aligned(16))) void patchITCM(void); #define CID_PATH "sdmc:/luma/nand_cid.bin" -void PatchITCMCid(void); +__attribute__((section(".PatchITCMCid"), target("arm"), aligned(16))) void PatchITCMCid(void); diff --git a/arm9/source/memcpy.s b/arm9/source/memcpy.s new file mode 100644 index 00000000..6a067c22 --- /dev/null +++ b/arm9/source/memcpy.s @@ -0,0 +1,70 @@ +@ memcpy_arm946e-s - hand written reimplementation of memcpy to be sequential +@ Written in 2019 by luigoalma +@ To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty. +@ For a copy of CC0 Public Domain Dedication, see . + .cpu arm946e-s + .arch armv5te + .arm + .section .text.memcpy, "ax", %progbits + .align 2 + .global memcpy + .syntax unified + .type memcpy, %function +memcpy: + @ r0 = dest + @ r1 = src + @ r2 = length + @ check if length 0 and return if so + cmp r2, #0 + bxeq lr + push {r0,r4-r9,lr} + @ pre-fetch data + pld [r1] + @ alignment check with word size + @ if not aligned but both are in the same misalignment, fix it up + @ otherwise jump to basic loop + orr r12, r0, r1 + ands r12, r12, #3 + beq .L1 + mov r12, r0, LSL#30 + cmp r12, r1, LSL#30 + bne .L6 +.L0: + ldrb r3, [r1], #1 + strb r3, [r0], #1 + subs r2, r2, #1 + popeq {r0,r4-r9,pc} + adds r12, r12, #0x40000000 + bne .L0 +.L1: + @ check if length higher than 32 + @ if so, do the 32 byte block copy loop, + @ until there's nothing left or remainder to copy is less than 32 + movs r3, r2, LSR#5 + beq .L3 +.L2: + ldm r1!, {r4-r9,r12,lr} + stm r0!, {r4-r9,r12,lr} + subs r3, r3, #1 + bne .L2 + ands r2, r2, #0x1F + popeq {r0,r4-r9,pc} +.L3: + @ copy in word size the remaining data, + @ and finish off with basic loop if can't copy all by word size. + movs r3, r2, LSR#2 + beq .L6 +.L4: + ldr r12, [r1], #4 + str r12, [r0], #4 + subs r3, r3, #1 + bne .L4 + ands r2, r2, #0x3 +.L5: @ the basic loop + popeq {r0,r4-r9,pc} +.L6: + ldrb r3, [r1], #1 + strb r3, [r0], #1 + subs r2, r2, #1 + b .L5 + .size memcpy, .-memcpy