diff --git a/systemrdl/core/ExprVisitor.py b/systemrdl/core/ExprVisitor.py
index 5d12987..91bbd71 100644
--- a/systemrdl/core/ExprVisitor.py
+++ b/systemrdl/core/ExprVisitor.py
@@ -261,6 +261,38 @@ def visitStruct_literal(self, ctx: SystemRDLParser.Struct_literalContext):
 
             values[member_name] = (member_expr, member_name_src_ref)
 
+        missing_members = set(struct_type._members.keys()) - set(values.keys())
+        undefined_members = []
+        for member_name in missing_members:
+            # 6.3.2.3.2-b: When defining struct member values, unassigned members
+            # shall receive a default value depending on their type, when available:
+            t = struct_type._members[member_name]
+            if t == bool:
+                values[member_name] = (ast.BoolLiteral(self.compiler.env, None, False), None)
+            elif t == str:
+                values[member_name] = (ast.StringLiteral(self.compiler.env, None, ""), None)
+            elif t == rdltypes.AccessType:
+                v = ast.BuiltinEnumLiteral(self.compiler.env, None, rdltypes.AccessType.rw)
+                values[member_name] = (v, None)
+            elif t == rdltypes.AddressingType:
+                v = ast.BuiltinEnumLiteral(self.compiler.env, None, rdltypes.AddressingType.regalign)
+                values[member_name] = (v, None)
+            elif isinstance(t, rdltypes.ArrayedType):
+                v = ast.ArrayLiteral(self.compiler.env, None, [])
+                values[member_name] = (v, None)
+            else:
+                undefined_members.append(member_name)
+
+        if undefined_members:
+            # 6.3.2.3.2-c: All the members from a struct instance shall be assigned
+            # a value, either explicitly or by default.
+            # Undefined struct members shall raise an error
+            self.msg.fatal(
+                "Incomplete struct literal '%s'. The following members are undefined: %s"
+                % (struct_type_name, ", ".join(undefined_members)),
+                src_ref_from_antlr(ctx.ID())
+            )
+
         expr = ast.StructLiteral(
             self.compiler.env,
             src_ref_from_antlr(ctx.ID()),
diff --git a/systemrdl/node.py b/systemrdl/node.py
index 0506da3..62fae63 100644
--- a/systemrdl/node.py
+++ b/systemrdl/node.py
@@ -937,11 +937,10 @@ def total_size(self) -> int:
         """
         assert isinstance(self.inst, comp.AddressableComponent)
         if self.is_array:
-            # Total size of arrays is technically supposed to be:
-            #   self.inst.array_stride * (self.inst.n_elements-1) + self.size
-            # However this opens up a whole slew of ugly corner cases that the
-            # spec designers may not have anticipated.
-            # Using a simplified calculation for now until someone actually cares
+            # RDL spec does not explicitly clarify this, but total size for arrays
+            # should include any additional trailing padding implied by the stride.
+            # This makes it consistent with IP-XACT.
+            # See discussion here: https://forums.accellera.org/topic/7529-interpretation-of-total-array-size-implicit-address-allocation/
             return self.array_stride * self.inst.n_elements
 
         else:
diff --git a/systemrdl/parser/SystemRDL.g4 b/systemrdl/parser/SystemRDL.g4
index 9485067..49663c6 100644
--- a/systemrdl/parser/SystemRDL.g4
+++ b/systemrdl/parser/SystemRDL.g4
@@ -173,7 +173,9 @@ boolean_literal : val=(TRUE_kw|FALSE_kw);
 array_literal : '\'' '{' '}'
               | '\'' '{' expr (',' expr )* '}';
 
-struct_literal : ID '\'' '{' struct_kv (',' struct_kv)* '}';
+struct_literal : ID '\'' '{' '}'
+               | ID '\'' '{' struct_kv (',' struct_kv)* '}';
+
 struct_kv : ID ':' expr ;
 
 enum_literal : ID '::' ID;
diff --git a/systemrdl/parser/SystemRDL.interp b/systemrdl/parser/SystemRDL.interp
index 389b56d..369625f 100644
--- a/systemrdl/parser/SystemRDL.interp
+++ b/systemrdl/parser/SystemRDL.interp
@@ -343,4 +343,4 @@ constr_inside_value
 
 
 atn:
-[4, 1, 125, 804, 2, 0, 7, 0, 2, 1, 7, 1, 2, 2, 7, 2, 2, 3, 7, 3, 2, 4, 7, 4, 2, 5, 7, 5, 2, 6, 7, 6, 2, 7, 7, 7, 2, 8, 7, 8, 2, 9, 7, 9, 2, 10, 7, 10, 2, 11, 7, 11, 2, 12, 7, 12, 2, 13, 7, 13, 2, 14, 7, 14, 2, 15, 7, 15, 2, 16, 7, 16, 2, 17, 7, 17, 2, 18, 7, 18, 2, 19, 7, 19, 2, 20, 7, 20, 2, 21, 7, 21, 2, 22, 7, 22, 2, 23, 7, 23, 2, 24, 7, 24, 2, 25, 7, 25, 2, 26, 7, 26, 2, 27, 7, 27, 2, 28, 7, 28, 2, 29, 7, 29, 2, 30, 7, 30, 2, 31, 7, 31, 2, 32, 7, 32, 2, 33, 7, 33, 2, 34, 7, 34, 2, 35, 7, 35, 2, 36, 7, 36, 2, 37, 7, 37, 2, 38, 7, 38, 2, 39, 7, 39, 2, 40, 7, 40, 2, 41, 7, 41, 2, 42, 7, 42, 2, 43, 7, 43, 2, 44, 7, 44, 2, 45, 7, 45, 2, 46, 7, 46, 2, 47, 7, 47, 2, 48, 7, 48, 2, 49, 7, 49, 2, 50, 7, 50, 2, 51, 7, 51, 2, 52, 7, 52, 2, 53, 7, 53, 2, 54, 7, 54, 2, 55, 7, 55, 2, 56, 7, 56, 2, 57, 7, 57, 2, 58, 7, 58, 2, 59, 7, 59, 2, 60, 7, 60, 2, 61, 7, 61, 2, 62, 7, 62, 2, 63, 7, 63, 2, 64, 7, 64, 2, 65, 7, 65, 2, 66, 7, 66, 2, 67, 7, 67, 2, 68, 7, 68, 2, 69, 7, 69, 2, 70, 7, 70, 2, 71, 7, 71, 2, 72, 7, 72, 2, 73, 7, 73, 2, 74, 7, 74, 2, 75, 7, 75, 2, 76, 7, 76, 2, 77, 7, 77, 2, 78, 7, 78, 2, 79, 7, 79, 2, 80, 7, 80, 2, 81, 7, 81, 2, 82, 7, 82, 2, 83, 7, 83, 2, 84, 7, 84, 1, 0, 1, 0, 1, 0, 5, 0, 174, 8, 0, 10, 0, 12, 0, 177, 9, 0, 1, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 3, 2, 192, 8, 2, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 3, 3, 199, 8, 3, 3, 3, 201, 8, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 3, 3, 208, 8, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 3, 3, 218, 8, 3, 1, 4, 3, 4, 221, 8, 4, 1, 4, 3, 4, 224, 8, 4, 1, 4, 1, 4, 1, 4, 1, 5, 1, 5, 1, 5, 1, 6, 1, 6, 1, 6, 3, 6, 235, 8, 6, 1, 6, 1, 6, 1, 7, 1, 7, 1, 7, 1, 8, 1, 8, 1, 8, 1, 8, 5, 8, 246, 8, 8, 10, 8, 12, 8, 249, 9, 8, 1, 8, 1, 8, 1, 9, 1, 9, 1, 9, 1, 9, 1, 9, 1, 9, 1, 9, 3, 9, 260, 8, 9, 1, 10, 3, 10, 263, 8, 10, 1, 10, 1, 10, 1, 10, 5, 10, 268, 8, 10, 10, 10, 12, 10, 271, 9, 10, 1, 11, 1, 11, 4, 11, 275, 8, 11, 11, 11, 12, 11, 276, 1, 11, 3, 11, 280, 8, 11, 1, 11, 3, 11, 283, 8, 11, 1, 11, 3, 11, 286, 8, 11, 1, 11, 3, 11, 289, 8, 11, 1, 11, 3, 11, 292, 8, 11, 1, 12, 1, 12, 1, 12, 1, 13, 1, 13, 1, 13, 1, 14, 1, 14, 1, 14, 1, 15, 1, 15, 1, 15, 1, 16, 1, 16, 1, 17, 1, 17, 3, 17, 310, 8, 17, 1, 18, 1, 18, 1, 19, 1, 19, 1, 19, 1, 19, 1, 19, 5, 19, 319, 8, 19, 10, 19, 12, 19, 322, 9, 19, 1, 19, 1, 19, 1, 20, 1, 20, 1, 20, 3, 20, 329, 8, 20, 1, 20, 1, 20, 3, 20, 333, 8, 20, 1, 21, 1, 21, 1, 21, 1, 21, 1, 21, 5, 21, 340, 8, 21, 10, 21, 12, 21, 343, 9, 21, 1, 21, 1, 21, 1, 22, 1, 22, 1, 22, 1, 22, 1, 22, 1, 22, 1, 23, 1, 23, 1, 23, 1, 23, 3, 23, 357, 8, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 5, 23, 398, 8, 23, 10, 23, 12, 23, 401, 9, 23, 1, 24, 1, 24, 1, 24, 1, 24, 1, 24, 1, 24, 1, 24, 1, 24, 1, 24, 3, 24, 412, 8, 24, 1, 25, 1, 25, 1, 25, 1, 25, 5, 25, 418, 8, 25, 10, 25, 12, 25, 421, 9, 25, 1, 25, 1, 25, 1, 26, 1, 26, 1, 26, 1, 26, 1, 26, 1, 27, 1, 27, 1, 27, 1, 27, 1, 28, 1, 28, 1, 28, 1, 28, 1, 28, 1, 28, 1, 28, 1, 28, 1, 28, 1, 28, 1, 28, 1, 28, 3, 28, 446, 8, 28, 1, 29, 1, 29, 3, 29, 450, 8, 29, 1, 30, 1, 30, 1, 30, 1, 30, 1, 30, 1, 30, 1, 31, 1, 31, 1, 31, 1, 31, 1, 32, 1, 32, 1, 32, 1, 33, 1, 33, 3, 33, 467, 8, 33, 1, 34, 1, 34, 3, 34, 471, 8, 34, 1, 34, 3, 34, 474, 8, 34, 1, 35, 1, 35, 1, 35, 1, 35, 1, 35, 1, 35, 1, 35, 1, 35, 1, 35, 3, 35, 485, 8, 35, 1, 36, 1, 36, 1, 36, 3, 36, 490, 8, 36, 1, 37, 1, 37, 1, 38, 1, 38, 1, 39, 1, 39, 1, 39, 1, 39, 1, 39, 1, 39, 1, 39, 1, 39, 5, 39, 504, 8, 39, 10, 39, 12, 39, 507, 9, 39, 1, 39, 1, 39, 3, 39, 511, 8, 39, 1, 40, 1, 40, 1, 40, 1, 40, 1, 40, 1, 40, 5, 40, 519, 8, 40, 10, 40, 12, 40, 522, 9, 40, 1, 40, 1, 40, 1, 41, 1, 41, 1, 41, 1, 41, 1, 42, 1, 42, 1, 42, 1, 42, 1, 43, 1, 43, 1, 44, 1, 44, 1, 45, 1, 45, 1, 46, 1, 46, 1, 47, 1, 47, 1, 48, 1, 48, 1, 48, 5, 48, 547, 8, 48, 10, 48, 12, 48, 550, 9, 48, 1, 49, 1, 49, 5, 49, 554, 8, 49, 10, 49, 12, 49, 557, 9, 49, 1, 50, 1, 50, 1, 50, 1, 50, 3, 50, 563, 8, 50, 1, 51, 3, 51, 566, 8, 51, 1, 51, 1, 51, 3, 51, 570, 8, 51, 1, 51, 1, 51, 3, 51, 574, 8, 51, 1, 51, 3, 51, 577, 8, 51, 1, 52, 1, 52, 1, 52, 1, 52, 1, 52, 1, 52, 1, 52, 1, 52, 3, 52, 587, 8, 52, 1, 53, 1, 53, 3, 53, 591, 8, 53, 1, 53, 1, 53, 3, 53, 595, 8, 53, 1, 54, 1, 54, 1, 54, 1, 54, 1, 55, 1, 55, 1, 55, 1, 56, 1, 56, 3, 56, 606, 8, 56, 1, 57, 1, 57, 1, 58, 1, 58, 1, 59, 1, 59, 1, 59, 1, 59, 1, 59, 1, 59, 4, 59, 618, 8, 59, 11, 59, 12, 59, 619, 1, 59, 1, 59, 1, 60, 1, 60, 1, 60, 1, 60, 3, 60, 628, 8, 60, 1, 61, 1, 61, 1, 61, 1, 61, 3, 61, 634, 8, 61, 1, 62, 1, 62, 1, 62, 3, 62, 639, 8, 62, 1, 63, 1, 63, 1, 63, 1, 63, 1, 63, 5, 63, 646, 8, 63, 10, 63, 12, 63, 649, 9, 63, 1, 64, 1, 64, 3, 64, 653, 8, 64, 1, 65, 1, 65, 1, 65, 1, 65, 1, 66, 1, 66, 1, 66, 1, 66, 1, 67, 1, 67, 1, 67, 1, 67, 1, 67, 1, 67, 4, 67, 669, 8, 67, 11, 67, 12, 67, 670, 1, 67, 1, 67, 1, 68, 1, 68, 1, 68, 3, 68, 678, 8, 68, 1, 68, 1, 68, 1, 68, 1, 68, 5, 68, 684, 8, 68, 10, 68, 12, 68, 687, 9, 68, 1, 68, 3, 68, 690, 8, 68, 1, 69, 1, 69, 1, 69, 1, 69, 1, 70, 3, 70, 697, 8, 70, 1, 70, 1, 70, 1, 70, 1, 70, 3, 70, 703, 8, 70, 1, 70, 1, 70, 1, 70, 1, 70, 5, 70, 709, 8, 70, 10, 70, 12, 70, 712, 9, 70, 1, 70, 1, 70, 1, 71, 1, 71, 1, 71, 3, 71, 719, 8, 71, 1, 72, 1, 72, 3, 72, 723, 8, 72, 1, 73, 1, 73, 3, 73, 727, 8, 73, 1, 73, 1, 73, 1, 73, 3, 73, 732, 8, 73, 1, 74, 1, 74, 1, 74, 1, 74, 1, 75, 1, 75, 1, 75, 1, 76, 1, 76, 1, 76, 1, 76, 5, 76, 745, 8, 76, 10, 76, 12, 76, 748, 9, 76, 1, 76, 1, 76, 1, 77, 1, 77, 1, 77, 1, 77, 3, 77, 756, 8, 77, 1, 78, 1, 78, 1, 78, 5, 78, 761, 8, 78, 10, 78, 12, 78, 764, 9, 78, 1, 79, 1, 79, 1, 79, 1, 79, 1, 80, 1, 80, 1, 80, 1, 80, 1, 81, 1, 81, 1, 81, 1, 81, 1, 81, 1, 81, 5, 81, 780, 8, 81, 10, 81, 12, 81, 783, 9, 81, 1, 81, 1, 81, 1, 82, 1, 82, 1, 82, 1, 82, 1, 83, 1, 83, 3, 83, 793, 8, 83, 1, 84, 1, 84, 1, 84, 1, 84, 1, 84, 1, 84, 1, 84, 3, 84, 802, 8, 84, 1, 84, 0, 1, 46, 85, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94, 96, 98, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 142, 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, 166, 168, 0, 24, 1, 0, 28, 29, 1, 0, 30, 34, 3, 0, 96, 99, 101, 103, 105, 107, 2, 0, 110, 110, 112, 113, 1, 0, 96, 97, 1, 0, 108, 109, 1, 0, 117, 120, 2, 0, 114, 114, 116, 116, 1, 0, 106, 107, 1, 0, 18, 20, 1, 0, 23, 26, 1, 0, 19, 20, 3, 0, 18, 18, 22, 22, 125, 125, 1, 0, 36, 37, 1, 0, 38, 44, 1, 0, 45, 47, 1, 0, 48, 56, 1, 0, 57, 59, 1, 0, 60, 61, 3, 0, 45, 46, 48, 49, 60, 61, 1, 0, 62, 66, 2, 0, 76, 76, 78, 78, 2, 0, 68, 68, 71, 71, 2, 0, 114, 114, 116, 120, 836, 0, 175, 1, 0, 0, 0, 2, 180, 1, 0, 0, 0, 4, 191, 1, 0, 0, 0, 6, 217, 1, 0, 0, 0, 8, 220, 1, 0, 0, 0, 10, 228, 1, 0, 0, 0, 12, 231, 1, 0, 0, 0, 14, 238, 1, 0, 0, 0, 16, 241, 1, 0, 0, 0, 18, 259, 1, 0, 0, 0, 20, 262, 1, 0, 0, 0, 22, 272, 1, 0, 0, 0, 24, 293, 1, 0, 0, 0, 26, 296, 1, 0, 0, 0, 28, 299, 1, 0, 0, 0, 30, 302, 1, 0, 0, 0, 32, 305, 1, 0, 0, 0, 34, 309, 1, 0, 0, 0, 36, 311, 1, 0, 0, 0, 38, 313, 1, 0, 0, 0, 40, 325, 1, 0, 0, 0, 42, 334, 1, 0, 0, 0, 44, 346, 1, 0, 0, 0, 46, 356, 1, 0, 0, 0, 48, 411, 1, 0, 0, 0, 50, 413, 1, 0, 0, 0, 52, 424, 1, 0, 0, 0, 54, 429, 1, 0, 0, 0, 56, 445, 1, 0, 0, 0, 58, 449, 1, 0, 0, 0, 60, 451, 1, 0, 0, 0, 62, 457, 1, 0, 0, 0, 64, 461, 1, 0, 0, 0, 66, 466, 1, 0, 0, 0, 68, 473, 1, 0, 0, 0, 70, 484, 1, 0, 0, 0, 72, 489, 1, 0, 0, 0, 74, 491, 1, 0, 0, 0, 76, 493, 1, 0, 0, 0, 78, 510, 1, 0, 0, 0, 80, 512, 1, 0, 0, 0, 82, 525, 1, 0, 0, 0, 84, 529, 1, 0, 0, 0, 86, 533, 1, 0, 0, 0, 88, 535, 1, 0, 0, 0, 90, 537, 1, 0, 0, 0, 92, 539, 1, 0, 0, 0, 94, 541, 1, 0, 0, 0, 96, 543, 1, 0, 0, 0, 98, 551, 1, 0, 0, 0, 100, 558, 1, 0, 0, 0, 102, 576, 1, 0, 0, 0, 104, 586, 1, 0, 0, 0, 106, 590, 1, 0, 0, 0, 108, 596, 1, 0, 0, 0, 110, 600, 1, 0, 0, 0, 112, 605, 1, 0, 0, 0, 114, 607, 1, 0, 0, 0, 116, 609, 1, 0, 0, 0, 118, 611, 1, 0, 0, 0, 120, 627, 1, 0, 0, 0, 122, 629, 1, 0, 0, 0, 124, 638, 1, 0, 0, 0, 126, 640, 1, 0, 0, 0, 128, 652, 1, 0, 0, 0, 130, 654, 1, 0, 0, 0, 132, 658, 1, 0, 0, 0, 134, 662, 1, 0, 0, 0, 136, 674, 1, 0, 0, 0, 138, 691, 1, 0, 0, 0, 140, 696, 1, 0, 0, 0, 142, 715, 1, 0, 0, 0, 144, 722, 1, 0, 0, 0, 146, 731, 1, 0, 0, 0, 148, 733, 1, 0, 0, 0, 150, 737, 1, 0, 0, 0, 152, 740, 1, 0, 0, 0, 154, 755, 1, 0, 0, 0, 156, 757, 1, 0, 0, 0, 158, 765, 1, 0, 0, 0, 160, 769, 1, 0, 0, 0, 162, 773, 1, 0, 0, 0, 164, 786, 1, 0, 0, 0, 166, 792, 1, 0, 0, 0, 168, 801, 1, 0, 0, 0, 170, 171, 3, 4, 2, 0, 171, 172, 5, 1, 0, 0, 172, 174, 1, 0, 0, 0, 173, 170, 1, 0, 0, 0, 174, 177, 1, 0, 0, 0, 175, 173, 1, 0, 0, 0, 175, 176, 1, 0, 0, 0, 176, 178, 1, 0, 0, 0, 177, 175, 1, 0, 0, 0, 178, 179, 5, 0, 0, 1, 179, 1, 1, 0, 0, 0, 180, 181, 3, 46, 23, 0, 181, 182, 5, 0, 0, 1, 182, 3, 1, 0, 0, 0, 183, 192, 3, 6, 3, 0, 184, 192, 3, 134, 67, 0, 185, 192, 3, 118, 59, 0, 186, 192, 3, 140, 70, 0, 187, 192, 3, 146, 73, 0, 188, 192, 3, 8, 4, 0, 189, 192, 3, 102, 51, 0, 190, 192, 3, 104, 52, 0, 191, 183, 1, 0, 0, 0, 191, 184, 1, 0, 0, 0, 191, 185, 1, 0, 0, 0, 191, 186, 1, 0, 0, 0, 191, 187, 1, 0, 0, 0, 191, 188, 1, 0, 0, 0, 191, 189, 1, 0, 0, 0, 191, 190, 1, 0, 0, 0, 192, 5, 1, 0, 0, 0, 193, 200, 3, 12, 6, 0, 194, 195, 3, 32, 16, 0, 195, 196, 3, 20, 10, 0, 196, 201, 1, 0, 0, 0, 197, 199, 3, 20, 10, 0, 198, 197, 1, 0, 0, 0, 198, 199, 1, 0, 0, 0, 199, 201, 1, 0, 0, 0, 200, 194, 1, 0, 0, 0, 200, 198, 1, 0, 0, 0, 201, 218, 1, 0, 0, 0, 202, 207, 3, 14, 7, 0, 203, 204, 3, 32, 16, 0, 204, 205, 3, 20, 10, 0, 205, 208, 1, 0, 0, 0, 206, 208, 3, 20, 10, 0, 207, 203, 1, 0, 0, 0, 207, 206, 1, 0, 0, 0, 208, 218, 1, 0, 0, 0, 209, 210, 3, 32, 16, 0, 210, 211, 3, 12, 6, 0, 211, 212, 3, 20, 10, 0, 212, 218, 1, 0, 0, 0, 213, 214, 3, 32, 16, 0, 214, 215, 3, 14, 7, 0, 215, 216, 3, 20, 10, 0, 216, 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659, 3, 34, 17, 0, 657, 659, 7, 22, 0, 0, 658, 656, 1, 0, 0, 0, 658, 657, 1, 0, 0, 0, 659, 129, 1, 0, 0, 0, 660, 661, 5, 72, 0, 0, 661, 662, 5, 115, 0, 0, 662, 663, 3, 46, 23, 0, 663, 131, 1, 0, 0, 0, 664, 665, 5, 71, 0, 0, 665, 666, 5, 115, 0, 0, 666, 667, 5, 70, 0, 0, 667, 133, 1, 0, 0, 0, 668, 669, 5, 73, 0, 0, 669, 670, 5, 125, 0, 0, 670, 674, 5, 2, 0, 0, 671, 672, 3, 136, 68, 0, 672, 673, 5, 1, 0, 0, 673, 675, 1, 0, 0, 0, 674, 671, 1, 0, 0, 0, 675, 676, 1, 0, 0, 0, 676, 674, 1, 0, 0, 0, 676, 677, 1, 0, 0, 0, 677, 678, 1, 0, 0, 0, 678, 679, 5, 3, 0, 0, 679, 135, 1, 0, 0, 0, 680, 683, 5, 125, 0, 0, 681, 682, 5, 115, 0, 0, 682, 684, 3, 46, 23, 0, 683, 681, 1, 0, 0, 0, 683, 684, 1, 0, 0, 0, 684, 695, 1, 0, 0, 0, 685, 691, 5, 2, 0, 0, 686, 687, 3, 138, 69, 0, 687, 688, 5, 1, 0, 0, 688, 690, 1, 0, 0, 0, 689, 686, 1, 0, 0, 0, 690, 693, 1, 0, 0, 0, 691, 689, 1, 0, 0, 0, 691, 692, 1, 0, 0, 0, 692, 694, 1, 0, 0, 0, 693, 691, 1, 0, 0, 0, 694, 696, 5, 3, 0, 0, 695, 685, 1, 0, 0, 0, 695, 696, 1, 0, 0, 0, 696, 137, 1, 0, 0, 0, 697, 698, 5, 125, 0, 0, 698, 699, 5, 115, 0, 0, 699, 700, 3, 46, 23, 0, 700, 139, 1, 0, 0, 0, 701, 703, 5, 67, 0, 0, 702, 701, 1, 0, 0, 0, 702, 703, 1, 0, 0, 0, 703, 704, 1, 0, 0, 0, 704, 705, 5, 79, 0, 0, 705, 708, 5, 125, 0, 0, 706, 707, 5, 10, 0, 0, 707, 709, 5, 125, 0, 0, 708, 706, 1, 0, 0, 0, 708, 709, 1, 0, 0, 0, 709, 710, 1, 0, 0, 0, 710, 716, 5, 2, 0, 0, 711, 712, 3, 142, 71, 0, 712, 713, 5, 1, 0, 0, 713, 715, 1, 0, 0, 0, 714, 711, 1, 0, 0, 0, 715, 718, 1, 0, 0, 0, 716, 714, 1, 0, 0, 0, 716, 717, 1, 0, 0, 0, 717, 719, 1, 0, 0, 0, 718, 716, 1, 0, 0, 0, 719, 720, 5, 3, 0, 0, 720, 141, 1, 0, 0, 0, 721, 722, 3, 144, 72, 0, 722, 724, 5, 125, 0, 0, 723, 725, 3, 64, 32, 0, 724, 723, 1, 0, 0, 0, 724, 725, 1, 0, 0, 0, 725, 143, 1, 0, 0, 0, 726, 729, 3, 66, 33, 0, 727, 729, 3, 34, 17, 0, 728, 726, 1, 0, 0, 0, 728, 727, 1, 0, 0, 0, 729, 145, 1, 0, 0, 0, 730, 732, 3, 148, 74, 0, 731, 733, 3, 156, 78, 0, 732, 731, 1, 0, 0, 0, 732, 733, 1, 0, 0, 0, 733, 738, 1, 0, 0, 0, 734, 735, 3, 150, 75, 0, 735, 736, 3, 156, 78, 0, 736, 738, 1, 0, 0, 0, 737, 730, 1, 0, 0, 0, 737, 734, 1, 0, 0, 0, 738, 147, 1, 0, 0, 0, 739, 740, 5, 71, 0, 0, 740, 741, 5, 125, 0, 0, 741, 742, 3, 152, 76, 0, 742, 149, 1, 0, 0, 0, 743, 744, 5, 71, 0, 0, 744, 745, 3, 152, 76, 0, 745, 151, 1, 0, 0, 0, 746, 752, 5, 2, 0, 0, 747, 748, 3, 154, 77, 0, 748, 749, 5, 1, 0, 0, 749, 751, 1, 0, 0, 0, 750, 747, 1, 0, 0, 0, 751, 754, 1, 0, 0, 0, 752, 750, 1, 0, 0, 0, 752, 753, 1, 0, 0, 0, 753, 755, 1, 0, 0, 0, 754, 752, 1, 0, 0, 0, 755, 756, 5, 3, 0, 0, 756, 153, 1, 0, 0, 0, 757, 762, 3, 158, 79, 0, 758, 762, 3, 160, 80, 0, 759, 762, 3, 162, 81, 0, 760, 762, 3, 164, 82, 0, 761, 757, 1, 0, 0, 0, 761, 758, 1, 0, 0, 0, 761, 759, 1, 0, 0, 0, 761, 760, 1, 0, 0, 0, 762, 155, 1, 0, 0, 0, 763, 768, 5, 125, 0, 0, 764, 765, 5, 4, 0, 0, 765, 767, 5, 125, 0, 0, 766, 764, 1, 0, 0, 0, 767, 770, 1, 0, 0, 0, 768, 766, 1, 0, 0, 0, 768, 769, 1, 0, 0, 0, 769, 157, 1, 0, 0, 0, 770, 768, 1, 0, 0, 0, 771, 772, 3, 46, 23, 0, 772, 773, 7, 23, 0, 0, 773, 774, 3, 46, 23, 0, 774, 159, 1, 0, 0, 0, 775, 776, 5, 125, 0, 0, 776, 777, 5, 115, 0, 0, 777, 778, 3, 46, 23, 0, 778, 161, 1, 0, 0, 0, 779, 780, 3, 166, 83, 0, 780, 781, 5, 75, 0, 0, 781, 782, 5, 2, 0, 0, 782, 787, 3, 168, 84, 0, 783, 784, 5, 4, 0, 0, 784, 786, 3, 168, 84, 0, 785, 783, 1, 0, 0, 0, 786, 789, 1, 0, 0, 0, 787, 785, 1, 0, 0, 0, 787, 788, 1, 0, 0, 0, 788, 790, 1, 0, 0, 0, 789, 787, 1, 0, 0, 0, 790, 791, 5, 3, 0, 0, 791, 163, 1, 0, 0, 0, 792, 793, 3, 166, 83, 0, 793, 794, 5, 75, 0, 0, 794, 795, 5, 125, 0, 0, 795, 165, 1, 0, 0, 0, 796, 799, 5, 80, 0, 0, 797, 799, 3, 96, 48, 0, 798, 796, 1, 0, 0, 0, 798, 797, 1, 0, 0, 0, 799, 167, 1, 0, 0, 0, 800, 808, 3, 46, 23, 0, 801, 802, 5, 12, 0, 0, 802, 803, 3, 46, 23, 0, 803, 804, 5, 10, 0, 0, 804, 805, 3, 46, 23, 0, 805, 806, 5, 13, 0, 0, 806, 808, 1, 0, 0, 0, 807, 800, 1, 0, 0, 0, 807, 801, 1, 0, 0, 0, 808, 169, 1, 0, 0, 0, 74, 175, 191, 198, 200, 207, 217, 220, 223, 234, 247, 259, 262, 269, 276, 279, 282, 285, 288, 291, 309, 320, 328, 332, 341, 356, 397, 399, 411, 419, 445, 449, 466, 470, 473, 484, 489, 505, 510, 524, 529, 554, 561, 568, 571, 575, 579, 582, 592, 596, 600, 611, 625, 633, 639, 644, 653, 658, 676, 683, 691, 695, 702, 708, 716, 724, 728, 732, 737, 752, 761, 768, 787, 798, 807]
\ No newline at end of file
diff --git a/systemrdl/parser/SystemRDLParser.py b/systemrdl/parser/SystemRDLParser.py
index 38add32..05c02b5 100644
--- a/systemrdl/parser/SystemRDLParser.py
+++ b/systemrdl/parser/SystemRDLParser.py
@@ -10,7 +10,7 @@
 
 def serializedATN():
     return [
-        4,1,125,804,2,0,7,0,2,1,7,1,2,2,7,2,2,3,7,3,2,4,7,4,2,5,7,5,2,6,
+        4,1,125,810,2,0,7,0,2,1,7,1,2,2,7,2,2,3,7,3,2,4,7,4,2,5,7,5,2,6,
         7,6,2,7,7,7,2,8,7,8,2,9,7,9,2,10,7,10,2,11,7,11,2,12,7,12,2,13,7,
         13,2,14,7,14,2,15,7,15,2,16,7,16,2,17,7,17,2,18,7,18,2,19,7,19,2,
         20,7,20,2,21,7,21,2,22,7,22,2,23,7,23,2,24,7,24,2,25,7,25,2,26,7,
@@ -51,259 +51,262 @@ def serializedATN():
         1,35,1,35,1,35,1,35,1,35,1,35,1,35,3,35,485,8,35,1,36,1,36,1,36,
         3,36,490,8,36,1,37,1,37,1,38,1,38,1,39,1,39,1,39,1,39,1,39,1,39,
         1,39,1,39,5,39,504,8,39,10,39,12,39,507,9,39,1,39,1,39,3,39,511,
-        8,39,1,40,1,40,1,40,1,40,1,40,1,40,5,40,519,8,40,10,40,12,40,522,
-        9,40,1,40,1,40,1,41,1,41,1,41,1,41,1,42,1,42,1,42,1,42,1,43,1,43,
-        1,44,1,44,1,45,1,45,1,46,1,46,1,47,1,47,1,48,1,48,1,48,5,48,547,
-        8,48,10,48,12,48,550,9,48,1,49,1,49,5,49,554,8,49,10,49,12,49,557,
-        9,49,1,50,1,50,1,50,1,50,3,50,563,8,50,1,51,3,51,566,8,51,1,51,1,
-        51,3,51,570,8,51,1,51,1,51,3,51,574,8,51,1,51,3,51,577,8,51,1,52,
-        1,52,1,52,1,52,1,52,1,52,1,52,1,52,3,52,587,8,52,1,53,1,53,3,53,
-        591,8,53,1,53,1,53,3,53,595,8,53,1,54,1,54,1,54,1,54,1,55,1,55,1,
-        55,1,56,1,56,3,56,606,8,56,1,57,1,57,1,58,1,58,1,59,1,59,1,59,1,
-        59,1,59,1,59,4,59,618,8,59,11,59,12,59,619,1,59,1,59,1,60,1,60,1,
-        60,1,60,3,60,628,8,60,1,61,1,61,1,61,1,61,3,61,634,8,61,1,62,1,62,
-        1,62,3,62,639,8,62,1,63,1,63,1,63,1,63,1,63,5,63,646,8,63,10,63,
-        12,63,649,9,63,1,64,1,64,3,64,653,8,64,1,65,1,65,1,65,1,65,1,66,
-        1,66,1,66,1,66,1,67,1,67,1,67,1,67,1,67,1,67,4,67,669,8,67,11,67,
-        12,67,670,1,67,1,67,1,68,1,68,1,68,3,68,678,8,68,1,68,1,68,1,68,
-        1,68,5,68,684,8,68,10,68,12,68,687,9,68,1,68,3,68,690,8,68,1,69,
-        1,69,1,69,1,69,1,70,3,70,697,8,70,1,70,1,70,1,70,1,70,3,70,703,8,
-        70,1,70,1,70,1,70,1,70,5,70,709,8,70,10,70,12,70,712,9,70,1,70,1,
-        70,1,71,1,71,1,71,3,71,719,8,71,1,72,1,72,3,72,723,8,72,1,73,1,73,
-        3,73,727,8,73,1,73,1,73,1,73,3,73,732,8,73,1,74,1,74,1,74,1,74,1,
-        75,1,75,1,75,1,76,1,76,1,76,1,76,5,76,745,8,76,10,76,12,76,748,9,
-        76,1,76,1,76,1,77,1,77,1,77,1,77,3,77,756,8,77,1,78,1,78,1,78,5,
-        78,761,8,78,10,78,12,78,764,9,78,1,79,1,79,1,79,1,79,1,80,1,80,1,
-        80,1,80,1,81,1,81,1,81,1,81,1,81,1,81,5,81,780,8,81,10,81,12,81,
-        783,9,81,1,81,1,81,1,82,1,82,1,82,1,82,1,83,1,83,3,83,793,8,83,1,
-        84,1,84,1,84,1,84,1,84,1,84,1,84,3,84,802,8,84,1,84,0,1,46,85,0,
-        2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,
-        48,50,52,54,56,58,60,62,64,66,68,70,72,74,76,78,80,82,84,86,88,90,
-        92,94,96,98,100,102,104,106,108,110,112,114,116,118,120,122,124,
-        126,128,130,132,134,136,138,140,142,144,146,148,150,152,154,156,
-        158,160,162,164,166,168,0,24,1,0,28,29,1,0,30,34,3,0,96,99,101,103,
-        105,107,2,0,110,110,112,113,1,0,96,97,1,0,108,109,1,0,117,120,2,
-        0,114,114,116,116,1,0,106,107,1,0,18,20,1,0,23,26,1,0,19,20,3,0,
-        18,18,22,22,125,125,1,0,36,37,1,0,38,44,1,0,45,47,1,0,48,56,1,0,
-        57,59,1,0,60,61,3,0,45,46,48,49,60,61,1,0,62,66,2,0,76,76,78,78,
-        2,0,68,68,71,71,2,0,114,114,116,120,836,0,175,1,0,0,0,2,180,1,0,
-        0,0,4,191,1,0,0,0,6,217,1,0,0,0,8,220,1,0,0,0,10,228,1,0,0,0,12,
-        231,1,0,0,0,14,238,1,0,0,0,16,241,1,0,0,0,18,259,1,0,0,0,20,262,
-        1,0,0,0,22,272,1,0,0,0,24,293,1,0,0,0,26,296,1,0,0,0,28,299,1,0,
-        0,0,30,302,1,0,0,0,32,305,1,0,0,0,34,309,1,0,0,0,36,311,1,0,0,0,
-        38,313,1,0,0,0,40,325,1,0,0,0,42,334,1,0,0,0,44,346,1,0,0,0,46,356,
-        1,0,0,0,48,411,1,0,0,0,50,413,1,0,0,0,52,424,1,0,0,0,54,429,1,0,
-        0,0,56,445,1,0,0,0,58,449,1,0,0,0,60,451,1,0,0,0,62,457,1,0,0,0,
-        64,461,1,0,0,0,66,466,1,0,0,0,68,473,1,0,0,0,70,484,1,0,0,0,72,489,
-        1,0,0,0,74,491,1,0,0,0,76,493,1,0,0,0,78,510,1,0,0,0,80,512,1,0,
-        0,0,82,525,1,0,0,0,84,529,1,0,0,0,86,533,1,0,0,0,88,535,1,0,0,0,
-        90,537,1,0,0,0,92,539,1,0,0,0,94,541,1,0,0,0,96,543,1,0,0,0,98,551,
-        1,0,0,0,100,558,1,0,0,0,102,576,1,0,0,0,104,586,1,0,0,0,106,590,
-        1,0,0,0,108,596,1,0,0,0,110,600,1,0,0,0,112,605,1,0,0,0,114,607,
-        1,0,0,0,116,609,1,0,0,0,118,611,1,0,0,0,120,627,1,0,0,0,122,629,
-        1,0,0,0,124,638,1,0,0,0,126,640,1,0,0,0,128,652,1,0,0,0,130,654,
-        1,0,0,0,132,658,1,0,0,0,134,662,1,0,0,0,136,674,1,0,0,0,138,691,
-        1,0,0,0,140,696,1,0,0,0,142,715,1,0,0,0,144,722,1,0,0,0,146,731,
-        1,0,0,0,148,733,1,0,0,0,150,737,1,0,0,0,152,740,1,0,0,0,154,755,
-        1,0,0,0,156,757,1,0,0,0,158,765,1,0,0,0,160,769,1,0,0,0,162,773,
-        1,0,0,0,164,786,1,0,0,0,166,792,1,0,0,0,168,801,1,0,0,0,170,171,
-        3,4,2,0,171,172,5,1,0,0,172,174,1,0,0,0,173,170,1,0,0,0,174,177,
-        1,0,0,0,175,173,1,0,0,0,175,176,1,0,0,0,176,178,1,0,0,0,177,175,
-        1,0,0,0,178,179,5,0,0,1,179,1,1,0,0,0,180,181,3,46,23,0,181,182,
-        5,0,0,1,182,3,1,0,0,0,183,192,3,6,3,0,184,192,3,134,67,0,185,192,
-        3,118,59,0,186,192,3,140,70,0,187,192,3,146,73,0,188,192,3,8,4,0,
-        189,192,3,102,51,0,190,192,3,104,52,0,191,183,1,0,0,0,191,184,1,
-        0,0,0,191,185,1,0,0,0,191,186,1,0,0,0,191,187,1,0,0,0,191,188,1,
-        0,0,0,191,189,1,0,0,0,191,190,1,0,0,0,192,5,1,0,0,0,193,200,3,12,
-        6,0,194,195,3,32,16,0,195,196,3,20,10,0,196,201,1,0,0,0,197,199,
-        3,20,10,0,198,197,1,0,0,0,198,199,1,0,0,0,199,201,1,0,0,0,200,194,
-        1,0,0,0,200,198,1,0,0,0,201,218,1,0,0,0,202,207,3,14,7,0,203,204,
-        3,32,16,0,204,205,3,20,10,0,205,208,1,0,0,0,206,208,3,20,10,0,207,
-        203,1,0,0,0,207,206,1,0,0,0,208,218,1,0,0,0,209,210,3,32,16,0,210,
-        211,3,12,6,0,211,212,3,20,10,0,212,218,1,0,0,0,213,214,3,32,16,0,
-        214,215,3,14,7,0,215,216,3,20,10,0,216,218,1,0,0,0,217,193,1,0,0,
-        0,217,202,1,0,0,0,217,209,1,0,0,0,217,213,1,0,0,0,218,7,1,0,0,0,
-        219,221,3,32,16,0,220,219,1,0,0,0,220,221,1,0,0,0,221,223,1,0,0,
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+        1,0,0,0,421,419,1,0,0,0,422,423,5,3,0,0,423,51,1,0,0,0,424,425,5,
+        2,0,0,425,426,3,46,23,0,426,427,3,50,25,0,427,428,5,3,0,0,428,53,
+        1,0,0,0,429,430,5,6,0,0,430,431,3,46,23,0,431,432,5,7,0,0,432,55,
+        1,0,0,0,433,434,7,9,0,0,434,435,5,11,0,0,435,436,5,6,0,0,436,437,
+        3,46,23,0,437,438,5,7,0,0,438,446,1,0,0,0,439,440,3,58,29,0,440,
+        441,5,11,0,0,441,442,5,6,0,0,442,443,3,46,23,0,443,444,5,7,0,0,444,
+        446,1,0,0,0,445,433,1,0,0,0,445,439,1,0,0,0,446,57,1,0,0,0,447,450,
+        3,70,35,0,448,450,3,54,27,0,449,447,1,0,0,0,449,448,1,0,0,0,450,
+        59,1,0,0,0,451,452,5,12,0,0,452,453,3,46,23,0,453,454,5,10,0,0,454,
+        455,3,46,23,0,455,456,5,13,0,0,456,61,1,0,0,0,457,458,5,12,0,0,458,
+        459,3,46,23,0,459,460,5,13,0,0,460,63,1,0,0,0,461,462,5,12,0,0,462,
+        463,5,13,0,0,463,65,1,0,0,0,464,467,3,68,34,0,465,467,7,10,0,0,466,
+        464,1,0,0,0,466,465,1,0,0,0,467,67,1,0,0,0,468,470,7,11,0,0,469,
+        471,5,21,0,0,470,469,1,0,0,0,470,471,1,0,0,0,471,474,1,0,0,0,472,
+        474,7,12,0,0,473,468,1,0,0,0,473,472,1,0,0,0,474,69,1,0,0,0,475,
+        485,3,72,36,0,476,485,3,74,37,0,477,485,3,76,38,0,478,485,3,86,43,
+        0,479,485,3,88,44,0,480,485,3,90,45,0,481,485,3,92,46,0,482,485,
+        3,94,47,0,483,485,3,84,42,0,484,475,1,0,0,0,484,476,1,0,0,0,484,
+        477,1,0,0,0,484,478,1,0,0,0,484,479,1,0,0,0,484,480,1,0,0,0,484,
+        481,1,0,0,0,484,482,1,0,0,0,484,483,1,0,0,0,485,71,1,0,0,0,486,490,
+        5,92,0,0,487,490,5,93,0,0,488,490,5,94,0,0,489,486,1,0,0,0,489,487,
+        1,0,0,0,489,488,1,0,0,0,490,73,1,0,0,0,491,492,5,95,0,0,492,75,1,
+        0,0,0,493,494,7,13,0,0,494,77,1,0,0,0,495,496,5,11,0,0,496,497,5,
+        2,0,0,497,511,5,3,0,0,498,499,5,11,0,0,499,500,5,2,0,0,500,505,3,
+        46,23,0,501,502,5,4,0,0,502,504,3,46,23,0,503,501,1,0,0,0,504,507,
+        1,0,0,0,505,503,1,0,0,0,505,506,1,0,0,0,506,508,1,0,0,0,507,505,
+        1,0,0,0,508,509,5,3,0,0,509,511,1,0,0,0,510,495,1,0,0,0,510,498,
+        1,0,0,0,511,79,1,0,0,0,512,513,5,125,0,0,513,514,5,11,0,0,514,515,
+        5,2,0,0,515,530,5,3,0,0,516,517,5,125,0,0,517,518,5,11,0,0,518,519,
+        5,2,0,0,519,524,3,82,41,0,520,521,5,4,0,0,521,523,3,82,41,0,522,
+        520,1,0,0,0,523,526,1,0,0,0,524,522,1,0,0,0,524,525,1,0,0,0,525,
+        527,1,0,0,0,526,524,1,0,0,0,527,528,5,3,0,0,528,530,1,0,0,0,529,
+        512,1,0,0,0,529,516,1,0,0,0,530,81,1,0,0,0,531,532,5,125,0,0,532,
+        533,5,10,0,0,533,534,3,46,23,0,534,83,1,0,0,0,535,536,5,125,0,0,
+        536,537,5,14,0,0,537,538,5,125,0,0,538,85,1,0,0,0,539,540,7,14,0,
+        0,540,87,1,0,0,0,541,542,7,15,0,0,542,89,1,0,0,0,543,544,7,16,0,
+        0,544,91,1,0,0,0,545,546,7,17,0,0,546,93,1,0,0,0,547,548,7,18,0,
+        0,548,95,1,0,0,0,549,554,3,98,49,0,550,551,5,8,0,0,551,553,3,98,
+        49,0,552,550,1,0,0,0,553,556,1,0,0,0,554,552,1,0,0,0,554,555,1,0,
+        0,0,555,97,1,0,0,0,556,554,1,0,0,0,557,561,5,125,0,0,558,560,3,62,
+        31,0,559,558,1,0,0,0,560,563,1,0,0,0,561,559,1,0,0,0,561,562,1,0,
+        0,0,562,99,1,0,0,0,563,561,1,0,0,0,564,565,3,96,48,0,565,568,5,15,
+        0,0,566,569,3,114,57,0,567,569,5,125,0,0,568,566,1,0,0,0,568,567,
+        1,0,0,0,569,101,1,0,0,0,570,572,5,72,0,0,571,570,1,0,0,0,571,572,
+        1,0,0,0,572,573,1,0,0,0,573,583,3,106,53,0,574,576,5,72,0,0,575,
+        574,1,0,0,0,575,576,1,0,0,0,576,577,1,0,0,0,577,583,3,108,54,0,578,
+        580,5,72,0,0,579,578,1,0,0,0,579,580,1,0,0,0,580,581,1,0,0,0,581,
+        583,3,110,55,0,582,571,1,0,0,0,582,575,1,0,0,0,582,579,1,0,0,0,583,
+        103,1,0,0,0,584,585,3,96,48,0,585,586,5,15,0,0,586,587,3,106,53,
+        0,587,593,1,0,0,0,588,589,3,96,48,0,589,590,5,15,0,0,590,591,3,108,
+        54,0,591,593,1,0,0,0,592,584,1,0,0,0,592,588,1,0,0,0,593,105,1,0,
+        0,0,594,597,3,114,57,0,595,597,5,125,0,0,596,594,1,0,0,0,596,595,
+        1,0,0,0,597,600,1,0,0,0,598,599,5,115,0,0,599,601,3,112,56,0,600,
+        598,1,0,0,0,600,601,1,0,0,0,601,107,1,0,0,0,602,603,5,74,0,0,603,
+        604,5,115,0,0,604,605,5,125,0,0,605,109,1,0,0,0,606,607,3,116,58,
+        0,607,608,5,125,0,0,608,111,1,0,0,0,609,612,3,94,47,0,610,612,3,
+        46,23,0,611,609,1,0,0,0,611,610,1,0,0,0,612,113,1,0,0,0,613,614,
+        7,19,0,0,614,115,1,0,0,0,615,616,7,20,0,0,616,117,1,0,0,0,617,618,
+        5,77,0,0,618,619,5,125,0,0,619,623,5,2,0,0,620,621,3,120,60,0,621,
+        622,5,1,0,0,622,624,1,0,0,0,623,620,1,0,0,0,624,625,1,0,0,0,625,
+        623,1,0,0,0,625,626,1,0,0,0,626,627,1,0,0,0,627,628,5,3,0,0,628,
+        119,1,0,0,0,629,634,3,122,61,0,630,634,3,126,63,0,631,634,3,130,
+        65,0,632,634,3,132,66,0,633,629,1,0,0,0,633,630,1,0,0,0,633,631,
+        1,0,0,0,633,632,1,0,0,0,634,121,1,0,0,0,635,636,5,81,0,0,636,637,
+        5,115,0,0,637,639,3,124,62,0,638,640,3,64,32,0,639,638,1,0,0,0,639,
+        640,1,0,0,0,640,123,1,0,0,0,641,645,3,36,18,0,642,645,7,21,0,0,643,
+        645,3,68,34,0,644,641,1,0,0,0,644,642,1,0,0,0,644,643,1,0,0,0,645,
+        125,1,0,0,0,646,647,5,69,0,0,647,648,5,115,0,0,648,653,3,128,64,
+        0,649,650,5,103,0,0,650,652,3,128,64,0,651,649,1,0,0,0,652,655,1,
+        0,0,0,653,651,1,0,0,0,653,654,1,0,0,0,654,127,1,0,0,0,655,653,1,
+        0,0,0,656,659,3,34,17,0,657,659,7,22,0,0,658,656,1,0,0,0,658,657,
+        1,0,0,0,659,129,1,0,0,0,660,661,5,72,0,0,661,662,5,115,0,0,662,663,
+        3,46,23,0,663,131,1,0,0,0,664,665,5,71,0,0,665,666,5,115,0,0,666,
+        667,5,70,0,0,667,133,1,0,0,0,668,669,5,73,0,0,669,670,5,125,0,0,
+        670,674,5,2,0,0,671,672,3,136,68,0,672,673,5,1,0,0,673,675,1,0,0,
+        0,674,671,1,0,0,0,675,676,1,0,0,0,676,674,1,0,0,0,676,677,1,0,0,
+        0,677,678,1,0,0,0,678,679,5,3,0,0,679,135,1,0,0,0,680,683,5,125,
+        0,0,681,682,5,115,0,0,682,684,3,46,23,0,683,681,1,0,0,0,683,684,
+        1,0,0,0,684,695,1,0,0,0,685,691,5,2,0,0,686,687,3,138,69,0,687,688,
+        5,1,0,0,688,690,1,0,0,0,689,686,1,0,0,0,690,693,1,0,0,0,691,689,
+        1,0,0,0,691,692,1,0,0,0,692,694,1,0,0,0,693,691,1,0,0,0,694,696,
+        5,3,0,0,695,685,1,0,0,0,695,696,1,0,0,0,696,137,1,0,0,0,697,698,
+        5,125,0,0,698,699,5,115,0,0,699,700,3,46,23,0,700,139,1,0,0,0,701,
+        703,5,67,0,0,702,701,1,0,0,0,702,703,1,0,0,0,703,704,1,0,0,0,704,
+        705,5,79,0,0,705,708,5,125,0,0,706,707,5,10,0,0,707,709,5,125,0,
+        0,708,706,1,0,0,0,708,709,1,0,0,0,709,710,1,0,0,0,710,716,5,2,0,
+        0,711,712,3,142,71,0,712,713,5,1,0,0,713,715,1,0,0,0,714,711,1,0,
+        0,0,715,718,1,0,0,0,716,714,1,0,0,0,716,717,1,0,0,0,717,719,1,0,
+        0,0,718,716,1,0,0,0,719,720,5,3,0,0,720,141,1,0,0,0,721,722,3,144,
+        72,0,722,724,5,125,0,0,723,725,3,64,32,0,724,723,1,0,0,0,724,725,
+        1,0,0,0,725,143,1,0,0,0,726,729,3,66,33,0,727,729,3,34,17,0,728,
+        726,1,0,0,0,728,727,1,0,0,0,729,145,1,0,0,0,730,732,3,148,74,0,731,
+        733,3,156,78,0,732,731,1,0,0,0,732,733,1,0,0,0,733,738,1,0,0,0,734,
+        735,3,150,75,0,735,736,3,156,78,0,736,738,1,0,0,0,737,730,1,0,0,
+        0,737,734,1,0,0,0,738,147,1,0,0,0,739,740,5,71,0,0,740,741,5,125,
+        0,0,741,742,3,152,76,0,742,149,1,0,0,0,743,744,5,71,0,0,744,745,
+        3,152,76,0,745,151,1,0,0,0,746,752,5,2,0,0,747,748,3,154,77,0,748,
+        749,5,1,0,0,749,751,1,0,0,0,750,747,1,0,0,0,751,754,1,0,0,0,752,
+        750,1,0,0,0,752,753,1,0,0,0,753,755,1,0,0,0,754,752,1,0,0,0,755,
+        756,5,3,0,0,756,153,1,0,0,0,757,762,3,158,79,0,758,762,3,160,80,
+        0,759,762,3,162,81,0,760,762,3,164,82,0,761,757,1,0,0,0,761,758,
+        1,0,0,0,761,759,1,0,0,0,761,760,1,0,0,0,762,155,1,0,0,0,763,768,
+        5,125,0,0,764,765,5,4,0,0,765,767,5,125,0,0,766,764,1,0,0,0,767,
+        770,1,0,0,0,768,766,1,0,0,0,768,769,1,0,0,0,769,157,1,0,0,0,770,
+        768,1,0,0,0,771,772,3,46,23,0,772,773,7,23,0,0,773,774,3,46,23,0,
+        774,159,1,0,0,0,775,776,5,125,0,0,776,777,5,115,0,0,777,778,3,46,
+        23,0,778,161,1,0,0,0,779,780,3,166,83,0,780,781,5,75,0,0,781,782,
+        5,2,0,0,782,787,3,168,84,0,783,784,5,4,0,0,784,786,3,168,84,0,785,
+        783,1,0,0,0,786,789,1,0,0,0,787,785,1,0,0,0,787,788,1,0,0,0,788,
+        790,1,0,0,0,789,787,1,0,0,0,790,791,5,3,0,0,791,163,1,0,0,0,792,
+        793,3,166,83,0,793,794,5,75,0,0,794,795,5,125,0,0,795,165,1,0,0,
+        0,796,799,5,80,0,0,797,799,3,96,48,0,798,796,1,0,0,0,798,797,1,0,
+        0,0,799,167,1,0,0,0,800,808,3,46,23,0,801,802,5,12,0,0,802,803,3,
+        46,23,0,803,804,5,10,0,0,804,805,3,46,23,0,805,806,5,13,0,0,806,
+        808,1,0,0,0,807,800,1,0,0,0,807,801,1,0,0,0,808,169,1,0,0,0,74,175,
+        191,198,200,207,217,220,223,234,247,259,262,269,276,279,282,285,
+        288,291,309,320,328,332,341,356,397,399,411,419,445,449,466,470,
+        473,484,489,505,510,524,529,554,561,568,571,575,579,582,592,596,
+        600,611,625,633,639,644,653,658,676,683,691,695,702,708,716,724,
+        728,732,737,752,761,768,787,798,807
     ]
 
 class SystemRDLParser ( Parser ):
@@ -3735,29 +3738,48 @@ def struct_literal(self):
         self.enterRule(localctx, 80, self.RULE_struct_literal)
         self._la = 0 # Token type
         try:
-            self.enterOuterAlt(localctx, 1)
-            self.state = 512
-            self.match(SystemRDLParser.ID)
-            self.state = 513
-            self.match(SystemRDLParser.T__10)
-            self.state = 514
-            self.match(SystemRDLParser.T__1)
-            self.state = 515
-            self.struct_kv()
-            self.state = 520
+            self.state = 529
             self._errHandler.sync(self)
-            _la = self._input.LA(1)
-            while _la==4:
+            la_ = self._interp.adaptivePredict(self._input,39,self._ctx)
+            if la_ == 1:
+                self.enterOuterAlt(localctx, 1)
+                self.state = 512
+                self.match(SystemRDLParser.ID)
+                self.state = 513
+                self.match(SystemRDLParser.T__10)
+                self.state = 514
+                self.match(SystemRDLParser.T__1)
+                self.state = 515
+                self.match(SystemRDLParser.T__2)
+                pass
+
+            elif la_ == 2:
+                self.enterOuterAlt(localctx, 2)
                 self.state = 516
-                self.match(SystemRDLParser.T__3)
+                self.match(SystemRDLParser.ID)
                 self.state = 517
+                self.match(SystemRDLParser.T__10)
+                self.state = 518
+                self.match(SystemRDLParser.T__1)
+                self.state = 519
                 self.struct_kv()
-                self.state = 522
+                self.state = 524
                 self._errHandler.sync(self)
                 _la = self._input.LA(1)
+                while _la==4:
+                    self.state = 520
+                    self.match(SystemRDLParser.T__3)
+                    self.state = 521
+                    self.struct_kv()
+                    self.state = 526
+                    self._errHandler.sync(self)
+                    _la = self._input.LA(1)
+
+                self.state = 527
+                self.match(SystemRDLParser.T__2)
+                pass
+
 
-            self.state = 523
-            self.match(SystemRDLParser.T__2)
         except RecognitionException as re:
             localctx.exception = re
             self._errHandler.reportError(self, re)
@@ -3799,11 +3821,11 @@ def struct_kv(self):
         self.enterRule(localctx, 82, self.RULE_struct_kv)
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 525
+            self.state = 531
             self.match(SystemRDLParser.ID)
-            self.state = 526
+            self.state = 532
             self.match(SystemRDLParser.T__9)
-            self.state = 527
+            self.state = 533
             self.expr(0)
         except RecognitionException as re:
             localctx.exception = re
@@ -3845,11 +3867,11 @@ def enum_literal(self):
         self.enterRule(localctx, 84, self.RULE_enum_literal)
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 529
+            self.state = 535
             self.match(SystemRDLParser.ID)
-            self.state = 530
+            self.state = 536
             self.match(SystemRDLParser.T__13)
-            self.state = 531
+            self.state = 537
             self.match(SystemRDLParser.ID)
         except RecognitionException as re:
             localctx.exception = re
@@ -3908,7 +3930,7 @@ def accesstype_literal(self):
         self._la = 0 # Token type
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 533
+            self.state = 539
             localctx.kw = self._input.LT(1)
             _la = self._input.LA(1)
             if not((((_la) & ~0x3f) == 0 and ((1 << _la) & 34909494181888) != 0)):
@@ -3961,7 +3983,7 @@ def onreadtype_literal(self):
         self._la = 0 # Token type
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 535
+            self.state = 541
             localctx.kw = self._input.LT(1)
             _la = self._input.LA(1)
             if not((((_la) & ~0x3f) == 0 and ((1 << _la) & 246290604621824) != 0)):
@@ -4032,7 +4054,7 @@ def onwritetype_literal(self):
         self._la = 0 # Token type
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 537
+            self.state = 543
             localctx.kw = self._input.LT(1)
             _la = self._input.LA(1)
             if not((((_la) & ~0x3f) == 0 and ((1 << _la) & 143833713099145216) != 0)):
@@ -4085,7 +4107,7 @@ def addressingtype_literal(self):
         self._la = 0 # Token type
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 539
+            self.state = 545
             localctx.kw = self._input.LT(1)
             _la = self._input.LA(1)
             if not((((_la) & ~0x3f) == 0 and ((1 << _la) & 1008806316530991104) != 0)):
@@ -4135,7 +4157,7 @@ def precedencetype_literal(self):
         self._la = 0 # Token type
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 541
+            self.state = 547
             localctx.kw = self._input.LT(1)
             _la = self._input.LA(1)
             if not(_la==60 or _la==61):
@@ -4184,20 +4206,20 @@ def instance_ref(self):
         self.enterRule(localctx, 96, self.RULE_instance_ref)
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 543
+            self.state = 549
             self.instance_ref_element()
-            self.state = 548
+            self.state = 554
             self._errHandler.sync(self)
-            _alt = self._interp.adaptivePredict(self._input,39,self._ctx)
+            _alt = self._interp.adaptivePredict(self._input,40,self._ctx)
             while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                 if _alt==1:
-                    self.state = 544
+                    self.state = 550
                     self.match(SystemRDLParser.T__7)
-                    self.state = 545
+                    self.state = 551
                     self.instance_ref_element() 
-                self.state = 550
+                self.state = 556
                 self._errHandler.sync(self)
-                _alt = self._interp.adaptivePredict(self._input,39,self._ctx)
+                _alt = self._interp.adaptivePredict(self._input,40,self._ctx)
 
         except RecognitionException as re:
             localctx.exception = re
@@ -4243,18 +4265,18 @@ def instance_ref_element(self):
         self.enterRule(localctx, 98, self.RULE_instance_ref_element)
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 551
+            self.state = 557
             self.match(SystemRDLParser.ID)
-            self.state = 555
+            self.state = 561
             self._errHandler.sync(self)
-            _alt = self._interp.adaptivePredict(self._input,40,self._ctx)
+            _alt = self._interp.adaptivePredict(self._input,41,self._ctx)
             while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                 if _alt==1:
-                    self.state = 552
+                    self.state = 558
                     self.array_suffix() 
-                self.state = 557
+                self.state = 563
                 self._errHandler.sync(self)
-                _alt = self._interp.adaptivePredict(self._input,40,self._ctx)
+                _alt = self._interp.adaptivePredict(self._input,41,self._ctx)
 
         except RecognitionException as re:
             localctx.exception = re
@@ -4301,19 +4323,19 @@ def prop_ref(self):
         self.enterRule(localctx, 100, self.RULE_prop_ref)
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 558
+            self.state = 564
             self.instance_ref()
-            self.state = 559
+            self.state = 565
             self.match(SystemRDLParser.T__14)
-            self.state = 562
+            self.state = 568
             self._errHandler.sync(self)
             token = self._input.LA(1)
             if token in [45, 46, 48, 49, 60, 61]:
-                self.state = 560
+                self.state = 566
                 self.prop_keyword()
                 pass
             elif token in [125]:
-                self.state = 561
+                self.state = 567
                 self.match(SystemRDLParser.ID)
                 pass
             else:
@@ -4368,48 +4390,48 @@ def local_property_assignment(self):
         self.enterRule(localctx, 102, self.RULE_local_property_assignment)
         self._la = 0 # Token type
         try:
-            self.state = 576
+            self.state = 582
             self._errHandler.sync(self)
-            la_ = self._interp.adaptivePredict(self._input,45,self._ctx)
+            la_ = self._interp.adaptivePredict(self._input,46,self._ctx)
             if la_ == 1:
                 self.enterOuterAlt(localctx, 1)
-                self.state = 565
+                self.state = 571
                 self._errHandler.sync(self)
                 _la = self._input.LA(1)
                 if _la==72:
-                    self.state = 564
+                    self.state = 570
                     self.match(SystemRDLParser.DEFAULT_kw)
 
 
-                self.state = 567
+                self.state = 573
                 self.normal_prop_assign()
                 pass
 
             elif la_ == 2:
                 self.enterOuterAlt(localctx, 2)
-                self.state = 569
+                self.state = 575
                 self._errHandler.sync(self)
                 _la = self._input.LA(1)
                 if _la==72:
-                    self.state = 568
+                    self.state = 574
                     self.match(SystemRDLParser.DEFAULT_kw)
 
 
-                self.state = 571
+                self.state = 577
                 self.encode_prop_assign()
                 pass
 
             elif la_ == 3:
                 self.enterOuterAlt(localctx, 3)
-                self.state = 573
+                self.state = 579
                 self._errHandler.sync(self)
                 _la = self._input.LA(1)
                 if _la==72:
-                    self.state = 572
+                    self.state = 578
                     self.match(SystemRDLParser.DEFAULT_kw)
 
 
-                self.state = 575
+                self.state = 581
                 self.prop_mod_assign()
                 pass
 
@@ -4459,26 +4481,26 @@ def dynamic_property_assignment(self):
         localctx = SystemRDLParser.Dynamic_property_assignmentContext(self, self._ctx, self.state)
         self.enterRule(localctx, 104, self.RULE_dynamic_property_assignment)
         try:
-            self.state = 586
+            self.state = 592
             self._errHandler.sync(self)
-            la_ = self._interp.adaptivePredict(self._input,46,self._ctx)
+            la_ = self._interp.adaptivePredict(self._input,47,self._ctx)
             if la_ == 1:
                 self.enterOuterAlt(localctx, 1)
-                self.state = 578
+                self.state = 584
                 self.instance_ref()
-                self.state = 579
+                self.state = 585
                 self.match(SystemRDLParser.T__14)
-                self.state = 580
+                self.state = 586
                 self.normal_prop_assign()
                 pass
 
             elif la_ == 2:
                 self.enterOuterAlt(localctx, 2)
-                self.state = 582
+                self.state = 588
                 self.instance_ref()
-                self.state = 583
+                self.state = 589
                 self.match(SystemRDLParser.T__14)
-                self.state = 584
+                self.state = 590
                 self.encode_prop_assign()
                 pass
 
@@ -4532,27 +4554,27 @@ def normal_prop_assign(self):
         self._la = 0 # Token type
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 590
+            self.state = 596
             self._errHandler.sync(self)
             token = self._input.LA(1)
             if token in [45, 46, 48, 49, 60, 61]:
-                self.state = 588
+                self.state = 594
                 self.prop_keyword()
                 pass
             elif token in [125]:
-                self.state = 589
+                self.state = 595
                 self.match(SystemRDLParser.ID)
                 pass
             else:
                 raise NoViableAltException(self)
 
-            self.state = 594
+            self.state = 600
             self._errHandler.sync(self)
             _la = self._input.LA(1)
             if _la==115:
-                self.state = 592
+                self.state = 598
                 self.match(SystemRDLParser.ASSIGN)
-                self.state = 593
+                self.state = 599
                 self.prop_assignment_rhs()
 
 
@@ -4599,11 +4621,11 @@ def encode_prop_assign(self):
         self.enterRule(localctx, 108, self.RULE_encode_prop_assign)
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 596
+            self.state = 602
             self.match(SystemRDLParser.ENCODE_kw)
-            self.state = 597
+            self.state = 603
             self.match(SystemRDLParser.ASSIGN)
-            self.state = 598
+            self.state = 604
             self.match(SystemRDLParser.ID)
         except RecognitionException as re:
             localctx.exception = re
@@ -4646,9 +4668,9 @@ def prop_mod_assign(self):
         self.enterRule(localctx, 110, self.RULE_prop_mod_assign)
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 600
+            self.state = 606
             self.prop_mod()
-            self.state = 601
+            self.state = 607
             self.match(SystemRDLParser.ID)
         except RecognitionException as re:
             localctx.exception = re
@@ -4691,18 +4713,18 @@ def prop_assignment_rhs(self):
         localctx = SystemRDLParser.Prop_assignment_rhsContext(self, self._ctx, self.state)
         self.enterRule(localctx, 112, self.RULE_prop_assignment_rhs)
         try:
-            self.state = 605
+            self.state = 611
             self._errHandler.sync(self)
-            la_ = self._interp.adaptivePredict(self._input,49,self._ctx)
+            la_ = self._interp.adaptivePredict(self._input,50,self._ctx)
             if la_ == 1:
                 self.enterOuterAlt(localctx, 1)
-                self.state = 603
+                self.state = 609
                 self.precedencetype_literal()
                 pass
 
             elif la_ == 2:
                 self.enterOuterAlt(localctx, 2)
-                self.state = 604
+                self.state = 610
                 self.expr(0)
                 pass
 
@@ -4761,7 +4783,7 @@ def prop_keyword(self):
         self._la = 0 # Token type
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 607
+            self.state = 613
             localctx.kw = self._input.LT(1)
             _la = self._input.LA(1)
             if not((((_la) & ~0x3f) == 0 and ((1 << _la) & 3459714491866939392) != 0)):
@@ -4820,7 +4842,7 @@ def prop_mod(self):
         self._la = 0 # Token type
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 609
+            self.state = 615
             localctx.kw = self._input.LT(1)
             _la = self._input.LA(1)
             if not(((((_la - 62)) & ~0x3f) == 0 and ((1 << (_la - 62)) & 31) != 0)):
@@ -4876,27 +4898,27 @@ def udp_def(self):
         self._la = 0 # Token type
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 611
+            self.state = 617
             self.match(SystemRDLParser.PROPERTY_kw)
-            self.state = 612
+            self.state = 618
             self.match(SystemRDLParser.ID)
-            self.state = 613
+            self.state = 619
             self.match(SystemRDLParser.T__1)
-            self.state = 617 
+            self.state = 623 
             self._errHandler.sync(self)
             _la = self._input.LA(1)
             while True:
-                self.state = 614
+                self.state = 620
                 self.udp_attr()
-                self.state = 615
+                self.state = 621
                 self.match(SystemRDLParser.T__0)
-                self.state = 619 
+                self.state = 625 
                 self._errHandler.sync(self)
                 _la = self._input.LA(1)
                 if not (((((_la - 69)) & ~0x3f) == 0 and ((1 << (_la - 69)) & 4109) != 0)):
                     break
 
-            self.state = 621
+            self.state = 627
             self.match(SystemRDLParser.T__2)
         except RecognitionException as re:
             localctx.exception = re
@@ -4947,27 +4969,27 @@ def udp_attr(self):
         localctx = SystemRDLParser.Udp_attrContext(self, self._ctx, self.state)
         self.enterRule(localctx, 120, self.RULE_udp_attr)
         try:
-            self.state = 627
+            self.state = 633
             self._errHandler.sync(self)
             token = self._input.LA(1)
             if token in [81]:
                 self.enterOuterAlt(localctx, 1)
-                self.state = 623
+                self.state = 629
                 self.udp_type()
                 pass
             elif token in [69]:
                 self.enterOuterAlt(localctx, 2)
-                self.state = 624
+                self.state = 630
                 self.udp_usage()
                 pass
             elif token in [72]:
                 self.enterOuterAlt(localctx, 3)
-                self.state = 625
+                self.state = 631
                 self.udp_default()
                 pass
             elif token in [71]:
                 self.enterOuterAlt(localctx, 4)
-                self.state = 626
+                self.state = 632
                 self.udp_constraint()
                 pass
             else:
@@ -5022,17 +5044,17 @@ def udp_type(self):
         self._la = 0 # Token type
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 629
+            self.state = 635
             self.match(SystemRDLParser.TYPE_kw)
-            self.state = 630
+            self.state = 636
             self.match(SystemRDLParser.ASSIGN)
-            self.state = 631
+            self.state = 637
             self.udp_data_type()
-            self.state = 633
+            self.state = 639
             self._errHandler.sync(self)
             _la = self._input.LA(1)
             if _la==12:
-                self.state = 632
+                self.state = 638
                 self.array_type_suffix()
 
 
@@ -5085,17 +5107,17 @@ def udp_data_type(self):
         self.enterRule(localctx, 124, self.RULE_udp_data_type)
         self._la = 0 # Token type
         try:
-            self.state = 638
+            self.state = 644
             self._errHandler.sync(self)
             token = self._input.LA(1)
             if token in [30, 31, 32, 33, 34]:
                 self.enterOuterAlt(localctx, 1)
-                self.state = 635
+                self.state = 641
                 self.component_type_primary()
                 pass
             elif token in [76, 78]:
                 self.enterOuterAlt(localctx, 2)
-                self.state = 636
+                self.state = 642
                 localctx.kw = self._input.LT(1)
                 _la = self._input.LA(1)
                 if not(_la==76 or _la==78):
@@ -5106,7 +5128,7 @@ def udp_data_type(self):
                 pass
             elif token in [18, 19, 20, 22, 125]:
                 self.enterOuterAlt(localctx, 3)
-                self.state = 637
+                self.state = 643
                 self.basic_data_type()
                 pass
             else:
@@ -5166,21 +5188,21 @@ def udp_usage(self):
         self._la = 0 # Token type
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 640
+            self.state = 646
             self.match(SystemRDLParser.COMPONENT_kw)
-            self.state = 641
+            self.state = 647
             self.match(SystemRDLParser.ASSIGN)
-            self.state = 642
+            self.state = 648
             self.udp_comp_type()
-            self.state = 647
+            self.state = 653
             self._errHandler.sync(self)
             _la = self._input.LA(1)
             while _la==103:
-                self.state = 643
+                self.state = 649
                 self.match(SystemRDLParser.OR)
-                self.state = 644
+                self.state = 650
                 self.udp_comp_type()
-                self.state = 649
+                self.state = 655
                 self._errHandler.sync(self)
                 _la = self._input.LA(1)
 
@@ -5229,17 +5251,17 @@ def udp_comp_type(self):
         self.enterRule(localctx, 128, self.RULE_udp_comp_type)
         self._la = 0 # Token type
         try:
-            self.state = 652
+            self.state = 658
             self._errHandler.sync(self)
             token = self._input.LA(1)
             if token in [30, 31, 32, 33, 34, 35]:
                 self.enterOuterAlt(localctx, 1)
-                self.state = 650
+                self.state = 656
                 self.component_type()
                 pass
             elif token in [68, 71]:
                 self.enterOuterAlt(localctx, 2)
-                self.state = 651
+                self.state = 657
                 localctx.kw = self._input.LT(1)
                 _la = self._input.LA(1)
                 if not(_la==68 or _la==71):
@@ -5295,11 +5317,11 @@ def udp_default(self):
         self.enterRule(localctx, 130, self.RULE_udp_default)
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 654
+            self.state = 660
             self.match(SystemRDLParser.DEFAULT_kw)
-            self.state = 655
+            self.state = 661
             self.match(SystemRDLParser.ASSIGN)
-            self.state = 656
+            self.state = 662
             self.expr(0)
         except RecognitionException as re:
             localctx.exception = re
@@ -5344,11 +5366,11 @@ def udp_constraint(self):
         self.enterRule(localctx, 132, self.RULE_udp_constraint)
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 658
+            self.state = 664
             self.match(SystemRDLParser.CONSTRAINT_kw)
-            self.state = 659
+            self.state = 665
             self.match(SystemRDLParser.ASSIGN)
-            self.state = 660
+            self.state = 666
             self.match(SystemRDLParser.COMPONENTWIDTH_kw)
         except RecognitionException as re:
             localctx.exception = re
@@ -5398,27 +5420,27 @@ def enum_def(self):
         self._la = 0 # Token type
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 662
+            self.state = 668
             self.match(SystemRDLParser.ENUM_kw)
-            self.state = 663
+            self.state = 669
             self.match(SystemRDLParser.ID)
-            self.state = 664
+            self.state = 670
             self.match(SystemRDLParser.T__1)
-            self.state = 668 
+            self.state = 674 
             self._errHandler.sync(self)
             _la = self._input.LA(1)
             while True:
-                self.state = 665
+                self.state = 671
                 self.enum_entry()
-                self.state = 666
+                self.state = 672
                 self.match(SystemRDLParser.T__0)
-                self.state = 670 
+                self.state = 676 
                 self._errHandler.sync(self)
                 _la = self._input.LA(1)
                 if not (_la==125):
                     break
 
-            self.state = 672
+            self.state = 678
             self.match(SystemRDLParser.T__2)
         except RecognitionException as re:
             localctx.exception = re
@@ -5472,37 +5494,37 @@ def enum_entry(self):
         self._la = 0 # Token type
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 674
+            self.state = 680
             self.match(SystemRDLParser.ID)
-            self.state = 677
+            self.state = 683
             self._errHandler.sync(self)
             _la = self._input.LA(1)
             if _la==115:
-                self.state = 675
+                self.state = 681
                 self.match(SystemRDLParser.ASSIGN)
-                self.state = 676
+                self.state = 682
                 self.expr(0)
 
 
-            self.state = 689
+            self.state = 695
             self._errHandler.sync(self)
             _la = self._input.LA(1)
             if _la==2:
-                self.state = 679
-                self.match(SystemRDLParser.T__1)
                 self.state = 685
+                self.match(SystemRDLParser.T__1)
+                self.state = 691
                 self._errHandler.sync(self)
                 _la = self._input.LA(1)
                 while _la==125:
-                    self.state = 680
+                    self.state = 686
                     self.enum_prop_assign()
-                    self.state = 681
-                    self.match(SystemRDLParser.T__0)
                     self.state = 687
+                    self.match(SystemRDLParser.T__0)
+                    self.state = 693
                     self._errHandler.sync(self)
                     _la = self._input.LA(1)
 
-                self.state = 688
+                self.state = 694
                 self.match(SystemRDLParser.T__2)
 
 
@@ -5550,11 +5572,11 @@ def enum_prop_assign(self):
         self.enterRule(localctx, 138, self.RULE_enum_prop_assign)
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 691
+            self.state = 697
             self.match(SystemRDLParser.ID)
-            self.state = 692
+            self.state = 698
             self.match(SystemRDLParser.ASSIGN)
-            self.state = 693
+            self.state = 699
             self.expr(0)
         except RecognitionException as re:
             localctx.exception = re
@@ -5612,43 +5634,43 @@ def struct_def(self):
         self._la = 0 # Token type
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 696
+            self.state = 702
             self._errHandler.sync(self)
             _la = self._input.LA(1)
             if _la==67:
-                self.state = 695
+                self.state = 701
                 self.match(SystemRDLParser.ABSTRACT_kw)
 
 
-            self.state = 698
+            self.state = 704
             self.match(SystemRDLParser.STRUCT_kw)
-            self.state = 699
+            self.state = 705
             localctx.name = self.match(SystemRDLParser.ID)
-            self.state = 702
+            self.state = 708
             self._errHandler.sync(self)
             _la = self._input.LA(1)
             if _la==10:
-                self.state = 700
+                self.state = 706
                 self.match(SystemRDLParser.T__9)
-                self.state = 701
+                self.state = 707
                 localctx.base = self.match(SystemRDLParser.ID)
 
 
-            self.state = 704
-            self.match(SystemRDLParser.T__1)
             self.state = 710
+            self.match(SystemRDLParser.T__1)
+            self.state = 716
             self._errHandler.sync(self)
             _la = self._input.LA(1)
             while (((_la) & ~0x3f) == 0 and ((1 << _la) & 67777593344) != 0) or _la==125:
-                self.state = 705
+                self.state = 711
                 self.struct_elem()
-                self.state = 706
-                self.match(SystemRDLParser.T__0)
                 self.state = 712
+                self.match(SystemRDLParser.T__0)
+                self.state = 718
                 self._errHandler.sync(self)
                 _la = self._input.LA(1)
 
-            self.state = 713
+            self.state = 719
             self.match(SystemRDLParser.T__2)
         except RecognitionException as re:
             localctx.exception = re
@@ -5696,15 +5718,15 @@ def struct_elem(self):
         self._la = 0 # Token type
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 715
+            self.state = 721
             self.struct_type()
-            self.state = 716
+            self.state = 722
             self.match(SystemRDLParser.ID)
-            self.state = 718
+            self.state = 724
             self._errHandler.sync(self)
             _la = self._input.LA(1)
             if _la==12:
-                self.state = 717
+                self.state = 723
                 self.array_type_suffix()
 
 
@@ -5749,17 +5771,17 @@ def struct_type(self):
         localctx = SystemRDLParser.Struct_typeContext(self, self._ctx, self.state)
         self.enterRule(localctx, 144, self.RULE_struct_type)
         try:
-            self.state = 722
+            self.state = 728
             self._errHandler.sync(self)
             token = self._input.LA(1)
             if token in [18, 19, 20, 22, 23, 24, 25, 26, 125]:
                 self.enterOuterAlt(localctx, 1)
-                self.state = 720
+                self.state = 726
                 self.data_type()
                 pass
             elif token in [30, 31, 32, 33, 34, 35]:
                 self.enterOuterAlt(localctx, 2)
-                self.state = 721
+                self.state = 727
                 self.component_type()
                 pass
             else:
@@ -5811,18 +5833,18 @@ def constraint_def(self):
         self.enterRule(localctx, 146, self.RULE_constraint_def)
         self._la = 0 # Token type
         try:
-            self.state = 731
+            self.state = 737
             self._errHandler.sync(self)
-            la_ = self._interp.adaptivePredict(self._input,66,self._ctx)
+            la_ = self._interp.adaptivePredict(self._input,67,self._ctx)
             if la_ == 1:
                 self.enterOuterAlt(localctx, 1)
-                self.state = 724
+                self.state = 730
                 self.constraint_named_def()
-                self.state = 726
+                self.state = 732
                 self._errHandler.sync(self)
                 _la = self._input.LA(1)
                 if _la==125:
-                    self.state = 725
+                    self.state = 731
                     self.constraint_insts()
 
 
@@ -5830,9 +5852,9 @@ def constraint_def(self):
 
             elif la_ == 2:
                 self.enterOuterAlt(localctx, 2)
-                self.state = 728
+                self.state = 734
                 self.constraint_anon_def()
-                self.state = 729
+                self.state = 735
                 self.constraint_insts()
                 pass
 
@@ -5881,11 +5903,11 @@ def constraint_named_def(self):
         self.enterRule(localctx, 148, self.RULE_constraint_named_def)
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 733
+            self.state = 739
             self.match(SystemRDLParser.CONSTRAINT_kw)
-            self.state = 734
+            self.state = 740
             self.match(SystemRDLParser.ID)
-            self.state = 735
+            self.state = 741
             self.constraint_body()
         except RecognitionException as re:
             localctx.exception = re
@@ -5928,9 +5950,9 @@ def constraint_anon_def(self):
         self.enterRule(localctx, 150, self.RULE_constraint_anon_def)
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 737
+            self.state = 743
             self.match(SystemRDLParser.CONSTRAINT_kw)
-            self.state = 738
+            self.state = 744
             self.constraint_body()
         except RecognitionException as re:
             localctx.exception = re
@@ -5974,21 +5996,21 @@ def constraint_body(self):
         self._la = 0 # Token type
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 740
-            self.match(SystemRDLParser.T__1)
             self.state = 746
+            self.match(SystemRDLParser.T__1)
+            self.state = 752
             self._errHandler.sync(self)
             _la = self._input.LA(1)
             while (((_la) & ~0x3f) == 0 and ((1 << _la) & 4611685949709748292) != 0) or ((((_la - 80)) & ~0x3f) == 0 and ((1 << (_la - 80)) & 35184622694401) != 0):
-                self.state = 741
+                self.state = 747
                 self.constraint_body_elem()
-                self.state = 742
-                self.match(SystemRDLParser.T__0)
                 self.state = 748
+                self.match(SystemRDLParser.T__0)
+                self.state = 754
                 self._errHandler.sync(self)
                 _la = self._input.LA(1)
 
-            self.state = 749
+            self.state = 755
             self.match(SystemRDLParser.T__2)
         except RecognitionException as re:
             localctx.exception = re
@@ -6039,30 +6061,30 @@ def constraint_body_elem(self):
         localctx = SystemRDLParser.Constraint_body_elemContext(self, self._ctx, self.state)
         self.enterRule(localctx, 154, self.RULE_constraint_body_elem)
         try:
-            self.state = 755
+            self.state = 761
             self._errHandler.sync(self)
-            la_ = self._interp.adaptivePredict(self._input,68,self._ctx)
+            la_ = self._interp.adaptivePredict(self._input,69,self._ctx)
             if la_ == 1:
                 self.enterOuterAlt(localctx, 1)
-                self.state = 751
+                self.state = 757
                 self.constr_relational()
                 pass
 
             elif la_ == 2:
                 self.enterOuterAlt(localctx, 2)
-                self.state = 752
+                self.state = 758
                 self.constr_prop_assign()
                 pass
 
             elif la_ == 3:
                 self.enterOuterAlt(localctx, 3)
-                self.state = 753
+                self.state = 759
                 self.constr_inside_values()
                 pass
 
             elif la_ == 4:
                 self.enterOuterAlt(localctx, 4)
-                self.state = 754
+                self.state = 760
                 self.constr_inside_enum()
                 pass
 
@@ -6108,17 +6130,17 @@ def constraint_insts(self):
         self._la = 0 # Token type
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 757
+            self.state = 763
             self.match(SystemRDLParser.ID)
-            self.state = 762
+            self.state = 768
             self._errHandler.sync(self)
             _la = self._input.LA(1)
             while _la==4:
-                self.state = 758
+                self.state = 764
                 self.match(SystemRDLParser.T__3)
-                self.state = 759
+                self.state = 765
                 self.match(SystemRDLParser.ID)
-                self.state = 764
+                self.state = 770
                 self._errHandler.sync(self)
                 _la = self._input.LA(1)
 
@@ -6183,9 +6205,9 @@ def constr_relational(self):
         self._la = 0 # Token type
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 765
+            self.state = 771
             self.expr(0)
-            self.state = 766
+            self.state = 772
             localctx.op = self._input.LT(1)
             _la = self._input.LA(1)
             if not(((((_la - 114)) & ~0x3f) == 0 and ((1 << (_la - 114)) & 125) != 0)):
@@ -6193,7 +6215,7 @@ def constr_relational(self):
             else:
                 self._errHandler.reportMatch(self)
                 self.consume()
-            self.state = 767
+            self.state = 773
             self.expr(0)
         except RecognitionException as re:
             localctx.exception = re
@@ -6239,11 +6261,11 @@ def constr_prop_assign(self):
         self.enterRule(localctx, 160, self.RULE_constr_prop_assign)
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 769
+            self.state = 775
             self.match(SystemRDLParser.ID)
-            self.state = 770
+            self.state = 776
             self.match(SystemRDLParser.ASSIGN)
-            self.state = 771
+            self.state = 777
             self.expr(0)
         except RecognitionException as re:
             localctx.exception = re
@@ -6294,27 +6316,27 @@ def constr_inside_values(self):
         self._la = 0 # Token type
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 773
+            self.state = 779
             self.constr_lhs()
-            self.state = 774
+            self.state = 780
             self.match(SystemRDLParser.INSIDE_kw)
-            self.state = 775
+            self.state = 781
             self.match(SystemRDLParser.T__1)
-            self.state = 776
+            self.state = 782
             self.constr_inside_value()
-            self.state = 781
+            self.state = 787
             self._errHandler.sync(self)
             _la = self._input.LA(1)
             while _la==4:
-                self.state = 777
+                self.state = 783
                 self.match(SystemRDLParser.T__3)
-                self.state = 778
+                self.state = 784
                 self.constr_inside_value()
-                self.state = 783
+                self.state = 789
                 self._errHandler.sync(self)
                 _la = self._input.LA(1)
 
-            self.state = 784
+            self.state = 790
             self.match(SystemRDLParser.T__2)
         except RecognitionException as re:
             localctx.exception = re
@@ -6360,11 +6382,11 @@ def constr_inside_enum(self):
         self.enterRule(localctx, 164, self.RULE_constr_inside_enum)
         try:
             self.enterOuterAlt(localctx, 1)
-            self.state = 786
+            self.state = 792
             self.constr_lhs()
-            self.state = 787
+            self.state = 793
             self.match(SystemRDLParser.INSIDE_kw)
-            self.state = 788
+            self.state = 794
             self.match(SystemRDLParser.ID)
         except RecognitionException as re:
             localctx.exception = re
@@ -6406,17 +6428,17 @@ def constr_lhs(self):
         localctx = SystemRDLParser.Constr_lhsContext(self, self._ctx, self.state)
         self.enterRule(localctx, 166, self.RULE_constr_lhs)
         try:
-            self.state = 792
+            self.state = 798
             self._errHandler.sync(self)
             token = self._input.LA(1)
             if token in [80]:
                 self.enterOuterAlt(localctx, 1)
-                self.state = 790
+                self.state = 796
                 self.match(SystemRDLParser.THIS_kw)
                 pass
             elif token in [125]:
                 self.enterOuterAlt(localctx, 2)
-                self.state = 791
+                self.state = 797
                 self.instance_ref()
                 pass
             else:
@@ -6465,25 +6487,25 @@ def constr_inside_value(self):
         localctx = SystemRDLParser.Constr_inside_valueContext(self, self._ctx, self.state)
         self.enterRule(localctx, 168, self.RULE_constr_inside_value)
         try:
-            self.state = 801
+            self.state = 807
             self._errHandler.sync(self)
             token = self._input.LA(1)
             if token in [2, 6, 11, 18, 19, 20, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 92, 93, 94, 95, 96, 97, 98, 99, 101, 102, 103, 105, 106, 107, 125]:
                 self.enterOuterAlt(localctx, 1)
-                self.state = 794
+                self.state = 800
                 localctx.val = self.expr(0)
                 pass
             elif token in [12]:
                 self.enterOuterAlt(localctx, 2)
-                self.state = 795
+                self.state = 801
                 self.match(SystemRDLParser.T__11)
-                self.state = 796
+                self.state = 802
                 localctx.l_val = self.expr(0)
-                self.state = 797
+                self.state = 803
                 self.match(SystemRDLParser.T__9)
-                self.state = 798
+                self.state = 804
                 localctx.r_val = self.expr(0)
-                self.state = 799
+                self.state = 805
                 self.match(SystemRDLParser.T__12)
                 pass
             else:
diff --git a/systemrdl/parser/ext/SystemRDL.interp b/systemrdl/parser/ext/SystemRDL.interp
index 389b56d..369625f 100644
--- a/systemrdl/parser/ext/SystemRDL.interp
+++ b/systemrdl/parser/ext/SystemRDL.interp
@@ -343,4 +343,4 @@ constr_inside_value
 
 
 atn:
-[4, 1, 125, 804, 2, 0, 7, 0, 2, 1, 7, 1, 2, 2, 7, 2, 2, 3, 7, 3, 2, 4, 7, 4, 2, 5, 7, 5, 2, 6, 7, 6, 2, 7, 7, 7, 2, 8, 7, 8, 2, 9, 7, 9, 2, 10, 7, 10, 2, 11, 7, 11, 2, 12, 7, 12, 2, 13, 7, 13, 2, 14, 7, 14, 2, 15, 7, 15, 2, 16, 7, 16, 2, 17, 7, 17, 2, 18, 7, 18, 2, 19, 7, 19, 2, 20, 7, 20, 2, 21, 7, 21, 2, 22, 7, 22, 2, 23, 7, 23, 2, 24, 7, 24, 2, 25, 7, 25, 2, 26, 7, 26, 2, 27, 7, 27, 2, 28, 7, 28, 2, 29, 7, 29, 2, 30, 7, 30, 2, 31, 7, 31, 2, 32, 7, 32, 2, 33, 7, 33, 2, 34, 7, 34, 2, 35, 7, 35, 2, 36, 7, 36, 2, 37, 7, 37, 2, 38, 7, 38, 2, 39, 7, 39, 2, 40, 7, 40, 2, 41, 7, 41, 2, 42, 7, 42, 2, 43, 7, 43, 2, 44, 7, 44, 2, 45, 7, 45, 2, 46, 7, 46, 2, 47, 7, 47, 2, 48, 7, 48, 2, 49, 7, 49, 2, 50, 7, 50, 2, 51, 7, 51, 2, 52, 7, 52, 2, 53, 7, 53, 2, 54, 7, 54, 2, 55, 7, 55, 2, 56, 7, 56, 2, 57, 7, 57, 2, 58, 7, 58, 2, 59, 7, 59, 2, 60, 7, 60, 2, 61, 7, 61, 2, 62, 7, 62, 2, 63, 7, 63, 2, 64, 7, 64, 2, 65, 7, 65, 2, 66, 7, 66, 2, 67, 7, 67, 2, 68, 7, 68, 2, 69, 7, 69, 2, 70, 7, 70, 2, 71, 7, 71, 2, 72, 7, 72, 2, 73, 7, 73, 2, 74, 7, 74, 2, 75, 7, 75, 2, 76, 7, 76, 2, 77, 7, 77, 2, 78, 7, 78, 2, 79, 7, 79, 2, 80, 7, 80, 2, 81, 7, 81, 2, 82, 7, 82, 2, 83, 7, 83, 2, 84, 7, 84, 1, 0, 1, 0, 1, 0, 5, 0, 174, 8, 0, 10, 0, 12, 0, 177, 9, 0, 1, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 3, 2, 192, 8, 2, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 3, 3, 199, 8, 3, 3, 3, 201, 8, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 3, 3, 208, 8, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 3, 3, 218, 8, 3, 1, 4, 3, 4, 221, 8, 4, 1, 4, 3, 4, 224, 8, 4, 1, 4, 1, 4, 1, 4, 1, 5, 1, 5, 1, 5, 1, 6, 1, 6, 1, 6, 3, 6, 235, 8, 6, 1, 6, 1, 6, 1, 7, 1, 7, 1, 7, 1, 8, 1, 8, 1, 8, 1, 8, 5, 8, 246, 8, 8, 10, 8, 12, 8, 249, 9, 8, 1, 8, 1, 8, 1, 9, 1, 9, 1, 9, 1, 9, 1, 9, 1, 9, 1, 9, 3, 9, 260, 8, 9, 1, 10, 3, 10, 263, 8, 10, 1, 10, 1, 10, 1, 10, 5, 10, 268, 8, 10, 10, 10, 12, 10, 271, 9, 10, 1, 11, 1, 11, 4, 11, 275, 8, 11, 11, 11, 12, 11, 276, 1, 11, 3, 11, 280, 8, 11, 1, 11, 3, 11, 283, 8, 11, 1, 11, 3, 11, 286, 8, 11, 1, 11, 3, 11, 289, 8, 11, 1, 11, 3, 11, 292, 8, 11, 1, 12, 1, 12, 1, 12, 1, 13, 1, 13, 1, 13, 1, 14, 1, 14, 1, 14, 1, 15, 1, 15, 1, 15, 1, 16, 1, 16, 1, 17, 1, 17, 3, 17, 310, 8, 17, 1, 18, 1, 18, 1, 19, 1, 19, 1, 19, 1, 19, 1, 19, 5, 19, 319, 8, 19, 10, 19, 12, 19, 322, 9, 19, 1, 19, 1, 19, 1, 20, 1, 20, 1, 20, 3, 20, 329, 8, 20, 1, 20, 1, 20, 3, 20, 333, 8, 20, 1, 21, 1, 21, 1, 21, 1, 21, 1, 21, 5, 21, 340, 8, 21, 10, 21, 12, 21, 343, 9, 21, 1, 21, 1, 21, 1, 22, 1, 22, 1, 22, 1, 22, 1, 22, 1, 22, 1, 23, 1, 23, 1, 23, 1, 23, 3, 23, 357, 8, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 5, 23, 398, 8, 23, 10, 23, 12, 23, 401, 9, 23, 1, 24, 1, 24, 1, 24, 1, 24, 1, 24, 1, 24, 1, 24, 1, 24, 1, 24, 3, 24, 412, 8, 24, 1, 25, 1, 25, 1, 25, 1, 25, 5, 25, 418, 8, 25, 10, 25, 12, 25, 421, 9, 25, 1, 25, 1, 25, 1, 26, 1, 26, 1, 26, 1, 26, 1, 26, 1, 27, 1, 27, 1, 27, 1, 27, 1, 28, 1, 28, 1, 28, 1, 28, 1, 28, 1, 28, 1, 28, 1, 28, 1, 28, 1, 28, 1, 28, 1, 28, 3, 28, 446, 8, 28, 1, 29, 1, 29, 3, 29, 450, 8, 29, 1, 30, 1, 30, 1, 30, 1, 30, 1, 30, 1, 30, 1, 31, 1, 31, 1, 31, 1, 31, 1, 32, 1, 32, 1, 32, 1, 33, 1, 33, 3, 33, 467, 8, 33, 1, 34, 1, 34, 3, 34, 471, 8, 34, 1, 34, 3, 34, 474, 8, 34, 1, 35, 1, 35, 1, 35, 1, 35, 1, 35, 1, 35, 1, 35, 1, 35, 1, 35, 3, 35, 485, 8, 35, 1, 36, 1, 36, 1, 36, 3, 36, 490, 8, 36, 1, 37, 1, 37, 1, 38, 1, 38, 1, 39, 1, 39, 1, 39, 1, 39, 1, 39, 1, 39, 1, 39, 1, 39, 5, 39, 504, 8, 39, 10, 39, 12, 39, 507, 9, 39, 1, 39, 1, 39, 3, 39, 511, 8, 39, 1, 40, 1, 40, 1, 40, 1, 40, 1, 40, 1, 40, 5, 40, 519, 8, 40, 10, 40, 12, 40, 522, 9, 40, 1, 40, 1, 40, 1, 41, 1, 41, 1, 41, 1, 41, 1, 42, 1, 42, 1, 42, 1, 42, 1, 43, 1, 43, 1, 44, 1, 44, 1, 45, 1, 45, 1, 46, 1, 46, 1, 47, 1, 47, 1, 48, 1, 48, 1, 48, 5, 48, 547, 8, 48, 10, 48, 12, 48, 550, 9, 48, 1, 49, 1, 49, 5, 49, 554, 8, 49, 10, 49, 12, 49, 557, 9, 49, 1, 50, 1, 50, 1, 50, 1, 50, 3, 50, 563, 8, 50, 1, 51, 3, 51, 566, 8, 51, 1, 51, 1, 51, 3, 51, 570, 8, 51, 1, 51, 1, 51, 3, 51, 574, 8, 51, 1, 51, 3, 51, 577, 8, 51, 1, 52, 1, 52, 1, 52, 1, 52, 1, 52, 1, 52, 1, 52, 1, 52, 3, 52, 587, 8, 52, 1, 53, 1, 53, 3, 53, 591, 8, 53, 1, 53, 1, 53, 3, 53, 595, 8, 53, 1, 54, 1, 54, 1, 54, 1, 54, 1, 55, 1, 55, 1, 55, 1, 56, 1, 56, 3, 56, 606, 8, 56, 1, 57, 1, 57, 1, 58, 1, 58, 1, 59, 1, 59, 1, 59, 1, 59, 1, 59, 1, 59, 4, 59, 618, 8, 59, 11, 59, 12, 59, 619, 1, 59, 1, 59, 1, 60, 1, 60, 1, 60, 1, 60, 3, 60, 628, 8, 60, 1, 61, 1, 61, 1, 61, 1, 61, 3, 61, 634, 8, 61, 1, 62, 1, 62, 1, 62, 3, 62, 639, 8, 62, 1, 63, 1, 63, 1, 63, 1, 63, 1, 63, 5, 63, 646, 8, 63, 10, 63, 12, 63, 649, 9, 63, 1, 64, 1, 64, 3, 64, 653, 8, 64, 1, 65, 1, 65, 1, 65, 1, 65, 1, 66, 1, 66, 1, 66, 1, 66, 1, 67, 1, 67, 1, 67, 1, 67, 1, 67, 1, 67, 4, 67, 669, 8, 67, 11, 67, 12, 67, 670, 1, 67, 1, 67, 1, 68, 1, 68, 1, 68, 3, 68, 678, 8, 68, 1, 68, 1, 68, 1, 68, 1, 68, 5, 68, 684, 8, 68, 10, 68, 12, 68, 687, 9, 68, 1, 68, 3, 68, 690, 8, 68, 1, 69, 1, 69, 1, 69, 1, 69, 1, 70, 3, 70, 697, 8, 70, 1, 70, 1, 70, 1, 70, 1, 70, 3, 70, 703, 8, 70, 1, 70, 1, 70, 1, 70, 1, 70, 5, 70, 709, 8, 70, 10, 70, 12, 70, 712, 9, 70, 1, 70, 1, 70, 1, 71, 1, 71, 1, 71, 3, 71, 719, 8, 71, 1, 72, 1, 72, 3, 72, 723, 8, 72, 1, 73, 1, 73, 3, 73, 727, 8, 73, 1, 73, 1, 73, 1, 73, 3, 73, 732, 8, 73, 1, 74, 1, 74, 1, 74, 1, 74, 1, 75, 1, 75, 1, 75, 1, 76, 1, 76, 1, 76, 1, 76, 5, 76, 745, 8, 76, 10, 76, 12, 76, 748, 9, 76, 1, 76, 1, 76, 1, 77, 1, 77, 1, 77, 1, 77, 3, 77, 756, 8, 77, 1, 78, 1, 78, 1, 78, 5, 78, 761, 8, 78, 10, 78, 12, 78, 764, 9, 78, 1, 79, 1, 79, 1, 79, 1, 79, 1, 80, 1, 80, 1, 80, 1, 80, 1, 81, 1, 81, 1, 81, 1, 81, 1, 81, 1, 81, 5, 81, 780, 8, 81, 10, 81, 12, 81, 783, 9, 81, 1, 81, 1, 81, 1, 82, 1, 82, 1, 82, 1, 82, 1, 83, 1, 83, 3, 83, 793, 8, 83, 1, 84, 1, 84, 1, 84, 1, 84, 1, 84, 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582, 575, 1, 0, 0, 0, 582, 579, 1, 0, 0, 0, 583, 103, 1, 0, 0, 0, 584, 585, 3, 96, 48, 0, 585, 586, 5, 15, 0, 0, 586, 587, 3, 106, 53, 0, 587, 593, 1, 0, 0, 0, 588, 589, 3, 96, 48, 0, 589, 590, 5, 15, 0, 0, 590, 591, 3, 108, 54, 0, 591, 593, 1, 0, 0, 0, 592, 584, 1, 0, 0, 0, 592, 588, 1, 0, 0, 0, 593, 105, 1, 0, 0, 0, 594, 597, 3, 114, 57, 0, 595, 597, 5, 125, 0, 0, 596, 594, 1, 0, 0, 0, 596, 595, 1, 0, 0, 0, 597, 600, 1, 0, 0, 0, 598, 599, 5, 115, 0, 0, 599, 601, 3, 112, 56, 0, 600, 598, 1, 0, 0, 0, 600, 601, 1, 0, 0, 0, 601, 107, 1, 0, 0, 0, 602, 603, 5, 74, 0, 0, 603, 604, 5, 115, 0, 0, 604, 605, 5, 125, 0, 0, 605, 109, 1, 0, 0, 0, 606, 607, 3, 116, 58, 0, 607, 608, 5, 125, 0, 0, 608, 111, 1, 0, 0, 0, 609, 612, 3, 94, 47, 0, 610, 612, 3, 46, 23, 0, 611, 609, 1, 0, 0, 0, 611, 610, 1, 0, 0, 0, 612, 113, 1, 0, 0, 0, 613, 614, 7, 19, 0, 0, 614, 115, 1, 0, 0, 0, 615, 616, 7, 20, 0, 0, 616, 117, 1, 0, 0, 0, 617, 618, 5, 77, 0, 0, 618, 619, 5, 125, 0, 0, 619, 623, 5, 2, 0, 0, 620, 621, 3, 120, 60, 0, 621, 622, 5, 1, 0, 0, 622, 624, 1, 0, 0, 0, 623, 620, 1, 0, 0, 0, 624, 625, 1, 0, 0, 0, 625, 623, 1, 0, 0, 0, 625, 626, 1, 0, 0, 0, 626, 627, 1, 0, 0, 0, 627, 628, 5, 3, 0, 0, 628, 119, 1, 0, 0, 0, 629, 634, 3, 122, 61, 0, 630, 634, 3, 126, 63, 0, 631, 634, 3, 130, 65, 0, 632, 634, 3, 132, 66, 0, 633, 629, 1, 0, 0, 0, 633, 630, 1, 0, 0, 0, 633, 631, 1, 0, 0, 0, 633, 632, 1, 0, 0, 0, 634, 121, 1, 0, 0, 0, 635, 636, 5, 81, 0, 0, 636, 637, 5, 115, 0, 0, 637, 639, 3, 124, 62, 0, 638, 640, 3, 64, 32, 0, 639, 638, 1, 0, 0, 0, 639, 640, 1, 0, 0, 0, 640, 123, 1, 0, 0, 0, 641, 645, 3, 36, 18, 0, 642, 645, 7, 21, 0, 0, 643, 645, 3, 68, 34, 0, 644, 641, 1, 0, 0, 0, 644, 642, 1, 0, 0, 0, 644, 643, 1, 0, 0, 0, 645, 125, 1, 0, 0, 0, 646, 647, 5, 69, 0, 0, 647, 648, 5, 115, 0, 0, 648, 653, 3, 128, 64, 0, 649, 650, 5, 103, 0, 0, 650, 652, 3, 128, 64, 0, 651, 649, 1, 0, 0, 0, 652, 655, 1, 0, 0, 0, 653, 651, 1, 0, 0, 0, 653, 654, 1, 0, 0, 0, 654, 127, 1, 0, 0, 0, 655, 653, 1, 0, 0, 0, 656, 659, 3, 34, 17, 0, 657, 659, 7, 22, 0, 0, 658, 656, 1, 0, 0, 0, 658, 657, 1, 0, 0, 0, 659, 129, 1, 0, 0, 0, 660, 661, 5, 72, 0, 0, 661, 662, 5, 115, 0, 0, 662, 663, 3, 46, 23, 0, 663, 131, 1, 0, 0, 0, 664, 665, 5, 71, 0, 0, 665, 666, 5, 115, 0, 0, 666, 667, 5, 70, 0, 0, 667, 133, 1, 0, 0, 0, 668, 669, 5, 73, 0, 0, 669, 670, 5, 125, 0, 0, 670, 674, 5, 2, 0, 0, 671, 672, 3, 136, 68, 0, 672, 673, 5, 1, 0, 0, 673, 675, 1, 0, 0, 0, 674, 671, 1, 0, 0, 0, 675, 676, 1, 0, 0, 0, 676, 674, 1, 0, 0, 0, 676, 677, 1, 0, 0, 0, 677, 678, 1, 0, 0, 0, 678, 679, 5, 3, 0, 0, 679, 135, 1, 0, 0, 0, 680, 683, 5, 125, 0, 0, 681, 682, 5, 115, 0, 0, 682, 684, 3, 46, 23, 0, 683, 681, 1, 0, 0, 0, 683, 684, 1, 0, 0, 0, 684, 695, 1, 0, 0, 0, 685, 691, 5, 2, 0, 0, 686, 687, 3, 138, 69, 0, 687, 688, 5, 1, 0, 0, 688, 690, 1, 0, 0, 0, 689, 686, 1, 0, 0, 0, 690, 693, 1, 0, 0, 0, 691, 689, 1, 0, 0, 0, 691, 692, 1, 0, 0, 0, 692, 694, 1, 0, 0, 0, 693, 691, 1, 0, 0, 0, 694, 696, 5, 3, 0, 0, 695, 685, 1, 0, 0, 0, 695, 696, 1, 0, 0, 0, 696, 137, 1, 0, 0, 0, 697, 698, 5, 125, 0, 0, 698, 699, 5, 115, 0, 0, 699, 700, 3, 46, 23, 0, 700, 139, 1, 0, 0, 0, 701, 703, 5, 67, 0, 0, 702, 701, 1, 0, 0, 0, 702, 703, 1, 0, 0, 0, 703, 704, 1, 0, 0, 0, 704, 705, 5, 79, 0, 0, 705, 708, 5, 125, 0, 0, 706, 707, 5, 10, 0, 0, 707, 709, 5, 125, 0, 0, 708, 706, 1, 0, 0, 0, 708, 709, 1, 0, 0, 0, 709, 710, 1, 0, 0, 0, 710, 716, 5, 2, 0, 0, 711, 712, 3, 142, 71, 0, 712, 713, 5, 1, 0, 0, 713, 715, 1, 0, 0, 0, 714, 711, 1, 0, 0, 0, 715, 718, 1, 0, 0, 0, 716, 714, 1, 0, 0, 0, 716, 717, 1, 0, 0, 0, 717, 719, 1, 0, 0, 0, 718, 716, 1, 0, 0, 0, 719, 720, 5, 3, 0, 0, 720, 141, 1, 0, 0, 0, 721, 722, 3, 144, 72, 0, 722, 724, 5, 125, 0, 0, 723, 725, 3, 64, 32, 0, 724, 723, 1, 0, 0, 0, 724, 725, 1, 0, 0, 0, 725, 143, 1, 0, 0, 0, 726, 729, 3, 66, 33, 0, 727, 729, 3, 34, 17, 0, 728, 726, 1, 0, 0, 0, 728, 727, 1, 0, 0, 0, 729, 145, 1, 0, 0, 0, 730, 732, 3, 148, 74, 0, 731, 733, 3, 156, 78, 0, 732, 731, 1, 0, 0, 0, 732, 733, 1, 0, 0, 0, 733, 738, 1, 0, 0, 0, 734, 735, 3, 150, 75, 0, 735, 736, 3, 156, 78, 0, 736, 738, 1, 0, 0, 0, 737, 730, 1, 0, 0, 0, 737, 734, 1, 0, 0, 0, 738, 147, 1, 0, 0, 0, 739, 740, 5, 71, 0, 0, 740, 741, 5, 125, 0, 0, 741, 742, 3, 152, 76, 0, 742, 149, 1, 0, 0, 0, 743, 744, 5, 71, 0, 0, 744, 745, 3, 152, 76, 0, 745, 151, 1, 0, 0, 0, 746, 752, 5, 2, 0, 0, 747, 748, 3, 154, 77, 0, 748, 749, 5, 1, 0, 0, 749, 751, 1, 0, 0, 0, 750, 747, 1, 0, 0, 0, 751, 754, 1, 0, 0, 0, 752, 750, 1, 0, 0, 0, 752, 753, 1, 0, 0, 0, 753, 755, 1, 0, 0, 0, 754, 752, 1, 0, 0, 0, 755, 756, 5, 3, 0, 0, 756, 153, 1, 0, 0, 0, 757, 762, 3, 158, 79, 0, 758, 762, 3, 160, 80, 0, 759, 762, 3, 162, 81, 0, 760, 762, 3, 164, 82, 0, 761, 757, 1, 0, 0, 0, 761, 758, 1, 0, 0, 0, 761, 759, 1, 0, 0, 0, 761, 760, 1, 0, 0, 0, 762, 155, 1, 0, 0, 0, 763, 768, 5, 125, 0, 0, 764, 765, 5, 4, 0, 0, 765, 767, 5, 125, 0, 0, 766, 764, 1, 0, 0, 0, 767, 770, 1, 0, 0, 0, 768, 766, 1, 0, 0, 0, 768, 769, 1, 0, 0, 0, 769, 157, 1, 0, 0, 0, 770, 768, 1, 0, 0, 0, 771, 772, 3, 46, 23, 0, 772, 773, 7, 23, 0, 0, 773, 774, 3, 46, 23, 0, 774, 159, 1, 0, 0, 0, 775, 776, 5, 125, 0, 0, 776, 777, 5, 115, 0, 0, 777, 778, 3, 46, 23, 0, 778, 161, 1, 0, 0, 0, 779, 780, 3, 166, 83, 0, 780, 781, 5, 75, 0, 0, 781, 782, 5, 2, 0, 0, 782, 787, 3, 168, 84, 0, 783, 784, 5, 4, 0, 0, 784, 786, 3, 168, 84, 0, 785, 783, 1, 0, 0, 0, 786, 789, 1, 0, 0, 0, 787, 785, 1, 0, 0, 0, 787, 788, 1, 0, 0, 0, 788, 790, 1, 0, 0, 0, 789, 787, 1, 0, 0, 0, 790, 791, 5, 3, 0, 0, 791, 163, 1, 0, 0, 0, 792, 793, 3, 166, 83, 0, 793, 794, 5, 75, 0, 0, 794, 795, 5, 125, 0, 0, 795, 165, 1, 0, 0, 0, 796, 799, 5, 80, 0, 0, 797, 799, 3, 96, 48, 0, 798, 796, 1, 0, 0, 0, 798, 797, 1, 0, 0, 0, 799, 167, 1, 0, 0, 0, 800, 808, 3, 46, 23, 0, 801, 802, 5, 12, 0, 0, 802, 803, 3, 46, 23, 0, 803, 804, 5, 10, 0, 0, 804, 805, 3, 46, 23, 0, 805, 806, 5, 13, 0, 0, 806, 808, 1, 0, 0, 0, 807, 800, 1, 0, 0, 0, 807, 801, 1, 0, 0, 0, 808, 169, 1, 0, 0, 0, 74, 175, 191, 198, 200, 207, 217, 220, 223, 234, 247, 259, 262, 269, 276, 279, 282, 285, 288, 291, 309, 320, 328, 332, 341, 356, 397, 399, 411, 419, 445, 449, 466, 470, 473, 484, 489, 505, 510, 524, 529, 554, 561, 568, 571, 575, 579, 582, 592, 596, 600, 611, 625, 633, 639, 644, 653, 658, 676, 683, 691, 695, 702, 708, 716, 724, 728, 732, 737, 752, 761, 768, 787, 798, 807]
\ No newline at end of file
diff --git a/systemrdl/parser/ext/SystemRDLParser.cpp b/systemrdl/parser/ext/SystemRDLParser.cpp
index 234ddc1..1da21ce 100644
--- a/systemrdl/parser/ext/SystemRDLParser.cpp
+++ b/systemrdl/parser/ext/SystemRDLParser.cpp
@@ -116,7 +116,7 @@ void systemrdlParserInitialize() {
     }
   );
   static const int32_t serializedATNSegment[] = {
-  	4,1,125,804,2,0,7,0,2,1,7,1,2,2,7,2,2,3,7,3,2,4,7,4,2,5,7,5,2,6,7,6,2,
+  	4,1,125,810,2,0,7,0,2,1,7,1,2,2,7,2,2,3,7,3,2,4,7,4,2,5,7,5,2,6,7,6,2,
   	7,7,7,2,8,7,8,2,9,7,9,2,10,7,10,2,11,7,11,2,12,7,12,2,13,7,13,2,14,7,
   	14,2,15,7,15,2,16,7,16,2,17,7,17,2,18,7,18,2,19,7,19,2,20,7,20,2,21,7,
   	21,2,22,7,22,2,23,7,23,2,24,7,24,2,25,7,25,2,26,7,26,2,27,7,27,2,28,7,
@@ -154,241 +154,243 @@ void systemrdlParserInitialize() {
   	34,474,8,34,1,35,1,35,1,35,1,35,1,35,1,35,1,35,1,35,1,35,3,35,485,8,35,
   	1,36,1,36,1,36,3,36,490,8,36,1,37,1,37,1,38,1,38,1,39,1,39,1,39,1,39,
   	1,39,1,39,1,39,1,39,5,39,504,8,39,10,39,12,39,507,9,39,1,39,1,39,3,39,
-  	511,8,39,1,40,1,40,1,40,1,40,1,40,1,40,5,40,519,8,40,10,40,12,40,522,
-  	9,40,1,40,1,40,1,41,1,41,1,41,1,41,1,42,1,42,1,42,1,42,1,43,1,43,1,44,
-  	1,44,1,45,1,45,1,46,1,46,1,47,1,47,1,48,1,48,1,48,5,48,547,8,48,10,48,
-  	12,48,550,9,48,1,49,1,49,5,49,554,8,49,10,49,12,49,557,9,49,1,50,1,50,
-  	1,50,1,50,3,50,563,8,50,1,51,3,51,566,8,51,1,51,1,51,3,51,570,8,51,1,
-  	51,1,51,3,51,574,8,51,1,51,3,51,577,8,51,1,52,1,52,1,52,1,52,1,52,1,52,
-  	1,52,1,52,3,52,587,8,52,1,53,1,53,3,53,591,8,53,1,53,1,53,3,53,595,8,
-  	53,1,54,1,54,1,54,1,54,1,55,1,55,1,55,1,56,1,56,3,56,606,8,56,1,57,1,
-  	57,1,58,1,58,1,59,1,59,1,59,1,59,1,59,1,59,4,59,618,8,59,11,59,12,59,
-  	619,1,59,1,59,1,60,1,60,1,60,1,60,3,60,628,8,60,1,61,1,61,1,61,1,61,3,
-  	61,634,8,61,1,62,1,62,1,62,3,62,639,8,62,1,63,1,63,1,63,1,63,1,63,5,63,
-  	646,8,63,10,63,12,63,649,9,63,1,64,1,64,3,64,653,8,64,1,65,1,65,1,65,
-  	1,65,1,66,1,66,1,66,1,66,1,67,1,67,1,67,1,67,1,67,1,67,4,67,669,8,67,
-  	11,67,12,67,670,1,67,1,67,1,68,1,68,1,68,3,68,678,8,68,1,68,1,68,1,68,
-  	1,68,5,68,684,8,68,10,68,12,68,687,9,68,1,68,3,68,690,8,68,1,69,1,69,
-  	1,69,1,69,1,70,3,70,697,8,70,1,70,1,70,1,70,1,70,3,70,703,8,70,1,70,1,
-  	70,1,70,1,70,5,70,709,8,70,10,70,12,70,712,9,70,1,70,1,70,1,71,1,71,1,
-  	71,3,71,719,8,71,1,72,1,72,3,72,723,8,72,1,73,1,73,3,73,727,8,73,1,73,
-  	1,73,1,73,3,73,732,8,73,1,74,1,74,1,74,1,74,1,75,1,75,1,75,1,76,1,76,
-  	1,76,1,76,5,76,745,8,76,10,76,12,76,748,9,76,1,76,1,76,1,77,1,77,1,77,
-  	1,77,3,77,756,8,77,1,78,1,78,1,78,5,78,761,8,78,10,78,12,78,764,9,78,
-  	1,79,1,79,1,79,1,79,1,80,1,80,1,80,1,80,1,81,1,81,1,81,1,81,1,81,1,81,
-  	5,81,780,8,81,10,81,12,81,783,9,81,1,81,1,81,1,82,1,82,1,82,1,82,1,83,
-  	1,83,3,83,793,8,83,1,84,1,84,1,84,1,84,1,84,1,84,1,84,3,84,802,8,84,1,
-  	84,0,1,46,85,0,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,
-  	42,44,46,48,50,52,54,56,58,60,62,64,66,68,70,72,74,76,78,80,82,84,86,
-  	88,90,92,94,96,98,100,102,104,106,108,110,112,114,116,118,120,122,124,
-  	126,128,130,132,134,136,138,140,142,144,146,148,150,152,154,156,158,160,
-  	162,164,166,168,0,24,1,0,28,29,1,0,30,34,3,0,96,99,101,103,105,107,2,
-  	0,110,110,112,113,1,0,96,97,1,0,108,109,1,0,117,120,2,0,114,114,116,116,
-  	1,0,106,107,1,0,18,20,1,0,23,26,1,0,19,20,3,0,18,18,22,22,125,125,1,0,
-  	36,37,1,0,38,44,1,0,45,47,1,0,48,56,1,0,57,59,1,0,60,61,3,0,45,46,48,
-  	49,60,61,1,0,62,66,2,0,76,76,78,78,2,0,68,68,71,71,2,0,114,114,116,120,
-  	836,0,175,1,0,0,0,2,180,1,0,0,0,4,191,1,0,0,0,6,217,1,0,0,0,8,220,1,0,
-  	0,0,10,228,1,0,0,0,12,231,1,0,0,0,14,238,1,0,0,0,16,241,1,0,0,0,18,259,
-  	1,0,0,0,20,262,1,0,0,0,22,272,1,0,0,0,24,293,1,0,0,0,26,296,1,0,0,0,28,
-  	299,1,0,0,0,30,302,1,0,0,0,32,305,1,0,0,0,34,309,1,0,0,0,36,311,1,0,0,
-  	0,38,313,1,0,0,0,40,325,1,0,0,0,42,334,1,0,0,0,44,346,1,0,0,0,46,356,
-  	1,0,0,0,48,411,1,0,0,0,50,413,1,0,0,0,52,424,1,0,0,0,54,429,1,0,0,0,56,
-  	445,1,0,0,0,58,449,1,0,0,0,60,451,1,0,0,0,62,457,1,0,0,0,64,461,1,0,0,
-  	0,66,466,1,0,0,0,68,473,1,0,0,0,70,484,1,0,0,0,72,489,1,0,0,0,74,491,
-  	1,0,0,0,76,493,1,0,0,0,78,510,1,0,0,0,80,512,1,0,0,0,82,525,1,0,0,0,84,
-  	529,1,0,0,0,86,533,1,0,0,0,88,535,1,0,0,0,90,537,1,0,0,0,92,539,1,0,0,
-  	0,94,541,1,0,0,0,96,543,1,0,0,0,98,551,1,0,0,0,100,558,1,0,0,0,102,576,
-  	1,0,0,0,104,586,1,0,0,0,106,590,1,0,0,0,108,596,1,0,0,0,110,600,1,0,0,
-  	0,112,605,1,0,0,0,114,607,1,0,0,0,116,609,1,0,0,0,118,611,1,0,0,0,120,
-  	627,1,0,0,0,122,629,1,0,0,0,124,638,1,0,0,0,126,640,1,0,0,0,128,652,1,
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+  	5,6,0,0,336,341,3,44,22,0,337,338,5,4,0,0,338,340,3,44,22,0,339,337,1,
+  	0,0,0,340,343,1,0,0,0,341,339,1,0,0,0,341,342,1,0,0,0,342,344,1,0,0,0,
+  	343,341,1,0,0,0,344,345,5,7,0,0,345,43,1,0,0,0,346,347,5,8,0,0,347,348,
+  	5,125,0,0,348,349,5,6,0,0,349,350,3,46,23,0,350,351,5,7,0,0,351,45,1,
+  	0,0,0,352,353,6,23,-1,0,353,354,7,2,0,0,354,357,3,48,24,0,355,357,3,48,
+  	24,0,356,352,1,0,0,0,356,355,1,0,0,0,357,399,1,0,0,0,358,359,10,13,0,
+  	0,359,360,5,111,0,0,360,398,3,46,23,14,361,362,10,12,0,0,362,363,7,3,
+  	0,0,363,398,3,46,23,13,364,365,10,11,0,0,365,366,7,4,0,0,366,398,3,46,
+  	23,12,367,368,10,10,0,0,368,369,7,5,0,0,369,398,3,46,23,11,370,371,10,
+  	9,0,0,371,372,7,6,0,0,372,398,3,46,23,10,373,374,10,8,0,0,374,375,7,7,
+  	0,0,375,398,3,46,23,9,376,377,10,7,0,0,377,378,5,102,0,0,378,398,3,46,
+  	23,8,379,380,10,6,0,0,380,381,7,8,0,0,381,398,3,46,23,7,382,383,10,5,
+  	0,0,383,384,5,103,0,0,384,398,3,46,23,6,385,386,10,4,0,0,386,387,5,100,
+  	0,0,387,398,3,46,23,5,388,389,10,3,0,0,389,390,5,104,0,0,390,398,3,46,
+  	23,4,391,392,10,2,0,0,392,393,5,9,0,0,393,394,3,46,23,0,394,395,5,10,
+  	0,0,395,396,3,46,23,2,396,398,1,0,0,0,397,358,1,0,0,0,397,361,1,0,0,0,
+  	397,364,1,0,0,0,397,367,1,0,0,0,397,370,1,0,0,0,397,373,1,0,0,0,397,376,
+  	1,0,0,0,397,379,1,0,0,0,397,382,1,0,0,0,397,385,1,0,0,0,397,388,1,0,0,
+  	0,397,391,1,0,0,0,398,401,1,0,0,0,399,397,1,0,0,0,399,400,1,0,0,0,400,
+  	47,1,0,0,0,401,399,1,0,0,0,402,412,3,70,35,0,403,412,3,50,25,0,404,412,
+  	3,52,26,0,405,412,3,54,27,0,406,412,3,56,28,0,407,412,3,100,50,0,408,
+  	412,3,96,48,0,409,412,3,80,40,0,410,412,3,78,39,0,411,402,1,0,0,0,411,
+  	403,1,0,0,0,411,404,1,0,0,0,411,405,1,0,0,0,411,406,1,0,0,0,411,407,1,
+  	0,0,0,411,408,1,0,0,0,411,409,1,0,0,0,411,410,1,0,0,0,412,49,1,0,0,0,
+  	413,414,5,2,0,0,414,419,3,46,23,0,415,416,5,4,0,0,416,418,3,46,23,0,417,
+  	415,1,0,0,0,418,421,1,0,0,0,419,417,1,0,0,0,419,420,1,0,0,0,420,422,1,
+  	0,0,0,421,419,1,0,0,0,422,423,5,3,0,0,423,51,1,0,0,0,424,425,5,2,0,0,
+  	425,426,3,46,23,0,426,427,3,50,25,0,427,428,5,3,0,0,428,53,1,0,0,0,429,
+  	430,5,6,0,0,430,431,3,46,23,0,431,432,5,7,0,0,432,55,1,0,0,0,433,434,
+  	7,9,0,0,434,435,5,11,0,0,435,436,5,6,0,0,436,437,3,46,23,0,437,438,5,
+  	7,0,0,438,446,1,0,0,0,439,440,3,58,29,0,440,441,5,11,0,0,441,442,5,6,
+  	0,0,442,443,3,46,23,0,443,444,5,7,0,0,444,446,1,0,0,0,445,433,1,0,0,0,
+  	445,439,1,0,0,0,446,57,1,0,0,0,447,450,3,70,35,0,448,450,3,54,27,0,449,
+  	447,1,0,0,0,449,448,1,0,0,0,450,59,1,0,0,0,451,452,5,12,0,0,452,453,3,
+  	46,23,0,453,454,5,10,0,0,454,455,3,46,23,0,455,456,5,13,0,0,456,61,1,
+  	0,0,0,457,458,5,12,0,0,458,459,3,46,23,0,459,460,5,13,0,0,460,63,1,0,
+  	0,0,461,462,5,12,0,0,462,463,5,13,0,0,463,65,1,0,0,0,464,467,3,68,34,
+  	0,465,467,7,10,0,0,466,464,1,0,0,0,466,465,1,0,0,0,467,67,1,0,0,0,468,
+  	470,7,11,0,0,469,471,5,21,0,0,470,469,1,0,0,0,470,471,1,0,0,0,471,474,
+  	1,0,0,0,472,474,7,12,0,0,473,468,1,0,0,0,473,472,1,0,0,0,474,69,1,0,0,
+  	0,475,485,3,72,36,0,476,485,3,74,37,0,477,485,3,76,38,0,478,485,3,86,
+  	43,0,479,485,3,88,44,0,480,485,3,90,45,0,481,485,3,92,46,0,482,485,3,
+  	94,47,0,483,485,3,84,42,0,484,475,1,0,0,0,484,476,1,0,0,0,484,477,1,0,
+  	0,0,484,478,1,0,0,0,484,479,1,0,0,0,484,480,1,0,0,0,484,481,1,0,0,0,484,
+  	482,1,0,0,0,484,483,1,0,0,0,485,71,1,0,0,0,486,490,5,92,0,0,487,490,5,
+  	93,0,0,488,490,5,94,0,0,489,486,1,0,0,0,489,487,1,0,0,0,489,488,1,0,0,
+  	0,490,73,1,0,0,0,491,492,5,95,0,0,492,75,1,0,0,0,493,494,7,13,0,0,494,
+  	77,1,0,0,0,495,496,5,11,0,0,496,497,5,2,0,0,497,511,5,3,0,0,498,499,5,
+  	11,0,0,499,500,5,2,0,0,500,505,3,46,23,0,501,502,5,4,0,0,502,504,3,46,
+  	23,0,503,501,1,0,0,0,504,507,1,0,0,0,505,503,1,0,0,0,505,506,1,0,0,0,
+  	506,508,1,0,0,0,507,505,1,0,0,0,508,509,5,3,0,0,509,511,1,0,0,0,510,495,
+  	1,0,0,0,510,498,1,0,0,0,511,79,1,0,0,0,512,513,5,125,0,0,513,514,5,11,
+  	0,0,514,515,5,2,0,0,515,530,5,3,0,0,516,517,5,125,0,0,517,518,5,11,0,
+  	0,518,519,5,2,0,0,519,524,3,82,41,0,520,521,5,4,0,0,521,523,3,82,41,0,
+  	522,520,1,0,0,0,523,526,1,0,0,0,524,522,1,0,0,0,524,525,1,0,0,0,525,527,
+  	1,0,0,0,526,524,1,0,0,0,527,528,5,3,0,0,528,530,1,0,0,0,529,512,1,0,0,
+  	0,529,516,1,0,0,0,530,81,1,0,0,0,531,532,5,125,0,0,532,533,5,10,0,0,533,
+  	534,3,46,23,0,534,83,1,0,0,0,535,536,5,125,0,0,536,537,5,14,0,0,537,538,
+  	5,125,0,0,538,85,1,0,0,0,539,540,7,14,0,0,540,87,1,0,0,0,541,542,7,15,
+  	0,0,542,89,1,0,0,0,543,544,7,16,0,0,544,91,1,0,0,0,545,546,7,17,0,0,546,
+  	93,1,0,0,0,547,548,7,18,0,0,548,95,1,0,0,0,549,554,3,98,49,0,550,551,
+  	5,8,0,0,551,553,3,98,49,0,552,550,1,0,0,0,553,556,1,0,0,0,554,552,1,0,
+  	0,0,554,555,1,0,0,0,555,97,1,0,0,0,556,554,1,0,0,0,557,561,5,125,0,0,
+  	558,560,3,62,31,0,559,558,1,0,0,0,560,563,1,0,0,0,561,559,1,0,0,0,561,
+  	562,1,0,0,0,562,99,1,0,0,0,563,561,1,0,0,0,564,565,3,96,48,0,565,568,
+  	5,15,0,0,566,569,3,114,57,0,567,569,5,125,0,0,568,566,1,0,0,0,568,567,
+  	1,0,0,0,569,101,1,0,0,0,570,572,5,72,0,0,571,570,1,0,0,0,571,572,1,0,
+  	0,0,572,573,1,0,0,0,573,583,3,106,53,0,574,576,5,72,0,0,575,574,1,0,0,
+  	0,575,576,1,0,0,0,576,577,1,0,0,0,577,583,3,108,54,0,578,580,5,72,0,0,
+  	579,578,1,0,0,0,579,580,1,0,0,0,580,581,1,0,0,0,581,583,3,110,55,0,582,
+  	571,1,0,0,0,582,575,1,0,0,0,582,579,1,0,0,0,583,103,1,0,0,0,584,585,3,
+  	96,48,0,585,586,5,15,0,0,586,587,3,106,53,0,587,593,1,0,0,0,588,589,3,
+  	96,48,0,589,590,5,15,0,0,590,591,3,108,54,0,591,593,1,0,0,0,592,584,1,
+  	0,0,0,592,588,1,0,0,0,593,105,1,0,0,0,594,597,3,114,57,0,595,597,5,125,
+  	0,0,596,594,1,0,0,0,596,595,1,0,0,0,597,600,1,0,0,0,598,599,5,115,0,0,
+  	599,601,3,112,56,0,600,598,1,0,0,0,600,601,1,0,0,0,601,107,1,0,0,0,602,
+  	603,5,74,0,0,603,604,5,115,0,0,604,605,5,125,0,0,605,109,1,0,0,0,606,
+  	607,3,116,58,0,607,608,5,125,0,0,608,111,1,0,0,0,609,612,3,94,47,0,610,
+  	612,3,46,23,0,611,609,1,0,0,0,611,610,1,0,0,0,612,113,1,0,0,0,613,614,
+  	7,19,0,0,614,115,1,0,0,0,615,616,7,20,0,0,616,117,1,0,0,0,617,618,5,77,
+  	0,0,618,619,5,125,0,0,619,623,5,2,0,0,620,621,3,120,60,0,621,622,5,1,
+  	0,0,622,624,1,0,0,0,623,620,1,0,0,0,624,625,1,0,0,0,625,623,1,0,0,0,625,
+  	626,1,0,0,0,626,627,1,0,0,0,627,628,5,3,0,0,628,119,1,0,0,0,629,634,3,
+  	122,61,0,630,634,3,126,63,0,631,634,3,130,65,0,632,634,3,132,66,0,633,
+  	629,1,0,0,0,633,630,1,0,0,0,633,631,1,0,0,0,633,632,1,0,0,0,634,121,1,
+  	0,0,0,635,636,5,81,0,0,636,637,5,115,0,0,637,639,3,124,62,0,638,640,3,
+  	64,32,0,639,638,1,0,0,0,639,640,1,0,0,0,640,123,1,0,0,0,641,645,3,36,
+  	18,0,642,645,7,21,0,0,643,645,3,68,34,0,644,641,1,0,0,0,644,642,1,0,0,
+  	0,644,643,1,0,0,0,645,125,1,0,0,0,646,647,5,69,0,0,647,648,5,115,0,0,
+  	648,653,3,128,64,0,649,650,5,103,0,0,650,652,3,128,64,0,651,649,1,0,0,
+  	0,652,655,1,0,0,0,653,651,1,0,0,0,653,654,1,0,0,0,654,127,1,0,0,0,655,
+  	653,1,0,0,0,656,659,3,34,17,0,657,659,7,22,0,0,658,656,1,0,0,0,658,657,
+  	1,0,0,0,659,129,1,0,0,0,660,661,5,72,0,0,661,662,5,115,0,0,662,663,3,
+  	46,23,0,663,131,1,0,0,0,664,665,5,71,0,0,665,666,5,115,0,0,666,667,5,
+  	70,0,0,667,133,1,0,0,0,668,669,5,73,0,0,669,670,5,125,0,0,670,674,5,2,
+  	0,0,671,672,3,136,68,0,672,673,5,1,0,0,673,675,1,0,0,0,674,671,1,0,0,
+  	0,675,676,1,0,0,0,676,674,1,0,0,0,676,677,1,0,0,0,677,678,1,0,0,0,678,
+  	679,5,3,0,0,679,135,1,0,0,0,680,683,5,125,0,0,681,682,5,115,0,0,682,684,
+  	3,46,23,0,683,681,1,0,0,0,683,684,1,0,0,0,684,695,1,0,0,0,685,691,5,2,
+  	0,0,686,687,3,138,69,0,687,688,5,1,0,0,688,690,1,0,0,0,689,686,1,0,0,
+  	0,690,693,1,0,0,0,691,689,1,0,0,0,691,692,1,0,0,0,692,694,1,0,0,0,693,
+  	691,1,0,0,0,694,696,5,3,0,0,695,685,1,0,0,0,695,696,1,0,0,0,696,137,1,
+  	0,0,0,697,698,5,125,0,0,698,699,5,115,0,0,699,700,3,46,23,0,700,139,1,
+  	0,0,0,701,703,5,67,0,0,702,701,1,0,0,0,702,703,1,0,0,0,703,704,1,0,0,
+  	0,704,705,5,79,0,0,705,708,5,125,0,0,706,707,5,10,0,0,707,709,5,125,0,
+  	0,708,706,1,0,0,0,708,709,1,0,0,0,709,710,1,0,0,0,710,716,5,2,0,0,711,
+  	712,3,142,71,0,712,713,5,1,0,0,713,715,1,0,0,0,714,711,1,0,0,0,715,718,
+  	1,0,0,0,716,714,1,0,0,0,716,717,1,0,0,0,717,719,1,0,0,0,718,716,1,0,0,
+  	0,719,720,5,3,0,0,720,141,1,0,0,0,721,722,3,144,72,0,722,724,5,125,0,
+  	0,723,725,3,64,32,0,724,723,1,0,0,0,724,725,1,0,0,0,725,143,1,0,0,0,726,
+  	729,3,66,33,0,727,729,3,34,17,0,728,726,1,0,0,0,728,727,1,0,0,0,729,145,
+  	1,0,0,0,730,732,3,148,74,0,731,733,3,156,78,0,732,731,1,0,0,0,732,733,
+  	1,0,0,0,733,738,1,0,0,0,734,735,3,150,75,0,735,736,3,156,78,0,736,738,
+  	1,0,0,0,737,730,1,0,0,0,737,734,1,0,0,0,738,147,1,0,0,0,739,740,5,71,
+  	0,0,740,741,5,125,0,0,741,742,3,152,76,0,742,149,1,0,0,0,743,744,5,71,
+  	0,0,744,745,3,152,76,0,745,151,1,0,0,0,746,752,5,2,0,0,747,748,3,154,
+  	77,0,748,749,5,1,0,0,749,751,1,0,0,0,750,747,1,0,0,0,751,754,1,0,0,0,
+  	752,750,1,0,0,0,752,753,1,0,0,0,753,755,1,0,0,0,754,752,1,0,0,0,755,756,
+  	5,3,0,0,756,153,1,0,0,0,757,762,3,158,79,0,758,762,3,160,80,0,759,762,
+  	3,162,81,0,760,762,3,164,82,0,761,757,1,0,0,0,761,758,1,0,0,0,761,759,
+  	1,0,0,0,761,760,1,0,0,0,762,155,1,0,0,0,763,768,5,125,0,0,764,765,5,4,
+  	0,0,765,767,5,125,0,0,766,764,1,0,0,0,767,770,1,0,0,0,768,766,1,0,0,0,
+  	768,769,1,0,0,0,769,157,1,0,0,0,770,768,1,0,0,0,771,772,3,46,23,0,772,
+  	773,7,23,0,0,773,774,3,46,23,0,774,159,1,0,0,0,775,776,5,125,0,0,776,
+  	777,5,115,0,0,777,778,3,46,23,0,778,161,1,0,0,0,779,780,3,166,83,0,780,
+  	781,5,75,0,0,781,782,5,2,0,0,782,787,3,168,84,0,783,784,5,4,0,0,784,786,
+  	3,168,84,0,785,783,1,0,0,0,786,789,1,0,0,0,787,785,1,0,0,0,787,788,1,
+  	0,0,0,788,790,1,0,0,0,789,787,1,0,0,0,790,791,5,3,0,0,791,163,1,0,0,0,
+  	792,793,3,166,83,0,793,794,5,75,0,0,794,795,5,125,0,0,795,165,1,0,0,0,
+  	796,799,5,80,0,0,797,799,3,96,48,0,798,796,1,0,0,0,798,797,1,0,0,0,799,
+  	167,1,0,0,0,800,808,3,46,23,0,801,802,5,12,0,0,802,803,3,46,23,0,803,
+  	804,5,10,0,0,804,805,3,46,23,0,805,806,5,13,0,0,806,808,1,0,0,0,807,800,
+  	1,0,0,0,807,801,1,0,0,0,808,169,1,0,0,0,74,175,191,198,200,207,217,220,
+  	223,234,247,259,262,269,276,279,282,285,288,291,309,320,328,332,341,356,
+  	397,399,411,419,445,449,466,470,473,484,489,505,510,524,529,554,561,568,
+  	571,575,579,582,592,596,600,611,625,633,639,644,653,658,676,683,691,695,
+  	702,708,716,724,728,732,737,752,761,768,787,798,807
   };
   staticData->serializedATN = antlr4::atn::SerializedATNView(serializedATNSegment, sizeof(serializedATNSegment) / sizeof(serializedATNSegment[0]));
 
@@ -4325,29 +4327,52 @@ SystemRDLParser::Struct_literalContext* SystemRDLParser::struct_literal() {
     exitRule();
   });
   try {
-    enterOuterAlt(_localctx, 1);
-    setState(512);
-    match(SystemRDLParser::ID);
-    setState(513);
-    match(SystemRDLParser::T__10);
-    setState(514);
-    match(SystemRDLParser::T__1);
-    setState(515);
-    struct_kv();
-    setState(520);
+    setState(529);
     _errHandler->sync(this);
-    _la = _input->LA(1);
-    while (_la == SystemRDLParser::T__3) {
+    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 39, _ctx)) {
+    case 1: {
+      enterOuterAlt(_localctx, 1);
+      setState(512);
+      match(SystemRDLParser::ID);
+      setState(513);
+      match(SystemRDLParser::T__10);
+      setState(514);
+      match(SystemRDLParser::T__1);
+      setState(515);
+      match(SystemRDLParser::T__2);
+      break;
+    }
+
+    case 2: {
+      enterOuterAlt(_localctx, 2);
       setState(516);
-      match(SystemRDLParser::T__3);
+      match(SystemRDLParser::ID);
       setState(517);
+      match(SystemRDLParser::T__10);
+      setState(518);
+      match(SystemRDLParser::T__1);
+      setState(519);
       struct_kv();
-      setState(522);
+      setState(524);
       _errHandler->sync(this);
       _la = _input->LA(1);
+      while (_la == SystemRDLParser::T__3) {
+        setState(520);
+        match(SystemRDLParser::T__3);
+        setState(521);
+        struct_kv();
+        setState(526);
+        _errHandler->sync(this);
+        _la = _input->LA(1);
+      }
+      setState(527);
+      match(SystemRDLParser::T__2);
+      break;
+    }
+
+    default:
+      break;
     }
-    setState(523);
-    match(SystemRDLParser::T__2);
    
   }
   catch (RecognitionException &e) {
@@ -4399,11 +4424,11 @@ SystemRDLParser::Struct_kvContext* SystemRDLParser::struct_kv() {
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(525);
+    setState(531);
     match(SystemRDLParser::ID);
-    setState(526);
+    setState(532);
     match(SystemRDLParser::T__9);
-    setState(527);
+    setState(533);
     expr(0);
    
   }
@@ -4456,11 +4481,11 @@ SystemRDLParser::Enum_literalContext* SystemRDLParser::enum_literal() {
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(529);
+    setState(535);
     match(SystemRDLParser::ID);
-    setState(530);
+    setState(536);
     match(SystemRDLParser::T__13);
-    setState(531);
+    setState(537);
     match(SystemRDLParser::ID);
    
   }
@@ -4534,7 +4559,7 @@ SystemRDLParser::Accesstype_literalContext* SystemRDLParser::accesstype_literal(
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(533);
+    setState(539);
     antlrcpp::downCast<Accesstype_literalContext *>(_localctx)->kw = _input->LT(1);
     _la = _input->LA(1);
     if (!((((_la & ~ 0x3fULL) == 0) &&
@@ -4601,7 +4626,7 @@ SystemRDLParser::Onreadtype_literalContext* SystemRDLParser::onreadtype_literal(
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(535);
+    setState(541);
     antlrcpp::downCast<Onreadtype_literalContext *>(_localctx)->kw = _input->LT(1);
     _la = _input->LA(1);
     if (!((((_la & ~ 0x3fULL) == 0) &&
@@ -4692,7 +4717,7 @@ SystemRDLParser::Onwritetype_literalContext* SystemRDLParser::onwritetype_litera
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(537);
+    setState(543);
     antlrcpp::downCast<Onwritetype_literalContext *>(_localctx)->kw = _input->LT(1);
     _la = _input->LA(1);
     if (!((((_la & ~ 0x3fULL) == 0) &&
@@ -4759,7 +4784,7 @@ SystemRDLParser::Addressingtype_literalContext* SystemRDLParser::addressingtype_
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(539);
+    setState(545);
     antlrcpp::downCast<Addressingtype_literalContext *>(_localctx)->kw = _input->LT(1);
     _la = _input->LA(1);
     if (!((((_la & ~ 0x3fULL) == 0) &&
@@ -4822,7 +4847,7 @@ SystemRDLParser::Precedencetype_literalContext* SystemRDLParser::precedencetype_
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(541);
+    setState(547);
     antlrcpp::downCast<Precedencetype_literalContext *>(_localctx)->kw = _input->LT(1);
     _la = _input->LA(1);
     if (!(_la == SystemRDLParser::HW_kw
@@ -4886,21 +4911,21 @@ SystemRDLParser::Instance_refContext* SystemRDLParser::instance_ref() {
   try {
     size_t alt;
     enterOuterAlt(_localctx, 1);
-    setState(543);
+    setState(549);
     instance_ref_element();
-    setState(548);
+    setState(554);
     _errHandler->sync(this);
-    alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 39, _ctx);
+    alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 40, _ctx);
     while (alt != 2 && alt != atn::ATN::INVALID_ALT_NUMBER) {
       if (alt == 1) {
-        setState(544);
+        setState(550);
         match(SystemRDLParser::T__7);
-        setState(545);
+        setState(551);
         instance_ref_element(); 
       }
-      setState(550);
+      setState(556);
       _errHandler->sync(this);
-      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 39, _ctx);
+      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 40, _ctx);
     }
    
   }
@@ -4958,19 +4983,19 @@ SystemRDLParser::Instance_ref_elementContext* SystemRDLParser::instance_ref_elem
   try {
     size_t alt;
     enterOuterAlt(_localctx, 1);
-    setState(551);
+    setState(557);
     match(SystemRDLParser::ID);
-    setState(555);
+    setState(561);
     _errHandler->sync(this);
-    alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 40, _ctx);
+    alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 41, _ctx);
     while (alt != 2 && alt != atn::ATN::INVALID_ALT_NUMBER) {
       if (alt == 1) {
-        setState(552);
+        setState(558);
         array_suffix(); 
       }
-      setState(557);
+      setState(563);
       _errHandler->sync(this);
-      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 40, _ctx);
+      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 41, _ctx);
     }
    
   }
@@ -5027,11 +5052,11 @@ SystemRDLParser::Prop_refContext* SystemRDLParser::prop_ref() {
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(558);
+    setState(564);
     instance_ref();
-    setState(559);
+    setState(565);
     match(SystemRDLParser::T__14);
-    setState(562);
+    setState(568);
     _errHandler->sync(this);
     switch (_input->LA(1)) {
       case SystemRDLParser::RCLR_kw:
@@ -5040,13 +5065,13 @@ SystemRDLParser::Prop_refContext* SystemRDLParser::prop_ref() {
       case SystemRDLParser::WOCLR_kw:
       case SystemRDLParser::HW_kw:
       case SystemRDLParser::SW_kw: {
-        setState(560);
+        setState(566);
         prop_keyword();
         break;
       }
 
       case SystemRDLParser::ID: {
-        setState(561);
+        setState(567);
         match(SystemRDLParser::ID);
         break;
       }
@@ -5113,50 +5138,50 @@ SystemRDLParser::Local_property_assignmentContext* SystemRDLParser::local_proper
     exitRule();
   });
   try {
-    setState(576);
+    setState(582);
     _errHandler->sync(this);
-    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 45, _ctx)) {
+    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 46, _ctx)) {
     case 1: {
       enterOuterAlt(_localctx, 1);
-      setState(565);
+      setState(571);
       _errHandler->sync(this);
 
       _la = _input->LA(1);
       if (_la == SystemRDLParser::DEFAULT_kw) {
-        setState(564);
+        setState(570);
         match(SystemRDLParser::DEFAULT_kw);
       }
-      setState(567);
+      setState(573);
       normal_prop_assign();
       break;
     }
 
     case 2: {
       enterOuterAlt(_localctx, 2);
-      setState(569);
+      setState(575);
       _errHandler->sync(this);
 
       _la = _input->LA(1);
       if (_la == SystemRDLParser::DEFAULT_kw) {
-        setState(568);
+        setState(574);
         match(SystemRDLParser::DEFAULT_kw);
       }
-      setState(571);
+      setState(577);
       encode_prop_assign();
       break;
     }
 
     case 3: {
       enterOuterAlt(_localctx, 3);
-      setState(573);
+      setState(579);
       _errHandler->sync(this);
 
       _la = _input->LA(1);
       if (_la == SystemRDLParser::DEFAULT_kw) {
-        setState(572);
+        setState(578);
         match(SystemRDLParser::DEFAULT_kw);
       }
-      setState(575);
+      setState(581);
       prop_mod_assign();
       break;
     }
@@ -5218,27 +5243,27 @@ SystemRDLParser::Dynamic_property_assignmentContext* SystemRDLParser::dynamic_pr
     exitRule();
   });
   try {
-    setState(586);
+    setState(592);
     _errHandler->sync(this);
-    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 46, _ctx)) {
+    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 47, _ctx)) {
     case 1: {
       enterOuterAlt(_localctx, 1);
-      setState(578);
+      setState(584);
       instance_ref();
-      setState(579);
+      setState(585);
       match(SystemRDLParser::T__14);
-      setState(580);
+      setState(586);
       normal_prop_assign();
       break;
     }
 
     case 2: {
       enterOuterAlt(_localctx, 2);
-      setState(582);
+      setState(588);
       instance_ref();
-      setState(583);
+      setState(589);
       match(SystemRDLParser::T__14);
-      setState(584);
+      setState(590);
       encode_prop_assign();
       break;
     }
@@ -5306,7 +5331,7 @@ SystemRDLParser::Normal_prop_assignContext* SystemRDLParser::normal_prop_assign(
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(590);
+    setState(596);
     _errHandler->sync(this);
     switch (_input->LA(1)) {
       case SystemRDLParser::RCLR_kw:
@@ -5315,13 +5340,13 @@ SystemRDLParser::Normal_prop_assignContext* SystemRDLParser::normal_prop_assign(
       case SystemRDLParser::WOCLR_kw:
       case SystemRDLParser::HW_kw:
       case SystemRDLParser::SW_kw: {
-        setState(588);
+        setState(594);
         prop_keyword();
         break;
       }
 
       case SystemRDLParser::ID: {
-        setState(589);
+        setState(595);
         match(SystemRDLParser::ID);
         break;
       }
@@ -5329,14 +5354,14 @@ SystemRDLParser::Normal_prop_assignContext* SystemRDLParser::normal_prop_assign(
     default:
       throw NoViableAltException(this);
     }
-    setState(594);
+    setState(600);
     _errHandler->sync(this);
 
     _la = _input->LA(1);
     if (_la == SystemRDLParser::ASSIGN) {
-      setState(592);
+      setState(598);
       match(SystemRDLParser::ASSIGN);
-      setState(593);
+      setState(599);
       prop_assignment_rhs();
     }
    
@@ -5394,11 +5419,11 @@ SystemRDLParser::Encode_prop_assignContext* SystemRDLParser::encode_prop_assign(
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(596);
+    setState(602);
     match(SystemRDLParser::ENCODE_kw);
-    setState(597);
+    setState(603);
     match(SystemRDLParser::ASSIGN);
-    setState(598);
+    setState(604);
     match(SystemRDLParser::ID);
    
   }
@@ -5451,9 +5476,9 @@ SystemRDLParser::Prop_mod_assignContext* SystemRDLParser::prop_mod_assign() {
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(600);
+    setState(606);
     prop_mod();
-    setState(601);
+    setState(607);
     match(SystemRDLParser::ID);
    
   }
@@ -5505,19 +5530,19 @@ SystemRDLParser::Prop_assignment_rhsContext* SystemRDLParser::prop_assignment_rh
     exitRule();
   });
   try {
-    setState(605);
+    setState(611);
     _errHandler->sync(this);
-    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 49, _ctx)) {
+    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 50, _ctx)) {
     case 1: {
       enterOuterAlt(_localctx, 1);
-      setState(603);
+      setState(609);
       precedencetype_literal();
       break;
     }
 
     case 2: {
       enterOuterAlt(_localctx, 2);
-      setState(604);
+      setState(610);
       expr(0);
       break;
     }
@@ -5593,7 +5618,7 @@ SystemRDLParser::Prop_keywordContext* SystemRDLParser::prop_keyword() {
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(607);
+    setState(613);
     antlrcpp::downCast<Prop_keywordContext *>(_localctx)->kw = _input->LT(1);
     _la = _input->LA(1);
     if (!((((_la & ~ 0x3fULL) == 0) &&
@@ -5668,7 +5693,7 @@ SystemRDLParser::Prop_modContext* SystemRDLParser::prop_mod() {
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(609);
+    setState(615);
     antlrcpp::downCast<Prop_modContext *>(_localctx)->kw = _input->LT(1);
     _la = _input->LA(1);
     if (!(((((_la - 62) & ~ 0x3fULL) == 0) &&
@@ -5739,26 +5764,26 @@ SystemRDLParser::Udp_defContext* SystemRDLParser::udp_def() {
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(611);
+    setState(617);
     match(SystemRDLParser::PROPERTY_kw);
-    setState(612);
+    setState(618);
     match(SystemRDLParser::ID);
-    setState(613);
+    setState(619);
     match(SystemRDLParser::T__1);
-    setState(617); 
+    setState(623); 
     _errHandler->sync(this);
     _la = _input->LA(1);
     do {
-      setState(614);
+      setState(620);
       udp_attr();
-      setState(615);
+      setState(621);
       match(SystemRDLParser::T__0);
-      setState(619); 
+      setState(625); 
       _errHandler->sync(this);
       _la = _input->LA(1);
     } while (((((_la - 69) & ~ 0x3fULL) == 0) &&
       ((1ULL << (_la - 69)) & 4109) != 0));
-    setState(621);
+    setState(627);
     match(SystemRDLParser::T__2);
    
   }
@@ -5818,33 +5843,33 @@ SystemRDLParser::Udp_attrContext* SystemRDLParser::udp_attr() {
     exitRule();
   });
   try {
-    setState(627);
+    setState(633);
     _errHandler->sync(this);
     switch (_input->LA(1)) {
       case SystemRDLParser::TYPE_kw: {
         enterOuterAlt(_localctx, 1);
-        setState(623);
+        setState(629);
         udp_type();
         break;
       }
 
       case SystemRDLParser::COMPONENT_kw: {
         enterOuterAlt(_localctx, 2);
-        setState(624);
+        setState(630);
         udp_usage();
         break;
       }
 
       case SystemRDLParser::DEFAULT_kw: {
         enterOuterAlt(_localctx, 3);
-        setState(625);
+        setState(631);
         udp_default();
         break;
       }
 
       case SystemRDLParser::CONSTRAINT_kw: {
         enterOuterAlt(_localctx, 4);
-        setState(626);
+        setState(632);
         udp_constraint();
         break;
       }
@@ -5912,18 +5937,18 @@ SystemRDLParser::Udp_typeContext* SystemRDLParser::udp_type() {
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(629);
+    setState(635);
     match(SystemRDLParser::TYPE_kw);
-    setState(630);
+    setState(636);
     match(SystemRDLParser::ASSIGN);
-    setState(631);
+    setState(637);
     udp_data_type();
-    setState(633);
+    setState(639);
     _errHandler->sync(this);
 
     _la = _input->LA(1);
     if (_la == SystemRDLParser::T__11) {
-      setState(632);
+      setState(638);
       array_type_suffix();
     }
    
@@ -5985,7 +6010,7 @@ SystemRDLParser::Udp_data_typeContext* SystemRDLParser::udp_data_type() {
     exitRule();
   });
   try {
-    setState(638);
+    setState(644);
     _errHandler->sync(this);
     switch (_input->LA(1)) {
       case SystemRDLParser::ADDRMAP_kw:
@@ -5994,7 +6019,7 @@ SystemRDLParser::Udp_data_typeContext* SystemRDLParser::udp_data_type() {
       case SystemRDLParser::FIELD_kw:
       case SystemRDLParser::MEM_kw: {
         enterOuterAlt(_localctx, 1);
-        setState(635);
+        setState(641);
         component_type_primary();
         break;
       }
@@ -6002,7 +6027,7 @@ SystemRDLParser::Udp_data_typeContext* SystemRDLParser::udp_data_type() {
       case SystemRDLParser::NUMBER_kw:
       case SystemRDLParser::REF_kw: {
         enterOuterAlt(_localctx, 2);
-        setState(636);
+        setState(642);
         antlrcpp::downCast<Udp_data_typeContext *>(_localctx)->kw = _input->LT(1);
         _la = _input->LA(1);
         if (!(_la == SystemRDLParser::NUMBER_kw
@@ -6023,7 +6048,7 @@ SystemRDLParser::Udp_data_typeContext* SystemRDLParser::udp_data_type() {
       case SystemRDLParser::STRING_kw:
       case SystemRDLParser::ID: {
         enterOuterAlt(_localctx, 3);
-        setState(637);
+        setState(643);
         basic_data_type();
         break;
       }
@@ -6099,21 +6124,21 @@ SystemRDLParser::Udp_usageContext* SystemRDLParser::udp_usage() {
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(640);
+    setState(646);
     match(SystemRDLParser::COMPONENT_kw);
-    setState(641);
+    setState(647);
     match(SystemRDLParser::ASSIGN);
-    setState(642);
+    setState(648);
     udp_comp_type();
-    setState(647);
+    setState(653);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SystemRDLParser::OR) {
-      setState(643);
+      setState(649);
       match(SystemRDLParser::OR);
-      setState(644);
+      setState(650);
       udp_comp_type();
-      setState(649);
+      setState(655);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
@@ -6172,7 +6197,7 @@ SystemRDLParser::Udp_comp_typeContext* SystemRDLParser::udp_comp_type() {
     exitRule();
   });
   try {
-    setState(652);
+    setState(658);
     _errHandler->sync(this);
     switch (_input->LA(1)) {
       case SystemRDLParser::ADDRMAP_kw:
@@ -6182,7 +6207,7 @@ SystemRDLParser::Udp_comp_typeContext* SystemRDLParser::udp_comp_type() {
       case SystemRDLParser::MEM_kw:
       case SystemRDLParser::SIGNAL_kw: {
         enterOuterAlt(_localctx, 1);
-        setState(650);
+        setState(656);
         component_type();
         break;
       }
@@ -6190,7 +6215,7 @@ SystemRDLParser::Udp_comp_typeContext* SystemRDLParser::udp_comp_type() {
       case SystemRDLParser::ALL_kw:
       case SystemRDLParser::CONSTRAINT_kw: {
         enterOuterAlt(_localctx, 2);
-        setState(651);
+        setState(657);
         antlrcpp::downCast<Udp_comp_typeContext *>(_localctx)->kw = _input->LT(1);
         _la = _input->LA(1);
         if (!(_la == SystemRDLParser::ALL_kw
@@ -6263,11 +6288,11 @@ SystemRDLParser::Udp_defaultContext* SystemRDLParser::udp_default() {
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(654);
+    setState(660);
     match(SystemRDLParser::DEFAULT_kw);
-    setState(655);
+    setState(661);
     match(SystemRDLParser::ASSIGN);
-    setState(656);
+    setState(662);
     expr(0);
    
   }
@@ -6324,11 +6349,11 @@ SystemRDLParser::Udp_constraintContext* SystemRDLParser::udp_constraint() {
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(658);
+    setState(664);
     match(SystemRDLParser::CONSTRAINT_kw);
-    setState(659);
+    setState(665);
     match(SystemRDLParser::ASSIGN);
-    setState(660);
+    setState(666);
     match(SystemRDLParser::COMPONENTWIDTH_kw);
    
   }
@@ -6390,25 +6415,25 @@ SystemRDLParser::Enum_defContext* SystemRDLParser::enum_def() {
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(662);
+    setState(668);
     match(SystemRDLParser::ENUM_kw);
-    setState(663);
+    setState(669);
     match(SystemRDLParser::ID);
-    setState(664);
+    setState(670);
     match(SystemRDLParser::T__1);
-    setState(668); 
+    setState(674); 
     _errHandler->sync(this);
     _la = _input->LA(1);
     do {
-      setState(665);
+      setState(671);
       enum_entry();
-      setState(666);
+      setState(672);
       match(SystemRDLParser::T__0);
-      setState(670); 
+      setState(676); 
       _errHandler->sync(this);
       _la = _input->LA(1);
     } while (_la == SystemRDLParser::ID);
-    setState(672);
+    setState(678);
     match(SystemRDLParser::T__2);
    
   }
@@ -6474,38 +6499,38 @@ SystemRDLParser::Enum_entryContext* SystemRDLParser::enum_entry() {
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(674);
+    setState(680);
     match(SystemRDLParser::ID);
-    setState(677);
+    setState(683);
     _errHandler->sync(this);
 
     _la = _input->LA(1);
     if (_la == SystemRDLParser::ASSIGN) {
-      setState(675);
+      setState(681);
       match(SystemRDLParser::ASSIGN);
-      setState(676);
+      setState(682);
       expr(0);
     }
-    setState(689);
+    setState(695);
     _errHandler->sync(this);
 
     _la = _input->LA(1);
     if (_la == SystemRDLParser::T__1) {
-      setState(679);
-      match(SystemRDLParser::T__1);
       setState(685);
+      match(SystemRDLParser::T__1);
+      setState(691);
       _errHandler->sync(this);
       _la = _input->LA(1);
       while (_la == SystemRDLParser::ID) {
-        setState(680);
+        setState(686);
         enum_prop_assign();
-        setState(681);
-        match(SystemRDLParser::T__0);
         setState(687);
+        match(SystemRDLParser::T__0);
+        setState(693);
         _errHandler->sync(this);
         _la = _input->LA(1);
       }
-      setState(688);
+      setState(694);
       match(SystemRDLParser::T__2);
     }
    
@@ -6563,11 +6588,11 @@ SystemRDLParser::Enum_prop_assignContext* SystemRDLParser::enum_prop_assign() {
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(691);
+    setState(697);
     match(SystemRDLParser::ID);
-    setState(692);
+    setState(698);
     match(SystemRDLParser::ASSIGN);
-    setState(693);
+    setState(699);
     expr(0);
    
   }
@@ -6637,44 +6662,44 @@ SystemRDLParser::Struct_defContext* SystemRDLParser::struct_def() {
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(696);
+    setState(702);
     _errHandler->sync(this);
 
     _la = _input->LA(1);
     if (_la == SystemRDLParser::ABSTRACT_kw) {
-      setState(695);
+      setState(701);
       match(SystemRDLParser::ABSTRACT_kw);
     }
-    setState(698);
+    setState(704);
     match(SystemRDLParser::STRUCT_kw);
-    setState(699);
+    setState(705);
     antlrcpp::downCast<Struct_defContext *>(_localctx)->name = match(SystemRDLParser::ID);
-    setState(702);
+    setState(708);
     _errHandler->sync(this);
 
     _la = _input->LA(1);
     if (_la == SystemRDLParser::T__9) {
-      setState(700);
+      setState(706);
       match(SystemRDLParser::T__9);
-      setState(701);
+      setState(707);
       antlrcpp::downCast<Struct_defContext *>(_localctx)->base = match(SystemRDLParser::ID);
     }
-    setState(704);
-    match(SystemRDLParser::T__1);
     setState(710);
+    match(SystemRDLParser::T__1);
+    setState(716);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while ((((_la & ~ 0x3fULL) == 0) &&
       ((1ULL << _la) & 67777593344) != 0) || _la == SystemRDLParser::ID) {
-      setState(705);
+      setState(711);
       struct_elem();
-      setState(706);
-      match(SystemRDLParser::T__0);
       setState(712);
+      match(SystemRDLParser::T__0);
+      setState(718);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(713);
+    setState(719);
     match(SystemRDLParser::T__2);
    
   }
@@ -6732,16 +6757,16 @@ SystemRDLParser::Struct_elemContext* SystemRDLParser::struct_elem() {
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(715);
+    setState(721);
     struct_type();
-    setState(716);
+    setState(722);
     match(SystemRDLParser::ID);
-    setState(718);
+    setState(724);
     _errHandler->sync(this);
 
     _la = _input->LA(1);
     if (_la == SystemRDLParser::T__11) {
-      setState(717);
+      setState(723);
       array_type_suffix();
     }
    
@@ -6794,7 +6819,7 @@ SystemRDLParser::Struct_typeContext* SystemRDLParser::struct_type() {
     exitRule();
   });
   try {
-    setState(722);
+    setState(728);
     _errHandler->sync(this);
     switch (_input->LA(1)) {
       case SystemRDLParser::BOOLEAN_kw:
@@ -6807,7 +6832,7 @@ SystemRDLParser::Struct_typeContext* SystemRDLParser::struct_type() {
       case SystemRDLParser::ONWRITETYPE_kw:
       case SystemRDLParser::ID: {
         enterOuterAlt(_localctx, 1);
-        setState(720);
+        setState(726);
         data_type();
         break;
       }
@@ -6819,7 +6844,7 @@ SystemRDLParser::Struct_typeContext* SystemRDLParser::struct_type() {
       case SystemRDLParser::MEM_kw:
       case SystemRDLParser::SIGNAL_kw: {
         enterOuterAlt(_localctx, 2);
-        setState(721);
+        setState(727);
         component_type();
         break;
       }
@@ -6882,19 +6907,19 @@ SystemRDLParser::Constraint_defContext* SystemRDLParser::constraint_def() {
     exitRule();
   });
   try {
-    setState(731);
+    setState(737);
     _errHandler->sync(this);
-    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 66, _ctx)) {
+    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 67, _ctx)) {
     case 1: {
       enterOuterAlt(_localctx, 1);
-      setState(724);
+      setState(730);
       constraint_named_def();
-      setState(726);
+      setState(732);
       _errHandler->sync(this);
 
       _la = _input->LA(1);
       if (_la == SystemRDLParser::ID) {
-        setState(725);
+        setState(731);
         constraint_insts();
       }
       break;
@@ -6902,9 +6927,9 @@ SystemRDLParser::Constraint_defContext* SystemRDLParser::constraint_def() {
 
     case 2: {
       enterOuterAlt(_localctx, 2);
-      setState(728);
+      setState(734);
       constraint_anon_def();
-      setState(729);
+      setState(735);
       constraint_insts();
       break;
     }
@@ -6967,11 +6992,11 @@ SystemRDLParser::Constraint_named_defContext* SystemRDLParser::constraint_named_
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(733);
+    setState(739);
     match(SystemRDLParser::CONSTRAINT_kw);
-    setState(734);
+    setState(740);
     match(SystemRDLParser::ID);
-    setState(735);
+    setState(741);
     constraint_body();
    
   }
@@ -7024,9 +7049,9 @@ SystemRDLParser::Constraint_anon_defContext* SystemRDLParser::constraint_anon_de
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(737);
+    setState(743);
     match(SystemRDLParser::CONSTRAINT_kw);
-    setState(738);
+    setState(744);
     constraint_body();
    
   }
@@ -7080,23 +7105,23 @@ SystemRDLParser::Constraint_bodyContext* SystemRDLParser::constraint_body() {
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(740);
-    match(SystemRDLParser::T__1);
     setState(746);
+    match(SystemRDLParser::T__1);
+    setState(752);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while ((((_la & ~ 0x3fULL) == 0) &&
       ((1ULL << _la) & 4611685949709748292) != 0) || ((((_la - 80) & ~ 0x3fULL) == 0) &&
       ((1ULL << (_la - 80)) & 35184622694401) != 0)) {
-      setState(741);
+      setState(747);
       constraint_body_elem();
-      setState(742);
-      match(SystemRDLParser::T__0);
       setState(748);
+      match(SystemRDLParser::T__0);
+      setState(754);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(749);
+    setState(755);
     match(SystemRDLParser::T__2);
    
   }
@@ -7156,33 +7181,33 @@ SystemRDLParser::Constraint_body_elemContext* SystemRDLParser::constraint_body_e
     exitRule();
   });
   try {
-    setState(755);
+    setState(761);
     _errHandler->sync(this);
-    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 68, _ctx)) {
+    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 69, _ctx)) {
     case 1: {
       enterOuterAlt(_localctx, 1);
-      setState(751);
+      setState(757);
       constr_relational();
       break;
     }
 
     case 2: {
       enterOuterAlt(_localctx, 2);
-      setState(752);
+      setState(758);
       constr_prop_assign();
       break;
     }
 
     case 3: {
       enterOuterAlt(_localctx, 3);
-      setState(753);
+      setState(759);
       constr_inside_values();
       break;
     }
 
     case 4: {
       enterOuterAlt(_localctx, 4);
-      setState(754);
+      setState(760);
       constr_inside_enum();
       break;
     }
@@ -7242,17 +7267,17 @@ SystemRDLParser::Constraint_instsContext* SystemRDLParser::constraint_insts() {
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(757);
+    setState(763);
     match(SystemRDLParser::ID);
-    setState(762);
+    setState(768);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SystemRDLParser::T__3) {
-      setState(758);
+      setState(764);
       match(SystemRDLParser::T__3);
-      setState(759);
+      setState(765);
       match(SystemRDLParser::ID);
-      setState(764);
+      setState(770);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
@@ -7332,9 +7357,9 @@ SystemRDLParser::Constr_relationalContext* SystemRDLParser::constr_relational()
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(765);
+    setState(771);
     expr(0);
-    setState(766);
+    setState(772);
     antlrcpp::downCast<Constr_relationalContext *>(_localctx)->op = _input->LT(1);
     _la = _input->LA(1);
     if (!(((((_la - 114) & ~ 0x3fULL) == 0) &&
@@ -7345,7 +7370,7 @@ SystemRDLParser::Constr_relationalContext* SystemRDLParser::constr_relational()
       _errHandler->reportMatch(this);
       consume();
     }
-    setState(767);
+    setState(773);
     expr(0);
    
   }
@@ -7402,11 +7427,11 @@ SystemRDLParser::Constr_prop_assignContext* SystemRDLParser::constr_prop_assign(
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(769);
+    setState(775);
     match(SystemRDLParser::ID);
-    setState(770);
+    setState(776);
     match(SystemRDLParser::ASSIGN);
-    setState(771);
+    setState(777);
     expr(0);
    
   }
@@ -7468,27 +7493,27 @@ SystemRDLParser::Constr_inside_valuesContext* SystemRDLParser::constr_inside_val
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(773);
+    setState(779);
     constr_lhs();
-    setState(774);
+    setState(780);
     match(SystemRDLParser::INSIDE_kw);
-    setState(775);
+    setState(781);
     match(SystemRDLParser::T__1);
-    setState(776);
+    setState(782);
     constr_inside_value();
-    setState(781);
+    setState(787);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SystemRDLParser::T__3) {
-      setState(777);
+      setState(783);
       match(SystemRDLParser::T__3);
-      setState(778);
+      setState(784);
       constr_inside_value();
-      setState(783);
+      setState(789);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(784);
+    setState(790);
     match(SystemRDLParser::T__2);
    
   }
@@ -7545,11 +7570,11 @@ SystemRDLParser::Constr_inside_enumContext* SystemRDLParser::constr_inside_enum(
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(786);
+    setState(792);
     constr_lhs();
-    setState(787);
+    setState(793);
     match(SystemRDLParser::INSIDE_kw);
-    setState(788);
+    setState(794);
     match(SystemRDLParser::ID);
    
   }
@@ -7601,19 +7626,19 @@ SystemRDLParser::Constr_lhsContext* SystemRDLParser::constr_lhs() {
     exitRule();
   });
   try {
-    setState(792);
+    setState(798);
     _errHandler->sync(this);
     switch (_input->LA(1)) {
       case SystemRDLParser::THIS_kw: {
         enterOuterAlt(_localctx, 1);
-        setState(790);
+        setState(796);
         match(SystemRDLParser::THIS_kw);
         break;
       }
 
       case SystemRDLParser::ID: {
         enterOuterAlt(_localctx, 2);
-        setState(791);
+        setState(797);
         instance_ref();
         break;
       }
@@ -7671,7 +7696,7 @@ SystemRDLParser::Constr_inside_valueContext* SystemRDLParser::constr_inside_valu
     exitRule();
   });
   try {
-    setState(801);
+    setState(807);
     _errHandler->sync(this);
     switch (_input->LA(1)) {
       case SystemRDLParser::T__1:
@@ -7722,22 +7747,22 @@ SystemRDLParser::Constr_inside_valueContext* SystemRDLParser::constr_inside_valu
       case SystemRDLParser::XNOR:
       case SystemRDLParser::ID: {
         enterOuterAlt(_localctx, 1);
-        setState(794);
+        setState(800);
         antlrcpp::downCast<Constr_inside_valueContext *>(_localctx)->val = expr(0);
         break;
       }
 
       case SystemRDLParser::T__11: {
         enterOuterAlt(_localctx, 2);
-        setState(795);
+        setState(801);
         match(SystemRDLParser::T__11);
-        setState(796);
+        setState(802);
         antlrcpp::downCast<Constr_inside_valueContext *>(_localctx)->l_val = expr(0);
-        setState(797);
+        setState(803);
         match(SystemRDLParser::T__9);
-        setState(798);
+        setState(804);
         antlrcpp::downCast<Constr_inside_valueContext *>(_localctx)->r_val = expr(0);
-        setState(799);
+        setState(805);
         match(SystemRDLParser::T__12);
         break;
       }
diff --git a/systemrdl/parser/ext/sa_systemrdl_cpp_parser.cpp b/systemrdl/parser/ext/sa_systemrdl_cpp_parser.cpp
index ab65611..b695ba8 100644
--- a/systemrdl/parser/ext/sa_systemrdl_cpp_parser.cpp
+++ b/systemrdl/parser/ext/sa_systemrdl_cpp_parser.cpp
@@ -1,5 +1,5 @@
 /*
- * This file was auto-generated by speedy-antlr-tool v1.4.1
+ * This file was auto-generated by speedy-antlr-tool v1.4.3
  *  https://github.com/amykyta3/speedy-antlr-tool
  */
 
diff --git a/systemrdl/parser/ext/sa_systemrdl_translator.cpp b/systemrdl/parser/ext/sa_systemrdl_translator.cpp
index a1881c7..6bc95bc 100644
--- a/systemrdl/parser/ext/sa_systemrdl_translator.cpp
+++ b/systemrdl/parser/ext/sa_systemrdl_translator.cpp
@@ -1,5 +1,5 @@
 /*
- * This file was auto-generated by speedy-antlr-tool v1.4.1
+ * This file was auto-generated by speedy-antlr-tool v1.4.3
  *  https://github.com/amykyta3/speedy-antlr-tool
  */
 
diff --git a/systemrdl/parser/ext/sa_systemrdl_translator.h b/systemrdl/parser/ext/sa_systemrdl_translator.h
index 2d2d083..1e3a021 100644
--- a/systemrdl/parser/ext/sa_systemrdl_translator.h
+++ b/systemrdl/parser/ext/sa_systemrdl_translator.h
@@ -1,5 +1,5 @@
 /*
- * This file was auto-generated by speedy-antlr-tool v1.4.1
+ * This file was auto-generated by speedy-antlr-tool v1.4.3
  *  https://github.com/amykyta3/speedy-antlr-tool
  */
 
diff --git a/systemrdl/parser/ext/speedy_antlr.cpp b/systemrdl/parser/ext/speedy_antlr.cpp
index 88b7ea5..f0eafab 100644
--- a/systemrdl/parser/ext/speedy_antlr.cpp
+++ b/systemrdl/parser/ext/speedy_antlr.cpp
@@ -1,5 +1,5 @@
 /*
- * This file was auto-generated by speedy-antlr-tool v1.4.1
+ * This file was auto-generated by speedy-antlr-tool v1.4.3
  *  https://github.com/amykyta3/speedy-antlr-tool
  */
 
diff --git a/systemrdl/parser/ext/speedy_antlr.h b/systemrdl/parser/ext/speedy_antlr.h
index d0e3ef7..941ca9c 100644
--- a/systemrdl/parser/ext/speedy_antlr.h
+++ b/systemrdl/parser/ext/speedy_antlr.h
@@ -1,5 +1,5 @@
 /*
- * This file was auto-generated by speedy-antlr-tool v1.4.1
+ * This file was auto-generated by speedy-antlr-tool v1.4.3
  *  https://github.com/amykyta3/speedy-antlr-tool
  */
 
diff --git a/systemrdl/parser/sa_systemrdl.py b/systemrdl/parser/sa_systemrdl.py
index 8a8e4f6..7ce73af 100644
--- a/systemrdl/parser/sa_systemrdl.py
+++ b/systemrdl/parser/sa_systemrdl.py
@@ -1,4 +1,4 @@
-# This file was auto-generated by speedy-antlr-tool v1.4.1
+# This file was auto-generated by speedy-antlr-tool v1.4.3
 #  https://github.com/amykyta3/speedy-antlr-tool
 
 import sys
diff --git a/test/rdl_err_src/err_incomplete_struct.rdl b/test/rdl_err_src/err_incomplete_struct.rdl
new file mode 100644
index 0000000..d8ae6b1
--- /dev/null
+++ b/test/rdl_err_src/err_incomplete_struct.rdl
@@ -0,0 +1,17 @@
+struct struct_t {
+    boolean a;
+    longint b;
+};
+
+property struct_prop {
+    type = struct_t;
+    component = field;
+};
+
+addrmap top {
+    reg {
+        field {
+            struct_prop = struct_t'{a: true};
+        } f;
+    } reg_error;
+};
diff --git a/test/rdl_src/incomplete_struct.rdl b/test/rdl_src/incomplete_struct.rdl
new file mode 100644
index 0000000..c43bfd7
--- /dev/null
+++ b/test/rdl_src/incomplete_struct.rdl
@@ -0,0 +1,21 @@
+struct struct_t {
+    boolean x;
+    boolean a;
+    string b;
+    accesstype c;
+    addressingtype d;
+    longint e[];
+};
+
+property struct_prop {
+    type = struct_t;
+    component = field;
+};
+
+addrmap top {
+    reg {
+        field {
+            struct_prop = struct_t'{};
+        } f1;
+    } r1;
+};
diff --git a/test/test_errors.py b/test/test_errors.py
index 8d67839..9a56fcd 100644
--- a/test/test_errors.py
+++ b/test/test_errors.py
@@ -68,6 +68,13 @@ def test_bad_mem_child(self):
             r"Definitions of 'addrmap' components not allowed inside a mem definition"
         )
 
+    def test_incomplete_struct(self):
+        self.assertRDLCompileError(
+            ["rdl_err_src/err_incomplete_struct.rdl"],
+            None,
+            r"Incomplete struct literal 'struct_t'. The following members are undefined: b"
+        )
+
 
 class TestUserErrors(RDLSourceTestCase):
     def setUp(self):
diff --git a/test/test_structs.py b/test/test_structs.py
index dd84eb3..742d76e 100644
--- a/test/test_structs.py
+++ b/test/test_structs.py
@@ -124,3 +124,16 @@ def test_struct_pickleable(self):
             self.assertEqual(struct._is_abstract, struct2._is_abstract)
             self.assertIs(type(struct).__class__, type(struct2).__class__)
             self.assertIs(type(struct).__module__, type(struct2).__module__)
+
+    def test_incomplete_struct(self):
+        root = self.compile(
+            ["rdl_src/incomplete_struct.rdl"],
+            "top"
+        )
+
+        struct = root.find_by_path("top.r1.f1").get_property('struct_prop')
+        self.assertEqual(struct.a, False)
+        self.assertEqual(struct.b, "")
+        self.assertEqual(struct.c, rdlt.AccessType.rw)
+        self.assertEqual(struct.d, rdlt.AddressingType.regalign)
+        self.assertEqual(struct.e, [])