1.18.0

New Features

• Add FieldNode.is_hw_readable/writable (#84)
• Add RegNode.has_hw_readable/writable (#87/#88)

1.17.0

New Features

• Add dim kwarg to Node.get_path() array suffix formatters. #80

Bug Fixes

• Fix calculation of mem component size. #78

1.16.0

Updates

• Add official importer API that formalizes the process of constructing register model objects from external sources. Also include an example for reference. #66

1.15.1

Bug Fixes

• Fix we, wel, hwset and hwclr properties to allow assignments of signal and field references. (#73)

1.15.0

Deprecation

• Add deprecation warning to Node.add_derived_property(). (#68)

Updates

• Remove unnecessary white styling from console messages (#71)
• Improve error message for illegal RHS property reference (#70)
• Add missed validation of reference widths for some properties
• Validate that singlepulse fields are sw writable
• Extend missing reset validation to also check runtime-constant fields for a reset
• Revise validation of swwe/swwel properties. (#43)

Bug Fixes

• Fix quirk where dynamic assignment to an imported component breaks extended DPA type name resolution

1.14.0

New Features

• Update Antlr runtime to v4.9

1.13.2

Bug Fixes

• Fix ability to reference parameter from any enclosing namespace. Found some more examples from the spec author that suggest I had originally misinterpreted namespace rules. New behavior is in-line with spec author's intent.

1.13.1

Bug Fixes

• Fix Verilog Preprocessor regression when checking for trailing text after include directives in files that use Windows CRLF newlines (#65)
• Fix Verilog Preprocessor bug when processing macro text in files that use Windows CRLF newlines (#65)
• Fix missed check on Verilog Preprocessor's conditional state when processing macro expansion and undef directives. (#64)

1.13.0

New Features

• Implement Verilog Preprocessor. (#41, #59)
• Drop support for Python v3.4 (#61)
• Implement better source reference tracking for property assignments.
• Refactored source reference infrastructure.

Bug Fixes

• Fix missing inferred address placement of registers inside mem. (#52)
• Misc error handling bugs/quirks.

1.12.0

New Features

• Add include_native and include_udp options to Node.list_properties(). (#45)
• Add RDLCompiler.list_udps(). (#45)
• Add Node.owning_addrmap property.
• Add ability to use parent operators in Node.find_by_path(). (Related to #48)

Bug Fixes

• Fix validation bug when assigning a signal to the reset value. (#44)
• Fix interaction of swwe and swwel properties with sw property. (#43)
• Fix propagation of boolean type in UDP default. (#45)
• Make littleendian and bigendian properties logically exclusive.
• Add hierarchy separator between parent operators when getting relative path. (#48)
• Fix Component.get_scope_path() to return None if scope is not known.