Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Overhaul Linter Handling of Black-boxed Verilog Models #1929

Merged
merged 18 commits into from
Aug 31, 2023
Merged

Overhaul Linter Handling of Black-boxed Verilog Models #1929

merged 18 commits into from
Aug 31, 2023

Conversation

kareefardi
Copy link
Collaborator

@kareefardi kareefardi commented Aug 3, 2023 •
edited by donn
Loading 

+ add `generate_blackbox_verilog` that generates a header file from a listof files
+ add `scripts/synth/blackbox.tcl` for `generate_blackbox_verilog`
+ use `generate_blackbox_verilog` with `VERILOG_FILES_BLACKBOX` and PDK verilog models
+ disable `UNDRIVEN` and `UNUSEDSIGNAL` for PDK verilog files
+ add `YOSYS_IN`, `YOSYS_OUT`, `YOSYS_DEFINES` which are used in blackbox.tcl
 to internal variables in ci variables documentation workflow 
~ enable `LINTER_INCLUDE_PDK_MODELS`

@kareefardi kareefardi marked this pull request as ready for review August 8, 2023 21:51
@kareefardi kareefardi requested a review from donn August 10, 2023 14:12
@donn
Copy link
Collaborator

donn commented Aug 10, 2023

Aren't we waiting on the PDK for this?

@kareefardi
Copy link
Collaborator Author

Aren't we waiting on the PDK for this?

The PDK was updated yesterday

donn
donn reviewed Aug 15, 2023
View reviewed changes
scripts/tcl_commands/synthesis.tcl Outdated Show resolved Hide resolved
scripts/tcl_commands/synthesis.tcl Outdated Show resolved Hide resolved
donn
donn approved these changes Aug 30, 2023
View reviewed changes
Copy link
Collaborator

@donn donn left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM

@donn donn changed the title Better linter handling of blackbox verilog modules Overhaul Linter Handling of Black-boxed Verilog Models Aug 31, 2023
@donn donn merged commit 3376e5f into The-OpenROAD-Project:master Aug 31, 2023
28 checks passed
@donn donn mentioned this pull request Sep 20, 2023
Closed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@donn donn donn approved these changes

Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
2 participants
@kareefardi @donn