[IHP sg13g2] IO pin access problem on the chip right side only

[lanserge]

Describe the bug

Global routing failed reporting congestion at the right side IO cells only. However there is no real congestion.
With some experimentation I could say that removing OBS from IO cells in LEF results in successful routing, but those OBS are actually on opposite side of IO cell and are not obstacles for routing. And actually other sides of the chip have same IO and routed without issue. Looks like some issue related to the cells orientation in the OpenROAD with determining pin access.

Expected Behavior

All sides of the chip routed.

Environment

kernel: Linux 6.10.11+bpo-amd64
os: Debian GNU/Linux 12 (bookworm)
cmake version 3.30.5
-- The CXX compiler identification is GNU 12.2.0
-- Detecting CXX compiler ABI info
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-- Check for working CXX compiler: /usr/bin/c++ - skipped
-- Detecting CXX compile features
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-- OpenROAD version: v2.0-16972-g32d202458
-- System name: Linux
-- Compiler: GNU 12.2.0
-- Build type: RELEASE
-- Install prefix: /usr/local
-- C++ Standard: 17
-- C++ Standard Required: ON
-- C++ Extensions: OFF
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-- TCL library: /usr/lib/x86_64-linux-gnu/libtcl.so
-- TCL header: /usr/include/tcl/tcl.h
-- TCL readline library: /usr/lib/x86_64-linux-gnu/libtclreadline.so
-- TCL readline header: /usr/include/x86_64-linux-gnu
-- Found SWIG: /usr/bin/swig4.0 (found suitable version "4.1.0", minimum required is "4.0")
-- Using SWIG >= 4.1.0 -flatstaticmethod flag for python
-- Found Boost: /usr/lib/x86_64-linux-gnu/cmake/Boost-1.81.0/BoostConfig.cmake (found version "1.81.0")
-- boost: 1.81.0
-- Found GTest: /usr/lib/x86_64-linux-gnu/cmake/GTest/GTestConfig.cmake (found version "1.12.1")
-- GTest: 1.12.1
-- Found Python3: /usr/include/python3.11 (found version "3.11.2") found components: Development Development.Module Development.Embed
-- Found ZLIB: /usr/lib/x86_64-linux-gnu/libz.so (found version "1.2.13")
-- Found Threads: TRUE
-- spdlog: 1.10.0
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-- Found Doxygen: /usr/bin/doxygen (found version "1.9.4") found components: doxygen missing components: dot
-- STA version: 2.6.0
-- STA git sha: aa598a2f14c5c142e90391a69988523505e7db3d
-- System name: Linux
-- Compiler: GNU 12.2.0
-- Build type: RELEASE
-- Build CXX_FLAGS: -O3 -DNDEBUG
-- Install prefix: /usr/local
-- Found FLEX: /usr/bin/flex (found version "2.6.4")
-- TCL library: /usr/lib/x86_64-linux-gnu/libtcl.so
-- TCL header: /usr/include/tcl/tcl.h
-- TCL readline library: /usr/lib/x86_64-linux-gnu/libtclreadline.so
-- TCL readline header: /usr/include/x86_64-linux-gnu/tclreadline.h
-- CUDD library: not found
-- SSTA: 0
-- Found SWIG: /usr/bin/swig4.0 (found suitable version "4.1.0", minimum required is "3.0")
-- STA executable: /home/serge/projects/chipflow-backend-tools/tools/src/openroad/src/sta/app/sta
-- Found re2: /home/serge/projects/chipflow-backend-tools/tools/or-tools/lib/cmake/re2/re2Config.cmake (found version "11.0.0")
-- Found Clp: /home/serge/projects/chipflow-backend-tools/tools/or-tools/lib/cmake/Clp/ClpConfig.cmake (found version "1.17.7")
-- Found Cbc: /home/serge/projects/chipflow-backend-tools/tools/or-tools/lib/cmake/Cbc/CbcConfig.cmake (found version "2.10.7")
-- Found SCIP: /home/serge/projects/chipflow-backend-tools/tools/or-tools/lib/cmake/scip/scip-config.cmake (found version "9.0.0")
-- Found OpenMP_CXX: -fopenmp (found version "4.5")
-- Found OpenMP: TRUE (found version "4.5")
-- Found OR-Tools: /home/serge/projects/chipflow-backend-tools/tools/or-tools/lib/cmake/ortools (version: 9.11.4210)
-- TCL library: /usr/lib/x86_64-linux-gnu/libtcl.so
-- TCL header: /usr/include/tcl/tcl.h
-- Found OpenMP_C: -fopenmp (found version "4.5")
-- Found OpenMP: TRUE (found version "4.5")
-- Found OpenMP: TRUE (found version "4.5")
-- GUI is enabled
-- Number of processor cores: 4
-- Found Boost: /usr/lib/x86_64-linux-gnu/cmake/Boost-1.81.0/BoostConfig.cmake (found version "1.81.0") found components: serialization
-- Could NOT find VTune (missing: VTune_LIBRARIES VTune_INCLUDE_DIRS) 
-- Found Boost: /usr/lib/x86_64-linux-gnu/cmake/Boost-1.81.0/BoostConfig.cmake (found suitable version "1.81.0", minimum required is "1.78")
-- TCL library: /usr/lib/x86_64-linux-gnu/libtcl.so
-- TCL header: /usr/include/tcl/tcl.h
-- Found Boost: /usr/lib/x86_64-linux-gnu/cmake/Boost-1.81.0/BoostConfig.cmake (found version "1.81.0") found components: serialization system thread
-- Found Boost: /usr/lib/x86_64-linux-gnu/cmake/Boost-1.81.0/BoostConfig.cmake (found version "1.81.0")
-- Found Eigen3: /home/serge/projects/chipflow-backend-tools/tools/or-tools/share/eigen3/cmake/Eigen3Config.cmake (found version "3.4.0")
-- TCL readline enabled
-- Tcl Extended disabled
-- Python3 enabled
-- Configuring done (5.8s)
-- Generating done (0.9s)

To Reproduce

5_1_grt.zip
Unzip attached archive (it contains all the dependencies), from inside 5_1_grt folder run make.
The global routing will fail, produced files for analysis will be 5_1_grt/results/5_1_grt-failed.odb and 5_1_grt/reports/congestion.rpt

Relevant log output

No response

Screenshots

Additional Context

No response

[lanserge]

May be this will be of help: it some kind of related to Metal2 layer, as removing all the OBS only on this layer from IO LEF results in success. The questions are still the same: why chip right side only and why this cause congestion as those Metal2 OBS rectangles are on opposite side of pin routing.