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freeway.tan.rpt
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freeway.tan.rpt
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Classic Timing Analyzer report for freeway
Mon Jul 08 16:37:57 2019
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Parallel Compilation
6. Clock Setup: 'clock'
7. Clock Hold: 'clock'
8. tsu
9. tco
10. th
11. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-------------------------------+------------------------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-------------------------------+------------------------------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 4.200 ns ; Baixo ; debounce:inst11|my_dff:d1|Q ; -- ; clock ; 0 ;
; Worst-case tco ; N/A ; None ; 17.100 ns ; inst5 ; Rout ; clock ; -- ; 0 ;
; Worst-case th ; N/A ; None ; 1.000 ns ; Cima ; debounce:inst9|my_dff:d1|Q ; -- ; clock ; 0 ;
; Clock Setup: 'clock' ; N/A ; None ; 20.24 MHz ( period = 49.400 ns ) ; render:inst1|linha_galinha[4] ; render:inst1|linha_galinha[5] ; clock ; clock ; 0 ;
; Clock Hold: 'clock' ; Not operational: Clock Skew > Data Delay ; None ; N/A ; debounce:inst11|my_dff:d1|Q ; input_synchronizer:inst13|sync_reg ; clock ; clock ; 1 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 1 ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-------------------------------+------------------------------------+------------+----------+--------------+
+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPF10K20RC240-4 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Minimum Core Junction Temperature ; 0 ; ; ; ;
; Maximum Core Junction Temperature ; 85 ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; Off ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
; Output I/O Timing Endpoint ; Near End ; ; ; ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock' ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 20.24 MHz ( period = 49.400 ns ) ; render:inst1|linha_galinha[4] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 46.100 ns ;
; N/A ; 20.45 MHz ( period = 48.900 ns ) ; render:inst1|linha_galinha[6] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 45.300 ns ;
; N/A ; 20.53 MHz ( period = 48.700 ns ) ; render:inst1|linha_galinha[5] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 45.100 ns ;
; N/A ; 20.62 MHz ( period = 48.500 ns ) ; render:inst1|coluna_carro1[4] ; inst5 ; clock ; clock ; None ; None ; 39.400 ns ;
; N/A ; 20.66 MHz ( period = 48.400 ns ) ; render:inst1|linha_galinha[7] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 45.100 ns ;
; N/A ; 20.75 MHz ( period = 48.200 ns ) ; render:inst1|coluna_carro1[5] ; inst5 ; clock ; clock ; None ; None ; 39.100 ns ;
; N/A ; 20.92 MHz ( period = 47.800 ns ) ; render:inst1|linha_galinha[2] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 44.300 ns ;
; N/A ; 21.01 MHz ( period = 47.600 ns ) ; render:inst1|linha_galinha[8] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 44.000 ns ;
; N/A ; 21.05 MHz ( period = 47.500 ns ) ; render:inst1|linha_galinha[3] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 44.000 ns ;
; N/A ; 21.14 MHz ( period = 47.300 ns ) ; render:inst1|coluna_carro1[8] ; inst5 ; clock ; clock ; None ; None ; 38.200 ns ;
; N/A ; 21.19 MHz ( period = 47.200 ns ) ; render:inst1|coluna_carro1[3] ; inst5 ; clock ; clock ; None ; None ; 38.100 ns ;
; N/A ; 21.19 MHz ( period = 47.200 ns ) ; render:inst1|linha_galinha[4] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 43.600 ns ;
; N/A ; 21.19 MHz ( period = 47.200 ns ) ; render:inst1|linha_galinha[4] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 43.600 ns ;
; N/A ; 21.23 MHz ( period = 47.100 ns ) ; render:inst1|coluna_carro1_2[6] ; inst5 ; clock ; clock ; None ; None ; 38.000 ns ;
; N/A ; 21.23 MHz ( period = 47.100 ns ) ; render:inst1|coluna_carro1[4] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 43.800 ns ;
; N/A ; 21.28 MHz ( period = 47.000 ns ) ; render:inst1|coluna_carro1_2[8] ; inst5 ; clock ; clock ; None ; None ; 37.900 ns ;
; N/A ; 21.37 MHz ( period = 46.800 ns ) ; render:inst1|coluna_carro1_2[7] ; inst5 ; clock ; clock ; None ; None ; 37.700 ns ;
; N/A ; 21.37 MHz ( period = 46.800 ns ) ; render:inst1|coluna_carro1[5] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 43.500 ns ;
; N/A ; 21.37 MHz ( period = 46.800 ns ) ; render:inst1|linha_galinha[4] ; render:inst1|linha_galinha[8] ; clock ; clock ; None ; None ; 43.500 ns ;
; N/A ; 21.41 MHz ( period = 46.700 ns ) ; render:inst1|linha_galinha[6] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 42.800 ns ;
; N/A ; 21.41 MHz ( period = 46.700 ns ) ; render:inst1|linha_galinha[6] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 42.800 ns ;
; N/A ; 21.51 MHz ( period = 46.500 ns ) ; render:inst1|linha_galinha[5] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 42.600 ns ;
; N/A ; 21.51 MHz ( period = 46.500 ns ) ; render:inst1|linha_galinha[5] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 42.600 ns ;
; N/A ; 21.55 MHz ( period = 46.400 ns ) ; render:inst1|coluna_carro1_2[3] ; inst5 ; clock ; clock ; None ; None ; 37.300 ns ;
; N/A ; 21.55 MHz ( period = 46.400 ns ) ; render:inst1|linha_galinha[4] ; render:inst1|linha_galinha[3] ; clock ; clock ; None ; None ; 43.000 ns ;
; N/A ; 21.55 MHz ( period = 46.400 ns ) ; render:inst1|linha_galinha[4] ; render:inst1|linha_galinha[2] ; clock ; clock ; None ; None ; 43.000 ns ;
; N/A ; 21.60 MHz ( period = 46.300 ns ) ; render:inst1|coluna_carro1[6] ; inst5 ; clock ; clock ; None ; None ; 37.200 ns ;
; N/A ; 21.60 MHz ( period = 46.300 ns ) ; render:inst1|coluna_carro1[10] ; inst5 ; clock ; clock ; None ; None ; 37.200 ns ;
; N/A ; 21.60 MHz ( period = 46.300 ns ) ; render:inst1|linha_galinha[4] ; render:inst1|linha_galinha[6] ; clock ; clock ; None ; None ; 43.000 ns ;
; N/A ; 21.60 MHz ( period = 46.300 ns ) ; render:inst1|linha_galinha[6] ; render:inst1|linha_galinha[8] ; clock ; clock ; None ; None ; 42.700 ns ;
; N/A ; 21.65 MHz ( period = 46.200 ns ) ; render:inst1|coluna_carro1[9] ; inst5 ; clock ; clock ; None ; None ; 37.100 ns ;
; N/A ; 21.65 MHz ( period = 46.200 ns ) ; render:inst1|linha_galinha[7] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 42.600 ns ;
; N/A ; 21.65 MHz ( period = 46.200 ns ) ; render:inst1|linha_galinha[7] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 42.600 ns ;
; N/A ; 21.69 MHz ( period = 46.100 ns ) ; render:inst1|coluna_carro1_2[9] ; inst5 ; clock ; clock ; None ; None ; 37.000 ns ;
; N/A ; 21.69 MHz ( period = 46.100 ns ) ; render:inst1|coluna_carro1_2[4] ; inst5 ; clock ; clock ; None ; None ; 37.000 ns ;
; N/A ; 21.69 MHz ( period = 46.100 ns ) ; render:inst1|linha_galinha[5] ; render:inst1|linha_galinha[8] ; clock ; clock ; None ; None ; 42.500 ns ;
; N/A ; 21.74 MHz ( period = 46.000 ns ) ; render:inst1|coluna_carro1[7] ; inst5 ; clock ; clock ; None ; None ; 36.900 ns ;
; N/A ; 21.74 MHz ( period = 46.000 ns ) ; render:inst1|coluna_carro1[11] ; inst5 ; clock ; clock ; None ; None ; 36.900 ns ;
; N/A ; 21.79 MHz ( period = 45.900 ns ) ; render:inst1|coluna_carro1[8] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 42.600 ns ;
; N/A ; 21.79 MHz ( period = 45.900 ns ) ; render:inst1|linha_galinha[6] ; render:inst1|linha_galinha[3] ; clock ; clock ; None ; None ; 42.200 ns ;
; N/A ; 21.79 MHz ( period = 45.900 ns ) ; render:inst1|linha_galinha[6] ; render:inst1|linha_galinha[2] ; clock ; clock ; None ; None ; 42.200 ns ;
; N/A ; 21.83 MHz ( period = 45.800 ns ) ; render:inst1|coluna_carro1_2[5] ; inst5 ; clock ; clock ; None ; None ; 36.700 ns ;
; N/A ; 21.83 MHz ( period = 45.800 ns ) ; render:inst1|coluna_carro1[3] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 42.500 ns ;
; N/A ; 21.83 MHz ( period = 45.800 ns ) ; render:inst1|linha_galinha[6] ; render:inst1|linha_galinha[6] ; clock ; clock ; None ; None ; 42.200 ns ;
; N/A ; 21.83 MHz ( period = 45.800 ns ) ; render:inst1|linha_galinha[7] ; render:inst1|linha_galinha[8] ; clock ; clock ; None ; None ; 42.500 ns ;
; N/A ; 21.88 MHz ( period = 45.700 ns ) ; render:inst1|coluna_carro1_2[10] ; inst5 ; clock ; clock ; None ; None ; 36.600 ns ;
; N/A ; 21.88 MHz ( period = 45.700 ns ) ; render:inst1|coluna_carro1[12] ; inst5 ; clock ; clock ; None ; None ; 36.600 ns ;
; N/A ; 21.88 MHz ( period = 45.700 ns ) ; render:inst1|linha_galinha[5] ; render:inst1|linha_galinha[3] ; clock ; clock ; None ; None ; 42.000 ns ;
; N/A ; 21.88 MHz ( period = 45.700 ns ) ; render:inst1|linha_galinha[5] ; render:inst1|linha_galinha[2] ; clock ; clock ; None ; None ; 42.000 ns ;
; N/A ; 21.93 MHz ( period = 45.600 ns ) ; render:inst1|linha_galinha[2] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 41.800 ns ;
; N/A ; 21.93 MHz ( period = 45.600 ns ) ; render:inst1|linha_galinha[2] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 41.800 ns ;
; N/A ; 21.93 MHz ( period = 45.600 ns ) ; render:inst1|linha_galinha[5] ; render:inst1|linha_galinha[6] ; clock ; clock ; None ; None ; 42.000 ns ;
; N/A ; 21.98 MHz ( period = 45.500 ns ) ; render:inst1|coluna_carro1[13] ; inst5 ; clock ; clock ; None ; None ; 36.400 ns ;
; N/A ; 22.03 MHz ( period = 45.400 ns ) ; render:inst1|coluna_carro1_2[11] ; inst5 ; clock ; clock ; None ; None ; 36.300 ns ;
; N/A ; 22.03 MHz ( period = 45.400 ns ) ; render:inst1|linha_galinha[8] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 41.500 ns ;
; N/A ; 22.03 MHz ( period = 45.400 ns ) ; render:inst1|linha_galinha[7] ; render:inst1|linha_galinha[3] ; clock ; clock ; None ; None ; 42.000 ns ;
; N/A ; 22.03 MHz ( period = 45.400 ns ) ; render:inst1|linha_galinha[8] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 41.500 ns ;
; N/A ; 22.03 MHz ( period = 45.400 ns ) ; render:inst1|linha_galinha[7] ; render:inst1|linha_galinha[2] ; clock ; clock ; None ; None ; 42.000 ns ;
; N/A ; 22.08 MHz ( period = 45.300 ns ) ; render:inst1|linha_galinha[3] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 41.500 ns ;
; N/A ; 22.08 MHz ( period = 45.300 ns ) ; render:inst1|linha_galinha[3] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 41.500 ns ;
; N/A ; 22.08 MHz ( period = 45.300 ns ) ; render:inst1|linha_galinha[7] ; render:inst1|linha_galinha[6] ; clock ; clock ; None ; None ; 42.000 ns ;
; N/A ; 22.12 MHz ( period = 45.200 ns ) ; render:inst1|linha_galinha[2] ; render:inst1|linha_galinha[8] ; clock ; clock ; None ; None ; 41.700 ns ;
; N/A ; 22.17 MHz ( period = 45.100 ns ) ; render:inst1|coluna_carro1_2[12] ; inst5 ; clock ; clock ; None ; None ; 36.000 ns ;
; N/A ; 22.17 MHz ( period = 45.100 ns ) ; render:inst1|coluna_carro1[14] ; inst5 ; clock ; clock ; None ; None ; 36.000 ns ;
; N/A ; 22.17 MHz ( period = 45.100 ns ) ; render:inst1|coluna_carro3[6] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 41.800 ns ;
; N/A ; 22.22 MHz ( period = 45.000 ns ) ; render:inst1|linha_galinha[8] ; render:inst1|linha_galinha[8] ; clock ; clock ; None ; None ; 41.400 ns ;
; N/A ; 22.27 MHz ( period = 44.900 ns ) ; render:inst1|coluna_carro1[15] ; inst5 ; clock ; clock ; None ; None ; 35.800 ns ;
; N/A ; 22.27 MHz ( period = 44.900 ns ) ; render:inst1|coluna_carro1[6] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 41.600 ns ;
; N/A ; 22.27 MHz ( period = 44.900 ns ) ; render:inst1|coluna_carro1[10] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 41.600 ns ;
; N/A ; 22.27 MHz ( period = 44.900 ns ) ; render:inst1|coluna_carro1[4] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 41.300 ns ;
; N/A ; 22.27 MHz ( period = 44.900 ns ) ; render:inst1|coluna_carro1[4] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 41.300 ns ;
; N/A ; 22.27 MHz ( period = 44.900 ns ) ; render:inst1|linha_galinha[3] ; render:inst1|linha_galinha[8] ; clock ; clock ; None ; None ; 41.400 ns ;
; N/A ; 22.32 MHz ( period = 44.800 ns ) ; render:inst1|coluna_carro1_2[13] ; inst5 ; clock ; clock ; None ; None ; 35.700 ns ;
; N/A ; 22.32 MHz ( period = 44.800 ns ) ; render:inst1|coluna_carro1[16] ; inst5 ; clock ; clock ; None ; None ; 35.700 ns ;
; N/A ; 22.32 MHz ( period = 44.800 ns ) ; render:inst1|coluna_carro1[9] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 41.500 ns ;
; N/A ; 22.32 MHz ( period = 44.800 ns ) ; render:inst1|coluna_carro3[7] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 41.500 ns ;
; N/A ; 22.32 MHz ( period = 44.800 ns ) ; render:inst1|linha_galinha[2] ; render:inst1|linha_galinha[3] ; clock ; clock ; None ; None ; 41.200 ns ;
; N/A ; 22.32 MHz ( period = 44.800 ns ) ; render:inst1|linha_galinha[2] ; render:inst1|linha_galinha[2] ; clock ; clock ; None ; None ; 41.200 ns ;
; N/A ; 22.37 MHz ( period = 44.700 ns ) ; render:inst1|linha_galinha[2] ; render:inst1|linha_galinha[6] ; clock ; clock ; None ; None ; 41.200 ns ;
; N/A ; 22.42 MHz ( period = 44.600 ns ) ; render:inst1|coluna_carro2[5] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 41.300 ns ;
; N/A ; 22.42 MHz ( period = 44.600 ns ) ; render:inst1|coluna_carro1_2[6] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 41.300 ns ;
; N/A ; 22.42 MHz ( period = 44.600 ns ) ; render:inst1|coluna_carro1[7] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 41.300 ns ;
; N/A ; 22.42 MHz ( period = 44.600 ns ) ; render:inst1|coluna_carro1[11] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 41.300 ns ;
; N/A ; 22.42 MHz ( period = 44.600 ns ) ; render:inst1|coluna_carro1[5] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 41.000 ns ;
; N/A ; 22.42 MHz ( period = 44.600 ns ) ; render:inst1|linha_galinha[8] ; render:inst1|linha_galinha[3] ; clock ; clock ; None ; None ; 40.900 ns ;
; N/A ; 22.42 MHz ( period = 44.600 ns ) ; render:inst1|coluna_carro1[5] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 41.000 ns ;
; N/A ; 22.42 MHz ( period = 44.600 ns ) ; render:inst1|linha_galinha[8] ; render:inst1|linha_galinha[2] ; clock ; clock ; None ; None ; 40.900 ns ;
; N/A ; 22.47 MHz ( period = 44.500 ns ) ; render:inst1|coluna_carro1_2[14] ; inst5 ; clock ; clock ; None ; None ; 35.400 ns ;
; N/A ; 22.47 MHz ( period = 44.500 ns ) ; render:inst1|coluna_carro1_2[8] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 41.200 ns ;
; N/A ; 22.47 MHz ( period = 44.500 ns ) ; render:inst1|linha_galinha[3] ; render:inst1|linha_galinha[3] ; clock ; clock ; None ; None ; 40.900 ns ;
; N/A ; 22.47 MHz ( period = 44.500 ns ) ; render:inst1|linha_galinha[8] ; render:inst1|linha_galinha[6] ; clock ; clock ; None ; None ; 40.900 ns ;
; N/A ; 22.47 MHz ( period = 44.500 ns ) ; render:inst1|coluna_carro1[4] ; render:inst1|linha_galinha[8] ; clock ; clock ; None ; None ; 41.200 ns ;
; N/A ; 22.47 MHz ( period = 44.500 ns ) ; render:inst1|linha_galinha[3] ; render:inst1|linha_galinha[2] ; clock ; clock ; None ; None ; 40.900 ns ;
; N/A ; 22.52 MHz ( period = 44.400 ns ) ; render:inst1|coluna_carro3[8] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 41.100 ns ;
; N/A ; 22.52 MHz ( period = 44.400 ns ) ; render:inst1|linha_galinha[3] ; render:inst1|linha_galinha[6] ; clock ; clock ; None ; None ; 40.900 ns ;
; N/A ; 22.57 MHz ( period = 44.300 ns ) ; render:inst1|coluna_carro2[6] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 41.000 ns ;
; N/A ; 22.57 MHz ( period = 44.300 ns ) ; render:inst1|coluna_carro1_2[7] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 41.000 ns ;
; N/A ; 22.57 MHz ( period = 44.300 ns ) ; render:inst1|coluna_carro1[12] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 41.000 ns ;
; N/A ; 22.57 MHz ( period = 44.300 ns ) ; render:inst1|coluna_carro3[3] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 41.000 ns ;
; N/A ; 22.62 MHz ( period = 44.200 ns ) ; render:inst1|coluna_carro1_2[16] ; inst5 ; clock ; clock ; None ; None ; 35.100 ns ;
; N/A ; 22.62 MHz ( period = 44.200 ns ) ; render:inst1|coluna_carro1[5] ; render:inst1|linha_galinha[8] ; clock ; clock ; None ; None ; 40.900 ns ;
; N/A ; 22.68 MHz ( period = 44.100 ns ) ; render:inst1|coluna_carro1[13] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 40.800 ns ;
; N/A ; 22.68 MHz ( period = 44.100 ns ) ; render:inst1|coluna_carro1[4] ; render:inst1|linha_galinha[3] ; clock ; clock ; None ; None ; 40.700 ns ;
; N/A ; 22.68 MHz ( period = 44.100 ns ) ; render:inst1|coluna_carro1[4] ; render:inst1|linha_galinha[2] ; clock ; clock ; None ; None ; 40.700 ns ;
; N/A ; 22.73 MHz ( period = 44.000 ns ) ; render:inst1|coluna_carro1_2[15] ; inst5 ; clock ; clock ; None ; None ; 34.900 ns ;
; N/A ; 22.73 MHz ( period = 44.000 ns ) ; render:inst1|coluna_carro2[7] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 40.700 ns ;
; N/A ; 22.73 MHz ( period = 44.000 ns ) ; render:inst1|coluna_carro3[4] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 40.700 ns ;
; N/A ; 22.73 MHz ( period = 44.000 ns ) ; render:inst1|coluna_carro1[4] ; render:inst1|linha_galinha[6] ; clock ; clock ; None ; None ; 40.700 ns ;
; N/A ; 22.78 MHz ( period = 43.900 ns ) ; render:inst1|coluna_carro1_2[3] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 40.600 ns ;
; N/A ; 22.83 MHz ( period = 43.800 ns ) ; render:inst1|coluna_carro1[5] ; render:inst1|linha_galinha[3] ; clock ; clock ; None ; None ; 40.400 ns ;
; N/A ; 22.83 MHz ( period = 43.800 ns ) ; render:inst1|coluna_carro1[5] ; render:inst1|linha_galinha[2] ; clock ; clock ; None ; None ; 40.400 ns ;
; N/A ; 22.88 MHz ( period = 43.700 ns ) ; render:inst1|coluna_carro2[8] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 40.400 ns ;
; N/A ; 22.88 MHz ( period = 43.700 ns ) ; render:inst1|coluna_carro1[14] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 40.400 ns ;
; N/A ; 22.88 MHz ( period = 43.700 ns ) ; render:inst1|coluna_carro3[5] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 40.400 ns ;
; N/A ; 22.88 MHz ( period = 43.700 ns ) ; render:inst1|coluna_carro1[8] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 40.100 ns ;
; N/A ; 22.88 MHz ( period = 43.700 ns ) ; render:inst1|coluna_carro1[8] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 40.100 ns ;
; N/A ; 22.88 MHz ( period = 43.700 ns ) ; render:inst1|coluna_carro1[5] ; render:inst1|linha_galinha[6] ; clock ; clock ; None ; None ; 40.400 ns ;
; N/A ; 22.94 MHz ( period = 43.600 ns ) ; render:inst1|coluna_carro1[17] ; inst5 ; clock ; clock ; None ; None ; 34.500 ns ;
; N/A ; 22.94 MHz ( period = 43.600 ns ) ; render:inst1|coluna_carro2[3] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 40.300 ns ;
; N/A ; 22.94 MHz ( period = 43.600 ns ) ; render:inst1|coluna_carro1_2[9] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 40.300 ns ;
; N/A ; 22.94 MHz ( period = 43.600 ns ) ; render:inst1|coluna_carro1_2[4] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 40.300 ns ;
; N/A ; 22.94 MHz ( period = 43.600 ns ) ; render:inst1|coluna_carro1[3] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 40.000 ns ;
; N/A ; 22.94 MHz ( period = 43.600 ns ) ; render:inst1|coluna_carro1[3] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 40.000 ns ;
; N/A ; 22.99 MHz ( period = 43.500 ns ) ; render:inst1|coluna_carro1[15] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 40.200 ns ;
; N/A ; 23.04 MHz ( period = 43.400 ns ) ; render:inst1|coluna_carro1[16] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 40.100 ns ;
; N/A ; 23.04 MHz ( period = 43.400 ns ) ; render:inst1|coluna_carro3[9] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 40.100 ns ;
; N/A ; 23.09 MHz ( period = 43.300 ns ) ; render:inst1|coluna_carro1[19] ; inst5 ; clock ; clock ; None ; None ; 34.200 ns ;
; N/A ; 23.09 MHz ( period = 43.300 ns ) ; render:inst1|coluna_carro1[18] ; inst5 ; clock ; clock ; None ; None ; 34.200 ns ;
; N/A ; 23.09 MHz ( period = 43.300 ns ) ; render:inst1|coluna_carro2[4] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 40.000 ns ;
; N/A ; 23.09 MHz ( period = 43.300 ns ) ; render:inst1|coluna_carro1_2[5] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 40.000 ns ;
; N/A ; 23.09 MHz ( period = 43.300 ns ) ; render:inst1|coluna_carro3[10] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 40.000 ns ;
; N/A ; 23.09 MHz ( period = 43.300 ns ) ; render:inst1|coluna_carro1[8] ; render:inst1|linha_galinha[8] ; clock ; clock ; None ; None ; 40.000 ns ;
; N/A ; 23.15 MHz ( period = 43.200 ns ) ; render:inst1|coluna_carro1_2[10] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 39.900 ns ;
; N/A ; 23.15 MHz ( period = 43.200 ns ) ; render:inst1|coluna_carro1[3] ; render:inst1|linha_galinha[8] ; clock ; clock ; None ; None ; 39.900 ns ;
; N/A ; 23.20 MHz ( period = 43.100 ns ) ; render:inst1|coluna_carro1_2[19] ; inst5 ; clock ; clock ; None ; None ; 34.000 ns ;
; N/A ; 23.20 MHz ( period = 43.100 ns ) ; render:inst1|coluna_carro3[11] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 39.800 ns ;
; N/A ; 23.26 MHz ( period = 43.000 ns ) ; render:inst1|coluna_carro2[9] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 39.700 ns ;
; N/A ; 23.31 MHz ( period = 42.900 ns ) ; render:inst1|coluna_carro1_2[17] ; inst5 ; clock ; clock ; None ; None ; 33.800 ns ;
; N/A ; 23.31 MHz ( period = 42.900 ns ) ; render:inst1|coluna_carro2[11] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 39.600 ns ;
; N/A ; 23.31 MHz ( period = 42.900 ns ) ; render:inst1|coluna_carro1_2[11] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 39.600 ns ;
; N/A ; 23.31 MHz ( period = 42.900 ns ) ; render:inst1|coluna_carro3[6] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 39.300 ns ;
; N/A ; 23.31 MHz ( period = 42.900 ns ) ; render:inst1|coluna_carro1[8] ; render:inst1|linha_galinha[3] ; clock ; clock ; None ; None ; 39.500 ns ;
; N/A ; 23.31 MHz ( period = 42.900 ns ) ; render:inst1|coluna_carro3[6] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 39.300 ns ;
; N/A ; 23.31 MHz ( period = 42.900 ns ) ; render:inst1|coluna_carro1[8] ; render:inst1|linha_galinha[2] ; clock ; clock ; None ; None ; 39.500 ns ;
; N/A ; 23.36 MHz ( period = 42.800 ns ) ; render:inst1|coluna_carro1[20] ; inst5 ; clock ; clock ; None ; None ; 33.700 ns ;
; N/A ; 23.36 MHz ( period = 42.800 ns ) ; render:inst1|coluna_carro1_2[18] ; inst5 ; clock ; clock ; None ; None ; 33.700 ns ;
; N/A ; 23.36 MHz ( period = 42.800 ns ) ; render:inst1|coluna_carro2[10] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 39.500 ns ;
; N/A ; 23.36 MHz ( period = 42.800 ns ) ; render:inst1|coluna_carro3[12] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 39.500 ns ;
; N/A ; 23.36 MHz ( period = 42.800 ns ) ; render:inst1|coluna_carro1[3] ; render:inst1|linha_galinha[3] ; clock ; clock ; None ; None ; 39.400 ns ;
; N/A ; 23.36 MHz ( period = 42.800 ns ) ; render:inst1|coluna_carro1[8] ; render:inst1|linha_galinha[6] ; clock ; clock ; None ; None ; 39.500 ns ;
; N/A ; 23.36 MHz ( period = 42.800 ns ) ; render:inst1|coluna_carro1[3] ; render:inst1|linha_galinha[2] ; clock ; clock ; None ; None ; 39.400 ns ;
; N/A ; 23.42 MHz ( period = 42.700 ns ) ; render:inst1|coluna_carro3[6] ; inst5 ; clock ; clock ; None ; None ; 33.600 ns ;
; N/A ; 23.42 MHz ( period = 42.700 ns ) ; render:inst1|coluna_carro1[6] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 39.100 ns ;
; N/A ; 23.42 MHz ( period = 42.700 ns ) ; render:inst1|coluna_carro1[10] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 39.100 ns ;
; N/A ; 23.42 MHz ( period = 42.700 ns ) ; render:inst1|coluna_carro1[6] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 39.100 ns ;
; N/A ; 23.42 MHz ( period = 42.700 ns ) ; render:inst1|coluna_carro1[10] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 39.100 ns ;
; N/A ; 23.42 MHz ( period = 42.700 ns ) ; render:inst1|coluna_carro1[3] ; render:inst1|linha_galinha[6] ; clock ; clock ; None ; None ; 39.400 ns ;
; N/A ; 23.47 MHz ( period = 42.600 ns ) ; render:inst1|coluna_carro1_2[12] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 39.300 ns ;
; N/A ; 23.47 MHz ( period = 42.600 ns ) ; render:inst1|coluna_carro1[9] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 39.000 ns ;
; N/A ; 23.47 MHz ( period = 42.600 ns ) ; render:inst1|coluna_carro3[7] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 39.000 ns ;
; N/A ; 23.47 MHz ( period = 42.600 ns ) ; render:inst1|coluna_carro1[9] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 39.000 ns ;
; N/A ; 23.47 MHz ( period = 42.600 ns ) ; render:inst1|coluna_carro3[7] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 39.000 ns ;
; N/A ; 23.53 MHz ( period = 42.500 ns ) ; render:inst1|coluna_carro2[12] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 39.200 ns ;
; N/A ; 23.53 MHz ( period = 42.500 ns ) ; render:inst1|coluna_carro3[6] ; render:inst1|linha_galinha[8] ; clock ; clock ; None ; None ; 39.200 ns ;
; N/A ; 23.58 MHz ( period = 42.400 ns ) ; render:inst1|coluna_carro3[7] ; inst5 ; clock ; clock ; None ; None ; 33.300 ns ;
; N/A ; 23.58 MHz ( period = 42.400 ns ) ; render:inst1|coluna_carro2[5] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 38.800 ns ;
; N/A ; 23.58 MHz ( period = 42.400 ns ) ; render:inst1|coluna_carro1_2[6] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 38.800 ns ;
; N/A ; 23.58 MHz ( period = 42.400 ns ) ; render:inst1|coluna_carro1[7] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 38.800 ns ;
; N/A ; 23.58 MHz ( period = 42.400 ns ) ; render:inst1|coluna_carro1[11] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 38.800 ns ;
; N/A ; 23.58 MHz ( period = 42.400 ns ) ; render:inst1|coluna_carro2[5] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 38.800 ns ;
; N/A ; 23.58 MHz ( period = 42.400 ns ) ; render:inst1|coluna_carro1_2[6] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 38.800 ns ;
; N/A ; 23.58 MHz ( period = 42.400 ns ) ; render:inst1|coluna_carro1[7] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 38.800 ns ;
; N/A ; 23.58 MHz ( period = 42.400 ns ) ; render:inst1|coluna_carro1[11] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 38.800 ns ;
; N/A ; 23.64 MHz ( period = 42.300 ns ) ; render:inst1|coluna_carro2[5] ; inst5 ; clock ; clock ; None ; None ; 33.200 ns ;
; N/A ; 23.64 MHz ( period = 42.300 ns ) ; render:inst1|coluna_carro1_2[13] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 39.000 ns ;
; N/A ; 23.64 MHz ( period = 42.300 ns ) ; render:inst1|coluna_carro1_2[8] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 38.700 ns ;
; N/A ; 23.64 MHz ( period = 42.300 ns ) ; render:inst1|coluna_carro1_2[8] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 38.700 ns ;
; N/A ; 23.64 MHz ( period = 42.300 ns ) ; render:inst1|coluna_carro1[6] ; render:inst1|linha_galinha[8] ; clock ; clock ; None ; None ; 39.000 ns ;
; N/A ; 23.64 MHz ( period = 42.300 ns ) ; render:inst1|coluna_carro1[10] ; render:inst1|linha_galinha[8] ; clock ; clock ; None ; None ; 39.000 ns ;
; N/A ; 23.70 MHz ( period = 42.200 ns ) ; render:inst1|coluna_carro2[13] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 38.900 ns ;
; N/A ; 23.70 MHz ( period = 42.200 ns ) ; render:inst1|coluna_carro1[17] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 38.900 ns ;
; N/A ; 23.70 MHz ( period = 42.200 ns ) ; render:inst1|coluna_carro3[14] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 38.900 ns ;
; N/A ; 23.70 MHz ( period = 42.200 ns ) ; render:inst1|coluna_carro3[8] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 38.600 ns ;
; N/A ; 23.70 MHz ( period = 42.200 ns ) ; render:inst1|coluna_carro3[8] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 38.600 ns ;
; N/A ; 23.70 MHz ( period = 42.200 ns ) ; render:inst1|coluna_carro1[9] ; render:inst1|linha_galinha[8] ; clock ; clock ; None ; None ; 38.900 ns ;
; N/A ; 23.70 MHz ( period = 42.200 ns ) ; render:inst1|coluna_carro3[7] ; render:inst1|linha_galinha[8] ; clock ; clock ; None ; None ; 38.900 ns ;
; N/A ; 23.75 MHz ( period = 42.100 ns ) ; render:inst1|coluna_carro3[13] ; render:inst1|linha_galinha[5] ; clock ; clock ; None ; None ; 38.800 ns ;
; N/A ; 23.75 MHz ( period = 42.100 ns ) ; render:inst1|coluna_carro2[6] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 38.500 ns ;
; N/A ; 23.75 MHz ( period = 42.100 ns ) ; render:inst1|coluna_carro1_2[7] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 38.500 ns ;
; N/A ; 23.75 MHz ( period = 42.100 ns ) ; render:inst1|coluna_carro1[12] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 38.500 ns ;
; N/A ; 23.75 MHz ( period = 42.100 ns ) ; render:inst1|coluna_carro3[3] ; render:inst1|linha_galinha[4] ; clock ; clock ; None ; None ; 38.500 ns ;
; N/A ; 23.75 MHz ( period = 42.100 ns ) ; render:inst1|coluna_carro3[6] ; render:inst1|linha_galinha[3] ; clock ; clock ; None ; None ; 38.700 ns ;
; N/A ; 23.75 MHz ( period = 42.100 ns ) ; render:inst1|coluna_carro2[6] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 38.500 ns ;
; N/A ; 23.75 MHz ( period = 42.100 ns ) ; render:inst1|coluna_carro1_2[7] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 38.500 ns ;
; N/A ; 23.75 MHz ( period = 42.100 ns ) ; render:inst1|coluna_carro1[12] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 38.500 ns ;
; N/A ; 23.75 MHz ( period = 42.100 ns ) ; render:inst1|coluna_carro3[3] ; render:inst1|linha_galinha[7] ; clock ; clock ; None ; None ; 38.500 ns ;
; N/A ; 23.75 MHz ( period = 42.100 ns ) ; render:inst1|coluna_carro3[6] ; render:inst1|linha_galinha[2] ; clock ; clock ; None ; None ; 38.700 ns ;
; N/A ; 23.81 MHz ( period = 42.000 ns ) ; render:inst1|coluna_carro2[5] ; render:inst1|linha_galinha[8] ; clock ; clock ; None ; None ; 38.700 ns ;
; N/A ; 23.81 MHz ( period = 42.000 ns ) ; render:inst1|coluna_carro1_2[6] ; render:inst1|linha_galinha[8] ; clock ; clock ; None ; None ; 38.700 ns ;
; N/A ; 23.81 MHz ( period = 42.000 ns ) ; render:inst1|coluna_carro1[7] ; render:inst1|linha_galinha[8] ; clock ; clock ; None ; None ; 38.700 ns ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'clock' ;
+------------------------------------------+-----------------------------+------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+------------------------------------------+-----------------------------+------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Not operational: Clock Skew > Data Delay ; debounce:inst11|my_dff:d1|Q ; input_synchronizer:inst13|sync_reg ; clock ; clock ; None ; None ; 1.800 ns ;
+------------------------------------------+-----------------------------+------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
+------------------------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+-------+-----------------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+-------+-----------------------------+----------+
; N/A ; None ; 4.200 ns ; Baixo ; debounce:inst11|my_dff:d1|Q ; clock ;
; N/A ; None ; 3.100 ns ; Cima ; debounce:inst9|my_dff:d1|Q ; clock ;
+-------+--------------+------------+-------+-----------------------------+----------+
+-------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-----------------+------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-----------------+------+------------+
; N/A ; None ; 17.100 ns ; inst5 ; Rout ; clock ;
; N/A ; None ; 15.600 ns ; inst3 ; Rout ; clock ;
; N/A ; None ; 15.500 ns ; VGAdrive:inst|V ; V ; clock ;
; N/A ; None ; 15.200 ns ; VGAdrive:inst|H ; H ; clock ;
; N/A ; None ; 12.700 ns ; inst3 ; Gout ; clock ;
+-------+--------------+------------+-----------------+------+------------+
+------------------------------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+-------+-----------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+-------+-----------------------------+----------+
; N/A ; None ; 1.000 ns ; Cima ; debounce:inst9|my_dff:d1|Q ; clock ;
; N/A ; None ; -0.100 ns ; Baixo ; debounce:inst11|my_dff:d1|Q ; clock ;
+---------------+-------------+-----------+-------+-----------------------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Mon Jul 08 16:37:55 2019
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off freeway -c freeway
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clock" is an undefined clock
Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected ripple clock "debounce:inst9|clock_div:u1|slow_clk" as buffer
Info: Detected ripple clock "debounce:inst11|clock_div:u1|slow_clk" as buffer
Info: Detected ripple clock "divfreq:inst4|temporal" as buffer
Info: Detected ripple clock "divfreq:inst4|temporal2" as buffer
Info: Clock "clock" has Internal fmax of 20.24 MHz between source register "render:inst1|linha_galinha[4]" and destination register "render:inst1|linha_galinha[5]" (period= 49.4 ns)
Info: + Longest register to register delay is 46.100 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_D19; Fanout = 17; REG Node = 'render:inst1|linha_galinha[4]'
Info: 2: + IC(3.000 ns) + CELL(1.200 ns) = 4.200 ns; Loc. = LC5_D16; Fanout = 2; COMB Node = 'render:inst1|lpm_add_sub:Add15|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~COUT'
Info: 3: + IC(0.000 ns) + CELL(0.300 ns) = 4.500 ns; Loc. = LC6_D16; Fanout = 2; COMB Node = 'render:inst1|lpm_add_sub:Add15|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~COUT'
Info: 4: + IC(0.000 ns) + CELL(0.300 ns) = 4.800 ns; Loc. = LC7_D16; Fanout = 2; COMB Node = 'render:inst1|lpm_add_sub:Add15|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~COUT'
Info: 5: + IC(0.000 ns) + CELL(0.300 ns) = 5.100 ns; Loc. = LC8_D16; Fanout = 2; COMB Node = 'render:inst1|lpm_add_sub:Add15|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~COUT'
Info: 6: + IC(0.800 ns) + CELL(0.300 ns) = 6.200 ns; Loc. = LC1_D18; Fanout = 2; COMB Node = 'render:inst1|lpm_add_sub:Add15|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~COUT'
Info: 7: + IC(0.000 ns) + CELL(0.300 ns) = 6.500 ns; Loc. = LC2_D18; Fanout = 2; COMB Node = 'render:inst1|lpm_add_sub:Add15|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~COUT'
Info: 8: + IC(0.000 ns) + CELL(0.300 ns) = 6.800 ns; Loc. = LC3_D18; Fanout = 2; COMB Node = 'render:inst1|lpm_add_sub:Add15|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~COUT'
Info: 9: + IC(0.000 ns) + CELL(0.300 ns) = 7.100 ns; Loc. = LC4_D18; Fanout = 2; COMB Node = 'render:inst1|lpm_add_sub:Add15|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]~COUT'
Info: 10: + IC(0.000 ns) + CELL(0.300 ns) = 7.400 ns; Loc. = LC5_D18; Fanout = 2; COMB Node = 'render:inst1|lpm_add_sub:Add15|addcore:adder|a_csnbuffer:result_node|cs_buffer[10]~COUT'
Info: 11: + IC(0.000 ns) + CELL(0.300 ns) = 7.700 ns; Loc. = LC6_D18; Fanout = 2; COMB Node = 'render:inst1|lpm_add_sub:Add15|addcore:adder|a_csnbuffer:result_node|cs_buffer[11]~COUT'
Info: 12: + IC(0.000 ns) + CELL(0.300 ns) = 8.000 ns; Loc. = LC7_D18; Fanout = 2; COMB Node = 'render:inst1|lpm_add_sub:Add15|addcore:adder|a_csnbuffer:result_node|cs_buffer[12]~COUT'
Info: 13: + IC(0.000 ns) + CELL(0.300 ns) = 8.300 ns; Loc. = LC8_D18; Fanout = 2; COMB Node = 'render:inst1|lpm_add_sub:Add15|addcore:adder|a_csnbuffer:result_node|cs_buffer[13]~COUT'
Info: 14: + IC(0.800 ns) + CELL(0.300 ns) = 9.400 ns; Loc. = LC1_D20; Fanout = 2; COMB Node = 'render:inst1|lpm_add_sub:Add15|addcore:adder|a_csnbuffer:result_node|cs_buffer[14]~COUT'
Info: 15: + IC(0.000 ns) + CELL(0.300 ns) = 9.700 ns; Loc. = LC2_D20; Fanout = 2; COMB Node = 'render:inst1|lpm_add_sub:Add15|addcore:adder|a_csnbuffer:result_node|cs_buffer[15]~COUT'
Info: 16: + IC(0.000 ns) + CELL(0.300 ns) = 10.000 ns; Loc. = LC3_D20; Fanout = 2; COMB Node = 'render:inst1|lpm_add_sub:Add15|addcore:adder|a_csnbuffer:result_node|cs_buffer[16]~COUT'
Info: 17: + IC(0.000 ns) + CELL(0.300 ns) = 10.300 ns; Loc. = LC4_D20; Fanout = 2; COMB Node = 'render:inst1|lpm_add_sub:Add15|addcore:adder|a_csnbuffer:result_node|cs_buffer[17]~COUT'
Info: 18: + IC(0.000 ns) + CELL(0.300 ns) = 10.600 ns; Loc. = LC5_D20; Fanout = 2; COMB Node = 'render:inst1|lpm_add_sub:Add15|addcore:adder|a_csnbuffer:result_node|cs_buffer[18]~COUT'
Info: 19: + IC(0.000 ns) + CELL(0.300 ns) = 10.900 ns; Loc. = LC6_D20; Fanout = 2; COMB Node = 'render:inst1|lpm_add_sub:Add15|addcore:adder|a_csnbuffer:result_node|cs_buffer[19]~COUT'
Info: 20: + IC(0.000 ns) + CELL(0.300 ns) = 11.200 ns; Loc. = LC7_D20; Fanout = 2; COMB Node = 'render:inst1|lpm_add_sub:Add15|addcore:adder|a_csnbuffer:result_node|cs_buffer[20]~COUT'
Info: 21: + IC(0.000 ns) + CELL(0.300 ns) = 11.500 ns; Loc. = LC8_D20; Fanout = 2; COMB Node = 'render:inst1|lpm_add_sub:Add15|addcore:adder|a_csnbuffer:result_node|cs_buffer[21]~COUT'
Info: 22: + IC(0.800 ns) + CELL(0.300 ns) = 12.600 ns; Loc. = LC1_D22; Fanout = 2; COMB Node = 'render:inst1|lpm_add_sub:Add15|addcore:adder|a_csnbuffer:result_node|cs_buffer[22]~COUT'
Info: 23: + IC(0.000 ns) + CELL(0.300 ns) = 12.900 ns; Loc. = LC2_D22; Fanout = 2; COMB Node = 'render:inst1|lpm_add_sub:Add15|addcore:adder|a_csnbuffer:result_node|cs_buffer[23]~COUT'
Info: 24: + IC(0.000 ns) + CELL(0.300 ns) = 13.200 ns; Loc. = LC3_D22; Fanout = 2; COMB Node = 'render:inst1|lpm_add_sub:Add15|addcore:adder|a_csnbuffer:result_node|cs_buffer[24]~COUT'
Info: 25: + IC(0.000 ns) + CELL(0.300 ns) = 13.500 ns; Loc. = LC4_D22; Fanout = 2; COMB Node = 'render:inst1|lpm_add_sub:Add15|addcore:adder|a_csnbuffer:result_node|cs_buffer[25]~COUT'
Info: 26: + IC(0.000 ns) + CELL(1.300 ns) = 14.800 ns; Loc. = LC5_D22; Fanout = 1; COMB Node = 'render:inst1|lpm_add_sub:Add15|addcore:adder|a_csnbuffer:result_node|cs_buffer[26]'
Info: 27: + IC(0.600 ns) + CELL(2.300 ns) = 17.700 ns; Loc. = LC8_D22; Fanout = 1; COMB Node = 'render:inst1|linha_galinha~189'
Info: 28: + IC(2.200 ns) + CELL(1.800 ns) = 21.700 ns; Loc. = LC7_D21; Fanout = 1; COMB Node = 'render:inst1|linha_galinha~244'
Info: 29: + IC(0.600 ns) + CELL(2.300 ns) = 24.600 ns; Loc. = LC3_D21; Fanout = 1; COMB Node = 'render:inst1|linha_galinha~229'
Info: 30: + IC(0.600 ns) + CELL(1.800 ns) = 27.000 ns; Loc. = LC6_D21; Fanout = 1; COMB Node = 'render:inst1|linha_galinha~233'
Info: 31: + IC(2.200 ns) + CELL(1.800 ns) = 31.000 ns; Loc. = LC1_D23; Fanout = 1; COMB Node = 'render:inst1|linha_galinha~238'
Info: 32: + IC(2.300 ns) + CELL(1.800 ns) = 35.100 ns; Loc. = LC8_D13; Fanout = 1; COMB Node = 'render:inst1|linha_galinha~239'
Info: 33: + IC(0.600 ns) + CELL(1.200 ns) = 36.900 ns; Loc. = LC4_D13; Fanout = 1; COMB Node = 'render:inst1|linha_galinha~280'
Info: 34: + IC(0.000 ns) + CELL(0.900 ns) = 37.800 ns; Loc. = LC5_D13; Fanout = 1; COMB Node = 'render:inst1|linha_galinha~282'
Info: 35: + IC(0.000 ns) + CELL(1.500 ns) = 39.300 ns; Loc. = LC6_D13; Fanout = 7; COMB Node = 'render:inst1|linha_galinha~245'
Info: 36: + IC(0.600 ns) + CELL(2.300 ns) = 42.200 ns; Loc. = LC7_D13; Fanout = 1; COMB Node = 'render:inst1|linha_galinha~209'
Info: 37: + IC(2.200 ns) + CELL(1.700 ns) = 46.100 ns; Loc. = LC4_D14; Fanout = 17; REG Node = 'render:inst1|linha_galinha[5]'
Info: Total cell delay = 28.800 ns ( 62.47 % )
Info: Total interconnect delay = 17.300 ns ( 37.53 % )
Info: - Smallest clock skew is 0.300 ns
Info: + Shortest clock path from clock "clock" to destination register is 11.100 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_91; Fanout = 95; CLK Node = 'clock'
Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC2_A19; Fanout = 12; REG Node = 'divfreq:inst4|temporal2'
Info: 3: + IC(4.700 ns) + CELL(0.000 ns) = 11.100 ns; Loc. = LC4_D14; Fanout = 17; REG Node = 'render:inst1|linha_galinha[5]'
Info: Total cell delay = 3.900 ns ( 35.14 % )
Info: Total interconnect delay = 7.200 ns ( 64.86 % )
Info: - Longest clock path from clock "clock" to source register is 10.800 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_91; Fanout = 95; CLK Node = 'clock'
Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC2_A19; Fanout = 12; REG Node = 'divfreq:inst4|temporal2'
Info: 3: + IC(4.400 ns) + CELL(0.000 ns) = 10.800 ns; Loc. = LC3_D19; Fanout = 17; REG Node = 'render:inst1|linha_galinha[4]'
Info: Total cell delay = 3.900 ns ( 36.11 % )
Info: Total interconnect delay = 6.900 ns ( 63.89 % )
Info: + Micro clock to output delay of source is 1.100 ns
Info: + Micro setup delay of destination is 2.500 ns
Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "clock" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source pin or register "debounce:inst11|my_dff:d1|Q" and destination pin or register "input_synchronizer:inst13|sync_reg" for clock "clock" (Hold time is 200 ps)
Info: + Largest clock skew is 1.500 ns
Info: + Longest clock path from clock "clock" to destination register is 10.700 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_91; Fanout = 95; CLK Node = 'clock'
Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC2_A19; Fanout = 12; REG Node = 'divfreq:inst4|temporal2'
Info: 3: + IC(4.300 ns) + CELL(0.000 ns) = 10.700 ns; Loc. = LC1_D24; Fanout = 1; REG Node = 'input_synchronizer:inst13|sync_reg'
Info: Total cell delay = 3.900 ns ( 36.45 % )
Info: Total interconnect delay = 6.800 ns ( 63.55 % )
Info: - Shortest clock path from clock "clock" to source register is 9.200 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_91; Fanout = 95; CLK Node = 'clock'
Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC7_D5; Fanout = 2; REG Node = 'debounce:inst11|clock_div:u1|slow_clk'
Info: 3: + IC(2.800 ns) + CELL(0.000 ns) = 9.200 ns; Loc. = LC5_D24; Fanout = 2; REG Node = 'debounce:inst11|my_dff:d1|Q'
Info: Total cell delay = 3.900 ns ( 42.39 % )
Info: Total interconnect delay = 5.300 ns ( 57.61 % )
Info: - Micro clock to output delay of source is 1.100 ns
Info: - Shortest register to register delay is 1.800 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_D24; Fanout = 2; REG Node = 'debounce:inst11|my_dff:d1|Q'
Info: 2: + IC(0.600 ns) + CELL(1.200 ns) = 1.800 ns; Loc. = LC1_D24; Fanout = 1; REG Node = 'input_synchronizer:inst13|sync_reg'
Info: Total cell delay = 1.200 ns ( 66.67 % )
Info: Total interconnect delay = 0.600 ns ( 33.33 % )
Info: + Micro hold delay of destination is 1.600 ns
Info: tsu for register "debounce:inst11|my_dff:d1|Q" (data pin = "Baixo", clock pin = "clock") is 4.200 ns
Info: + Longest pin to register delay is 10.900 ns
Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_28; Fanout = 1; PIN Node = 'Baixo'
Info: 2: + IC(6.200 ns) + CELL(1.200 ns) = 10.900 ns; Loc. = LC5_D24; Fanout = 2; REG Node = 'debounce:inst11|my_dff:d1|Q'
Info: Total cell delay = 4.700 ns ( 43.12 % )
Info: Total interconnect delay = 6.200 ns ( 56.88 % )
Info: + Micro setup delay of destination is 2.500 ns
Info: - Shortest clock path from clock "clock" to destination register is 9.200 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_91; Fanout = 95; CLK Node = 'clock'
Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC7_D5; Fanout = 2; REG Node = 'debounce:inst11|clock_div:u1|slow_clk'
Info: 3: + IC(2.800 ns) + CELL(0.000 ns) = 9.200 ns; Loc. = LC5_D24; Fanout = 2; REG Node = 'debounce:inst11|my_dff:d1|Q'
Info: Total cell delay = 3.900 ns ( 42.39 % )
Info: Total interconnect delay = 5.300 ns ( 57.61 % )
Info: tco from clock "clock" to destination pin "Rout" through register "inst5" is 17.100 ns
Info: + Longest clock path from clock "clock" to source register is 5.300 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_91; Fanout = 95; CLK Node = 'clock'
Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_C16; Fanout = 1; REG Node = 'inst5'
Info: Total cell delay = 2.800 ns ( 52.83 % )
Info: Total interconnect delay = 2.500 ns ( 47.17 % )
Info: + Micro clock to output delay of source is 1.100 ns
Info: + Longest register to pin delay is 10.700 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_C16; Fanout = 1; REG Node = 'inst5'
Info: 2: + IC(2.600 ns) + CELL(1.800 ns) = 4.400 ns; Loc. = LC3_C24; Fanout = 1; COMB Node = 'inst12'
Info: 3: + IC(1.200 ns) + CELL(5.100 ns) = 10.700 ns; Loc. = PIN_236; Fanout = 0; PIN Node = 'Rout'
Info: Total cell delay = 6.900 ns ( 64.49 % )
Info: Total interconnect delay = 3.800 ns ( 35.51 % )
Info: th for register "debounce:inst9|my_dff:d1|Q" (data pin = "Cima", clock pin = "clock") is 1.000 ns
Info: + Longest clock path from clock "clock" to destination register is 10.300 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_91; Fanout = 95; CLK Node = 'clock'
Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC8_A23; Fanout = 2; REG Node = 'debounce:inst9|clock_div:u1|slow_clk'
Info: 3: + IC(3.900 ns) + CELL(0.000 ns) = 10.300 ns; Loc. = LC3_D23; Fanout = 2; REG Node = 'debounce:inst9|my_dff:d1|Q'
Info: Total cell delay = 3.900 ns ( 37.86 % )
Info: Total interconnect delay = 6.400 ns ( 62.14 % )
Info: + Micro hold delay of destination is 1.600 ns
Info: - Shortest pin to register delay is 10.900 ns
Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_29; Fanout = 1; PIN Node = 'Cima'
Info: 2: + IC(6.200 ns) + CELL(1.200 ns) = 10.900 ns; Loc. = LC3_D23; Fanout = 2; REG Node = 'debounce:inst9|my_dff:d1|Q'
Info: Total cell delay = 4.700 ns ( 43.12 % )
Info: Total interconnect delay = 6.200 ns ( 56.88 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 184 megabytes
Info: Processing ended: Mon Jul 08 16:37:58 2019
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:02