From c2dcb60ecfcfb09fc35dcea7e1fcf4316371825a Mon Sep 17 00:00:00 2001 From: a2k-hanlon Date: Thu, 24 Feb 2022 23:05:09 -0800 Subject: [PATCH 01/13] Port Speed Controller firmware to PlatformIO --- .gitignore | 3 +- Peripherals/RTC/RTC.h | 9 +- Peripherals/virtual_com/test/hardware_mock.h | 2 +- Peripherals/virtual_com/virtual_com.h | 13 +- Speed_Controller/.gitignore | 5 + Speed_Controller/.vscode/extensions.json | 10 + .../Target_1_STM32F103RB_1.0.0.dbgconf | 97 - .../main_STM32F103RB_1.0.0.dbgconf | 97 - .../RTE/Device/STM32F103RB/RTE_Device.h | 1811 ----------------- .../Device/STM32F103RB/startup_stm32f10x_md.s | 307 --- .../RTE/Device/STM32F103RB/system_stm32f10x.c | 1094 ---------- .../RTE/_Target_1/RTE_Components.h | 20 - Speed_Controller/RTE/_main/RTE_Components.h | 20 - Speed_Controller/Speed_Controller.uvprojx | 514 ----- Speed_Controller/platformio.ini | 25 + Speed_Controller/src/ADC/ADC.h | 10 +- Speed_Controller/src/Encoder/encoder.h | 8 +- Speed_Controller/src/Timer/Timer.h | 9 +- Speed_Controller/src/clock_init/clock_init.c | 150 ++ Speed_Controller/src/clock_init/clock_init.h | 9 + Speed_Controller/src/main.c | 7 +- 21 files changed, 231 insertions(+), 3989 deletions(-) create mode 100644 Speed_Controller/.gitignore create mode 100644 Speed_Controller/.vscode/extensions.json delete mode 100644 Speed_Controller/DebugConfig/Target_1_STM32F103RB_1.0.0.dbgconf delete mode 100644 Speed_Controller/DebugConfig/main_STM32F103RB_1.0.0.dbgconf delete mode 100644 Speed_Controller/RTE/Device/STM32F103RB/RTE_Device.h delete mode 100644 Speed_Controller/RTE/Device/STM32F103RB/startup_stm32f10x_md.s delete mode 100644 Speed_Controller/RTE/Device/STM32F103RB/system_stm32f10x.c delete mode 100644 Speed_Controller/RTE/_Target_1/RTE_Components.h delete mode 100644 Speed_Controller/RTE/_main/RTE_Components.h delete mode 100644 Speed_Controller/Speed_Controller.uvprojx create mode 100644 Speed_Controller/platformio.ini create mode 100644 Speed_Controller/src/clock_init/clock_init.c create mode 100644 Speed_Controller/src/clock_init/clock_init.h diff --git a/.gitignore b/.gitignore index baeff58..c26212d 100644 --- a/.gitignore +++ b/.gitignore @@ -2,6 +2,7 @@ !*.c !*.h +!platformio.ini !*.uvprojx !*.ino -!*.gitignore \ No newline at end of file +!*.gitignore diff --git a/Peripherals/RTC/RTC.h b/Peripherals/RTC/RTC.h index 09001ed..e35a37c 100644 --- a/Peripherals/RTC/RTC.h +++ b/Peripherals/RTC/RTC.h @@ -1,8 +1,13 @@ -#include "stm32f10x.h" +#ifndef RTC_H +#define RTC_H + +#include "stm32f103xb.h" #define RTC_PRESCALAR 2184 /** Initializes the RTC Clock with the LSE Oscillator on the Nucleo-64 board, using a prescalar value defined as a constant RTC_PRESCALAR. **/ -void RTCinit(void); \ No newline at end of file +void RTCinit(void); + +#endif /* RTC_H */ diff --git a/Peripherals/virtual_com/test/hardware_mock.h b/Peripherals/virtual_com/test/hardware_mock.h index 230a21f..1edb628 100644 --- a/Peripherals/virtual_com/test/hardware_mock.h +++ b/Peripherals/virtual_com/test/hardware_mock.h @@ -1,7 +1,7 @@ /** * Header file for the mock class. */ -#include "stm32f10x.h" +#include "stm32f103xb.h" #include #include diff --git a/Peripherals/virtual_com/virtual_com.h b/Peripherals/virtual_com/virtual_com.h index cdcf210..e8f7436 100644 --- a/Peripherals/virtual_com/virtual_com.h +++ b/Peripherals/virtual_com/virtual_com.h @@ -14,14 +14,10 @@ * */ -#include "stm32f10x.h" +#ifndef VIRTUAL_COM_H +#define VIRTUAL_COM_H -#ifndef VIRTUAL_COM -#define VIRTUAL_COM -/** - * Initializes virtual com. - */ -void VirtualComInit(void); +#include "stm32f103xb.h" /** * Sends ASCII character through USART. @@ -49,4 +45,5 @@ void SendInt(uint32_t i); * Sends a new line through USART */ void SendLine(void); -#endif + +#endif /* VIRTUAL_COM_H */ diff --git a/Speed_Controller/.gitignore b/Speed_Controller/.gitignore new file mode 100644 index 0000000..89cc49c --- /dev/null +++ b/Speed_Controller/.gitignore @@ -0,0 +1,5 @@ +.pio +.vscode/.browse.c_cpp.db* +.vscode/c_cpp_properties.json +.vscode/launch.json +.vscode/ipch diff --git a/Speed_Controller/.vscode/extensions.json b/Speed_Controller/.vscode/extensions.json new file mode 100644 index 0000000..080e70d --- /dev/null +++ b/Speed_Controller/.vscode/extensions.json @@ -0,0 +1,10 @@ +{ + // See http://go.microsoft.com/fwlink/?LinkId=827846 + // for the documentation about the extensions.json format + "recommendations": [ + "platformio.platformio-ide" + ], + "unwantedRecommendations": [ + "ms-vscode.cpptools-extension-pack" + ] +} diff --git a/Speed_Controller/DebugConfig/Target_1_STM32F103RB_1.0.0.dbgconf b/Speed_Controller/DebugConfig/Target_1_STM32F103RB_1.0.0.dbgconf deleted file mode 100644 index 90dabd8..0000000 --- a/Speed_Controller/DebugConfig/Target_1_STM32F103RB_1.0.0.dbgconf +++ /dev/null @@ -1,97 +0,0 @@ -// <<< Use Configuration Wizard in Context Menu >>> -// Debug MCU Configuration -// DBG_SLEEP -// Debug Sleep Mode -// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled -// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK -// DBG_STOP -// Debug Stop Mode -// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks -// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active -// DBG_STANDBY -// Debug Standby Mode -// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. -// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active -// DBG_IWDG_STOP -// Debug independent watchdog stopped when core is halted -// 0: The watchdog counter clock continues even if the core is halted -// 1: The watchdog counter clock is stopped when the core is halted -// DBG_WWDG_STOP -// Debug window watchdog stopped when core is halted -// 0: The window watchdog counter clock continues even if the core is halted -// 1: The window watchdog counter clock is stopped when the core is halted -// DBG_TIM1_STOP -// Timer 1 counter stopped when core is halted -// 0: The clock of the involved Timer Counter is fed even if the core is halted -// 1: The clock of the involved Timer counter is stopped when the core is halted -// DBG_TIM2_STOP -// Timer 2 counter stopped when core is halted -// 0: The clock of the involved Timer Counter is fed even if the core is halted -// 1: The clock of the involved Timer counter is stopped when the core is halted -// DBG_TIM3_STOP -// Timer 3 counter stopped when core is halted -// 0: The clock of the involved Timer Counter is fed even if the core is halted -// 1: The clock of the involved Timer counter is stopped when the core is halted -// DBG_TIM4_STOP -// Timer 4 counter stopped when core is halted -// 0: The clock of the involved Timer Counter is fed even if the core is halted -// 1: The clock of the involved Timer counter is stopped when the core is halted -// DBG_CAN1_STOP -// Debug CAN1 stopped when Core is halted -// 0: Same behavior as in normal mode -// 1: CAN1 receive registers are frozen -// DBG_I2C1_SMBUS_TIMEOUT -// I2C1 SMBUS timeout mode stopped when Core is halted -// 0: Same behavior as in normal mode -// 1: The SMBUS timeout is frozen -// DBG_I2C2_SMBUS_TIMEOUT -// I2C2 SMBUS timeout mode stopped when Core is halted -// 0: Same behavior as in normal mode -// 1: The SMBUS timeout is frozen -// DBG_TIM8_STOP -// Timer 8 counter stopped when core is halted -// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. -// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). -// DBG_TIM5_STOP -// Timer 5 counter stopped when core is halted -// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. -// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). -// DBG_TIM6_STOP -// Timer 6 counter stopped when core is halted -// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. -// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). -// DBG_TIM7_STOP -// Timer 7 counter stopped when core is halted -// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. -// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). -// DBG_CAN2_STOP -// Debug CAN2 stopped when Core is halted -// 0: Same behavior as in normal mode -// 1: CAN2 receive registers are frozen -// DBG_TIM12_STOP -// Timer 12 counter stopped when core is halted -// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. -// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). -// DBG_TIM13_STOP -// Timer 13 counter stopped when core is halted -// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. -// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). -// DBG_TIM14_STOP -// Timer 14 counter stopped when core is halted -// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. -// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). -// DBG_TIM9_STOP -// Timer 9 counter stopped when core is halted -// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. -// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). -// DBG_TIM10_STOP -// Timer 10 counter stopped when core is halted -// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. -// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). -// DBG_TIM11_STOP -// Timer 11 counter stopped when core is halted -// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. -// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). -// -DbgMCU_CR = 0x00000007; -// <<< end of configuration section >>> \ No newline at end of file diff --git a/Speed_Controller/DebugConfig/main_STM32F103RB_1.0.0.dbgconf b/Speed_Controller/DebugConfig/main_STM32F103RB_1.0.0.dbgconf deleted file mode 100644 index 90dabd8..0000000 --- a/Speed_Controller/DebugConfig/main_STM32F103RB_1.0.0.dbgconf +++ /dev/null @@ -1,97 +0,0 @@ -// <<< Use Configuration Wizard in Context Menu >>> -// Debug MCU Configuration -// DBG_SLEEP -// Debug Sleep Mode -// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled -// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK -// DBG_STOP -// Debug Stop Mode -// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks -// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active -// DBG_STANDBY -// Debug Standby Mode -// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. -// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active -// DBG_IWDG_STOP -// Debug independent watchdog stopped when core is halted -// 0: The watchdog counter clock continues even if the core is halted -// 1: The watchdog counter clock is stopped when the core is halted -// DBG_WWDG_STOP -// Debug window watchdog stopped when core is halted -// 0: The window watchdog counter clock continues even if the core is halted -// 1: The window watchdog counter clock is stopped when the core is halted -// DBG_TIM1_STOP -// Timer 1 counter stopped when core is halted -// 0: The clock of the involved Timer Counter is fed even if the core is halted -// 1: The clock of the involved Timer counter is stopped when the core is halted -// DBG_TIM2_STOP -// Timer 2 counter stopped when core is halted -// 0: The clock of the involved Timer Counter is fed even if the core is halted -// 1: The clock of the involved Timer counter is stopped when the core is halted -// DBG_TIM3_STOP -// Timer 3 counter stopped when core is halted -// 0: The clock of the involved Timer Counter is fed even if the core is halted -// 1: The clock of the involved Timer counter is stopped when the core is halted -// DBG_TIM4_STOP -// Timer 4 counter stopped when core is halted -// 0: The clock of the involved Timer Counter is fed even if the core is halted -// 1: The clock of the involved Timer counter is stopped when the core is halted -// DBG_CAN1_STOP -// Debug CAN1 stopped when Core is halted -// 0: Same behavior as in normal mode -// 1: CAN1 receive registers are frozen -// DBG_I2C1_SMBUS_TIMEOUT -// I2C1 SMBUS timeout mode stopped when Core is halted -// 0: Same behavior as in normal mode -// 1: The SMBUS timeout is frozen -// DBG_I2C2_SMBUS_TIMEOUT -// I2C2 SMBUS timeout mode stopped when Core is halted -// 0: Same behavior as in normal mode -// 1: The SMBUS timeout is frozen -// DBG_TIM8_STOP -// Timer 8 counter stopped when core is halted -// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. -// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). -// DBG_TIM5_STOP -// Timer 5 counter stopped when core is halted -// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. -// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). -// DBG_TIM6_STOP -// Timer 6 counter stopped when core is halted -// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. -// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). -// DBG_TIM7_STOP -// Timer 7 counter stopped when core is halted -// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. -// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). -// DBG_CAN2_STOP -// Debug CAN2 stopped when Core is halted -// 0: Same behavior as in normal mode -// 1: CAN2 receive registers are frozen -// DBG_TIM12_STOP -// Timer 12 counter stopped when core is halted -// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. -// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). -// DBG_TIM13_STOP -// Timer 13 counter stopped when core is halted -// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. -// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). -// DBG_TIM14_STOP -// Timer 14 counter stopped when core is halted -// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. -// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). -// DBG_TIM9_STOP -// Timer 9 counter stopped when core is halted -// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. -// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). -// DBG_TIM10_STOP -// Timer 10 counter stopped when core is halted -// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. -// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). -// DBG_TIM11_STOP -// Timer 11 counter stopped when core is halted -// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. -// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). -// -DbgMCU_CR = 0x00000007; -// <<< end of configuration section >>> \ No newline at end of file diff --git a/Speed_Controller/RTE/Device/STM32F103RB/RTE_Device.h b/Speed_Controller/RTE/Device/STM32F103RB/RTE_Device.h deleted file mode 100644 index d53b023..0000000 --- a/Speed_Controller/RTE/Device/STM32F103RB/RTE_Device.h +++ /dev/null @@ -1,1811 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (C) 2016 ARM Limited. All rights reserved. - * - * $Date: 29. August 2016 - * $Revision: V1.1.2 - * - * Project: RTE Device Configuration for STMicroelectronics STM32F1xx - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - - -#define GPIO_PORT(num) \ - ((num == 0) ? GPIOA : \ - (num == 1) ? GPIOB : \ - (num == 2) ? GPIOC : \ - (num == 3) ? GPIOD : \ - (num == 4) ? GPIOE : \ - (num == 5) ? GPIOF : \ - (num == 6) ? GPIOG : \ - NULL) - - -// Clock Configuration -// High-speed Internal Clock <1-999999999> -#define RTE_HSI 8000000 -// High-speed External Clock <1-999999999> -#define RTE_HSE 25000000 -// System Clock <1-999999999> -#define RTE_SYSCLK 72000000 -// HCLK Clock <1-999999999> -#define RTE_HCLK 72000000 -// APB1 Clock <1-999999999> -#define RTE_PCLK1 36000000 -// APB2 Clock <1-999999999> -#define RTE_PCLK2 72000000 -// ADC Clock <1-999999999> -#define RTE_ADCCLK 36000000 -// USB Clock -#define RTE_USBCLK 48000000 -// - - -// USART1 (Universal synchronous asynchronous receiver transmitter) -// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART -#define RTE_USART1 0 - -// USART1_TX Pin <0=>Not Used <1=>PA9 -#define RTE_USART1_TX_PORT_ID_DEF 0 -#if (RTE_USART1_TX_PORT_ID_DEF == 0) -#define RTE_USART1_TX_DEF 0 -#elif (RTE_USART1_TX_PORT_ID_DEF == 1) -#define RTE_USART1_TX_DEF 1 -#define RTE_USART1_TX_PORT_DEF GPIOA -#define RTE_USART1_TX_BIT_DEF 9 -#else -#error "Invalid USART1_TX Pin Configuration!" -#endif - -// USART1_RX Pin <0=>Not Used <1=>PA10 -#define RTE_USART1_RX_PORT_ID_DEF 0 -#if (RTE_USART1_RX_PORT_ID_DEF == 0) -#define RTE_USART1_RX_DEF 0 -#elif (RTE_USART1_RX_PORT_ID_DEF == 1) -#define RTE_USART1_RX_DEF 1 -#define RTE_USART1_RX_PORT_DEF GPIOA -#define RTE_USART1_RX_BIT_DEF 10 -#else -#error "Invalid USART1_RX Pin Configuration!" -#endif - -// USART1_CK Pin <0=>Not Used <1=>PA8 -#define RTE_USART1_CK_PORT_ID_DEF 0 -#if (RTE_USART1_CK_PORT_ID_DEF == 0) -#define RTE_USART1_CK 0 -#elif (RTE_USART1_CK_PORT_ID_DEF == 1) -#define RTE_USART1_CK 1 -#define RTE_USART1_CK_PORT_DEF GPIOA -#define RTE_USART1_CK_BIT_DEF 8 -#else -#error "Invalid USART1_CK Pin Configuration!" -#endif - -// USART1_CTS Pin <0=>Not Used <1=>PA11 -#define RTE_USART1_CTS_PORT_ID_DEF 0 -#if (RTE_USART1_CTS_PORT_ID_DEF == 0) -#define RTE_USART1_CTS 0 -#elif (RTE_USART1_CTS_PORT_ID_DEF == 1) -#define RTE_USART1_CTS 1 -#define RTE_USART1_CTS_PORT_DEF GPIOA -#define RTE_USART1_CTS_BIT_DEF 11 -#else -#error "Invalid USART1_CTS Pin Configuration!" -#endif - -// USART1_RTS Pin <0=>Not Used <1=>PA12 -#define RTE_USART1_RTS_PORT_ID_DEF 0 -#if (RTE_USART1_RTS_PORT_ID_DEF == 0) -#define RTE_USART1_RTS 0 -#elif (RTE_USART1_RTS_PORT_ID_DEF == 1) -#define RTE_USART1_RTS 1 -#define RTE_USART1_RTS_PORT_DEF GPIOA -#define RTE_USART1_RTS_BIT_DEF 12 -#else -#error "Invalid USART1_RTS Pin Configuration!" -#endif - -// USART1 Pin Remap -// Enable USART1 Pin Remapping -#define RTE_USART1_REMAP_FULL 0 - -// USART1_TX Pin <0=>Not Used <1=>PB6 -#define RTE_USART1_TX_PORT_ID_FULL 0 -#if (RTE_USART1_TX_PORT_ID_FULL == 0) -#define RTE_USART1_TX_FULL 0 -#elif (RTE_USART1_TX_PORT_ID_FULL == 1) -#define RTE_USART1_TX_FULL 1 -#define RTE_USART1_TX_PORT_FULL GPIOB -#define RTE_USART1_TX_BIT_FULL 6 -#else -#error "Invalid USART1_TX Pin Configuration!" -#endif - -// USART1_RX Pin <0=>Not Used <1=>PB7 -#define RTE_USART1_RX_PORT_ID_FULL 0 -#if (RTE_USART1_RX_PORT_ID_FULL == 0) -#define RTE_USART1_RX_FULL 0 -#elif (RTE_USART1_RX_PORT_ID_FULL == 1) -#define RTE_USART1_RX_FULL 1 -#define RTE_USART1_RX_PORT_FULL GPIOB -#define RTE_USART1_RX_BIT_FULL 7 -#else -#error "Invalid USART1_RX Pin Configuration!" -#endif -// - -#if (RTE_USART1_REMAP_FULL) -#define RTE_USART1_AF_REMAP AFIO_USART1_REMAP -#define RTE_USART1_TX RTE_USART1_TX_FULL -#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL -#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL -#define RTE_USART1_RX RTE_USART1_RX_FULL -#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL -#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL -#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF -#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF -#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF -#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF -#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF -#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF -#else -#define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP -#define RTE_USART1_TX RTE_USART1_TX_DEF -#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF -#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF -#define RTE_USART1_RX RTE_USART1_RX_DEF -#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF -#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF -#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF -#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF -#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF -#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF -#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF -#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very high -// Set DMA Channel priority -// -#define RTE_USART1_RX_DMA 0 -#define RTE_USART1_RX_DMA_NUMBER 1 -#define RTE_USART1_RX_DMA_CHANNEL 5 -#define RTE_USART1_RX_DMA_PRIORITY 0 -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very high -// Set DMA Channel priority -// -#define RTE_USART1_TX_DMA 0 -#define RTE_USART1_TX_DMA_NUMBER 1 -#define RTE_USART1_TX_DMA_CHANNEL 4 -#define RTE_USART1_TX_DMA_PRIORITY 0 -// - - -// USART2 (Universal synchronous asynchronous receiver transmitter) -// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART -#define RTE_USART2 0 - -// USART2_TX Pin <0=>Not Used <1=>PA2 -#define RTE_USART2_TX_PORT_ID_DEF 0 -#if (RTE_USART2_TX_PORT_ID_DEF == 0) -#define RTE_USART2_TX_DEF 0 -#elif (RTE_USART2_TX_PORT_ID_DEF == 1) -#define RTE_USART2_TX_DEF 1 -#define RTE_USART2_TX_PORT_DEF GPIOA -#define RTE_USART2_TX_BIT_DEF 2 -#else -#error "Invalid USART2_TX Pin Configuration!" -#endif - -// USART2_RX Pin <0=>Not Used <1=>PA3 -#define RTE_USART2_RX_PORT_ID_DEF 0 -#if (RTE_USART2_RX_PORT_ID_DEF == 0) -#define RTE_USART2_RX_DEF 0 -#elif (RTE_USART2_RX_PORT_ID_DEF == 1) -#define RTE_USART2_RX_DEF 1 -#define RTE_USART2_RX_PORT_DEF GPIOA -#define RTE_USART2_RX_BIT_DEF 3 -#else -#error "Invalid USART2_RX Pin Configuration!" -#endif - -// USART2_CK Pin <0=>Not Used <1=>PA4 -#define RTE_USART2_CK_PORT_ID_DEF 0 -#if (RTE_USART2_CK_PORT_ID_DEF == 0) -#define RTE_USART2_CK_DEF 0 -#elif (RTE_USART2_CK_PORT_ID_DEF == 1) -#define RTE_USART2_CK_DEF 1 -#define RTE_USART2_CK_PORT_DEF GPIOA -#define RTE_USART2_CK_BIT_DEF 4 -#else -#error "Invalid USART2_CK Pin Configuration!" -#endif - -// USART2_CTS Pin <0=>Not Used <1=>PA0 -#define RTE_USART2_CTS_PORT_ID_DEF 0 -#if (RTE_USART2_CTS_PORT_ID_DEF == 0) -#define RTE_USART2_CTS_DEF 0 -#elif (RTE_USART2_CTS_PORT_ID_DEF == 1) -#define RTE_USART2_CTS_DEF 1 -#define RTE_USART2_CTS_PORT_DEF GPIOA -#define RTE_USART2_CTS_BIT_DEF 0 -#else -#error "Invalid USART2_CTS Pin Configuration!" -#endif - -// USART2_RTS Pin <0=>Not Used <1=>PA1 -#define RTE_USART2_RTS_PORT_ID_DEF 0 -#if (RTE_USART2_RTS_PORT_ID_DEF == 0) -#define RTE_USART2_RTS_DEF 0 -#elif (RTE_USART2_RTS_PORT_ID_DEF == 1) -#define RTE_USART2_RTS_DEF 1 -#define RTE_USART2_RTS_PORT_DEF GPIOA -#define RTE_USART2_RTS_BIT_DEF 1 -#else -#error "Invalid USART2_RTS Pin Configuration!" -#endif - -// USART2 Pin Remap -// Enable USART2 Pin Remapping -#define RTE_USART2_REMAP_FULL 0 - -// USART2_TX Pin <0=>Not Used <1=>PD5 -#define RTE_USART2_TX_PORT_ID_FULL 0 -#if (RTE_USART2_TX_PORT_ID_FULL == 0) -#define RTE_USART2_TX_FULL 0 -#elif (RTE_USART2_TX_PORT_ID_FULL == 1) -#define RTE_USART2_TX_FULL 1 -#define RTE_USART2_TX_PORT_FULL GPIOD -#define RTE_USART2_TX_BIT_FULL 5 -#else -#error "Invalid USART2_TX Pin Configuration!" -#endif - -// USART2_RX Pin <0=>Not Used <1=>PD6 -#define RTE_USART2_RX_PORT_ID_FULL 0 -#if (RTE_USART2_RX_PORT_ID_FULL == 0) -#define RTE_USART2_RX_FULL 0 -#elif (RTE_USART2_RX_PORT_ID_FULL == 1) -#define RTE_USART2_RX_FULL 1 -#define RTE_USART2_RX_PORT_FULL GPIOD -#define RTE_USART2_RX_BIT_FULL 6 -#else -#error "Invalid USART2_RX Pin Configuration!" -#endif - -// USART2_CK Pin <0=>Not Used <1=>PD7 -#define RTE_USART2_CK_PORT_ID_FULL 0 -#if (RTE_USART2_CK_PORT_ID_FULL == 0) -#define RTE_USART2_CK_FULL 0 -#elif (RTE_USART2_CK_PORT_ID_FULL == 1) -#define RTE_USART2_CK_FULL 1 -#define RTE_USART2_CK_PORT_FULL GPIOD -#define RTE_USART2_CK_BIT_FULL 7 -#else -#error "Invalid USART2_CK Pin Configuration!" -#endif - -// USART2_CTS Pin <0=>Not Used <1=>PD3 -#define RTE_USART2_CTS_PORT_ID_FULL 0 -#if (RTE_USART2_CTS_PORT_ID_FULL == 0) -#define RTE_USART2_CTS_FULL 0 -#elif (RTE_USART2_CTS_PORT_ID_FULL == 1) -#define RTE_USART2_CTS_FULL 1 -#define RTE_USART2_CTS_PORT_FULL GPIOD -#define RTE_USART2_CTS_BIT_FULL 3 -#else -#error "Invalid USART2_CTS Pin Configuration!" -#endif - -// USART2_RTS Pin <0=>Not Used <1=>PD4 -#define RTE_USART2_RTS_PORT_ID_FULL 0 -#if (RTE_USART2_RTS_PORT_ID_FULL == 0) -#define RTE_USART2_RTS_FULL 0 -#elif (RTE_USART2_RTS_PORT_ID_FULL == 1) -#define RTE_USART2_RTS_FULL 1 -#define RTE_USART2_RTS_PORT_FULL GPIOD -#define RTE_USART2_RTS_BIT_FULL 4 -#else -#error "Invalid USART2_RTS Pin Configuration!" -#endif -// - -#if (RTE_USART2_REMAP_FULL) -#define RTE_USART2_AF_REMAP AFIO_USART2_REMAP -#define RTE_USART2_TX RTE_USART2_TX_FULL -#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL -#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL -#define RTE_USART2_RX RTE_USART2_RX_FULL -#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL -#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL -#define RTE_USART2_CK RTE_USART2_CK_FULL -#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL -#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL -#define RTE_USART2_CTS RTE_USART2_CTS_FULL -#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL -#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL -#define RTE_USART2_RTS RTE_USART2_RTS_FULL -#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL -#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL -#else -#define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP -#define RTE_USART2_TX RTE_USART2_TX_DEF -#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF -#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF -#define RTE_USART2_RX RTE_USART2_RX_DEF -#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF -#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF -#define RTE_USART2_CK RTE_USART2_CK_DEF -#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF -#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF -#define RTE_USART2_CTS RTE_USART2_CTS_DEF -#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF -#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF -#define RTE_USART2_RTS RTE_USART2_RTS_DEF -#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF -#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <6=>6 -// Selects DMA Channel (only Channel 6 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very high -// Set DMA Channel priority -// -#define RTE_USART2_RX_DMA 0 -#define RTE_USART2_RX_DMA_NUMBER 1 -#define RTE_USART2_RX_DMA_CHANNEL 6 -#define RTE_USART2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <7=>7 -// Selects DMA Channel (only Channel 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very high -// Set DMA Channel priority -// -#define RTE_USART2_TX_DMA 0 -#define RTE_USART2_TX_DMA_NUMBER 1 -#define RTE_USART2_TX_DMA_CHANNEL 7 -#define RTE_USART2_TX_DMA_PRIORITY 0 - -// - - -// USART3 (Universal synchronous asynchronous receiver transmitter) -// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART -#define RTE_USART3 0 - -// USART3_TX Pin <0=>Not Used <1=>PB10 -#define RTE_USART3_TX_PORT_ID_DEF 0 -#if (RTE_USART3_TX_PORT_ID_DEF == 0) -#define RTE_USART3_TX_DEF 0 -#elif (RTE_USART3_TX_PORT_ID_DEF == 1) -#define RTE_USART3_TX_DEF 1 -#define RTE_USART3_TX_PORT_DEF GPIOB -#define RTE_USART3_TX_BIT_DEF 10 -#else -#error "Invalid USART3_TX Pin Configuration!" -#endif - -// USART3_RX Pin <0=>Not Used <1=>PB11 -#define RTE_USART3_RX_PORT_ID_DEF 0 -#if (RTE_USART3_RX_PORT_ID_DEF == 0) -#define RTE_USART3_RX_DEF 0 -#elif (RTE_USART3_RX_PORT_ID_DEF == 1) -#define RTE_USART3_RX_DEF 1 -#define RTE_USART3_RX_PORT_DEF GPIOB -#define RTE_USART3_RX_BIT_DEF 11 -#else -#error "Invalid USART3_RX Pin Configuration!" -#endif - -// USART3_CK Pin <0=>Not Used <1=>PB12 -#define RTE_USART3_CK_PORT_ID_DEF 0 -#if (RTE_USART3_CK_PORT_ID_DEF == 0) -#define RTE_USART3_CK_DEF 0 -#elif (RTE_USART3_CK_PORT_ID_DEF == 1) -#define RTE_USART3_CK_DEF 1 -#define RTE_USART3_CK_PORT_DEF GPIOB -#define RTE_USART3_CK_BIT_DEF 12 -#else -#error "Invalid USART3_CK Pin Configuration!" -#endif - -// USART3_CTS Pin <0=>Not Used <1=>PB13 -#define RTE_USART3_CTS_PORT_ID_DEF 0 -#if (RTE_USART3_CTS_PORT_ID_DEF == 0) -#define RTE_USART3_CTS_DEF 0 -#elif (RTE_USART3_CTS_PORT_ID_DEF == 1) -#define RTE_USART3_CTS_DEF 1 -#define RTE_USART3_CTS_PORT_DEF GPIOB -#define RTE_USART3_CTS_BIT_DEF 13 -#else -#error "Invalid USART3_CTS Pin Configuration!" -#endif - -// USART3_RTS Pin <0=>Not Used <1=>PB14 -#define RTE_USART3_RTS_PORT_ID_DEF 0 -#if (RTE_USART3_RTS_PORT_ID_DEF == 0) -#define RTE_USART3_RTS_DEF 0 -#elif (RTE_USART3_RTS_PORT_ID_DEF == 1) -#define RTE_USART3_RTS_DEF 1 -#define RTE_USART3_RTS_PORT_DEF GPIOB -#define RTE_USART3_RTS_BIT_DEF 14 -#else -#error "Invalid USART3_RTS Pin Configuration!" -#endif - -// USART3 Partial Pin Remap -// Enable USART3 Partial Pin Remapping -#define RTE_USART3_REMAP_PARTIAL 0 - -// USART3_TX Pin <0=>Not Used <1=>PC10 -#define RTE_USART3_TX_PORT_ID_PARTIAL 0 -#if (RTE_USART3_TX_PORT_ID_PARTIAL == 0) -#define RTE_USART3_TX_PARTIAL 0 -#elif (RTE_USART3_TX_PORT_ID_PARTIAL == 1) -#define RTE_USART3_TX_PARTIAL 1 -#define RTE_USART3_TX_PORT_PARTIAL GPIOC -#define RTE_USART3_TX_BIT_PARTIAL 10 -#else -#error "Invalid USART3_TX Pin Configuration!" -#endif - -// USART3_RX Pin <0=>Not Used <1=>PC11 -#define RTE_USART3_RX_PORT_ID_PARTIAL 0 -#if (RTE_USART3_RX_PORT_ID_PARTIAL == 0) -#define RTE_USART3_RX_PARTIAL 0 -#elif (RTE_USART3_RX_PORT_ID_PARTIAL == 1) -#define RTE_USART3_RX_PARTIAL 1 -#define RTE_USART3_RX_PORT_PARTIAL GPIOC -#define RTE_USART3_RX_BIT_PARTIAL 11 -#else -#error "Invalid USART3_RX Pin Configuration!" -#endif - -// USART3_CK Pin <0=>Not Used <1=>PC12 -#define RTE_USART3_CK_PORT_ID_PARTIAL 0 -#if (RTE_USART3_CK_PORT_ID_PARTIAL == 0) -#define RTE_USART3_CK_PARTIAL 0 -#elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1) -#define RTE_USART3_CK_PARTIAL 1 -#define RTE_USART3_CK_PORT_PARTIAL GPIOC -#define RTE_USART3_CK_BIT_PARTIAL 12 -#else -#error "Invalid USART3_CK Pin Configuration!" -#endif -// - -// USART3 Full Pin Remap -// Enable USART3 Full Pin Remapping -#define RTE_USART3_REMAP_FULL 0 - -// USART3_TX Pin <0=>Not Used <1=>PD8 -#define RTE_USART3_TX_PORT_ID_FULL 0 -#if (RTE_USART3_TX_PORT_ID_FULL == 0) -#define RTE_USART3_TX_FULL 0 -#elif (RTE_USART3_TX_PORT_ID_FULL == 1) -#define RTE_USART3_TX_FULL 1 -#define RTE_USART3_TX_PORT_FULL GPIOD -#define RTE_USART3_TX_BIT_FULL 8 -#else -#error "Invalid USART3_TX Pin Configuration!" -#endif - -// USART3_RX Pin <0=>Not Used <1=>PD9 -#define RTE_USART3_RX_PORT_ID_FULL 0 -#if (RTE_USART3_RX_PORT_ID_FULL == 0) -#define RTE_USART3_RX_FULL 0 -#elif (RTE_USART3_RX_PORT_ID_FULL == 1) -#define RTE_USART3_RX_FULL 1 -#define RTE_USART3_RX_PORT_FULL GPIOD -#define RTE_USART3_RX_BIT_FULL 9 -#else -#error "Invalid USART3_RX Pin Configuration!" -#endif - -// USART3_CK Pin <0=>Not Used <1=>PD10 -#define RTE_USART3_CK_PORT_ID_FULL 0 -#if (RTE_USART3_CK_PORT_ID_FULL == 0) -#define RTE_USART3_CK_FULL 0 -#elif (RTE_USART3_CK_PORT_ID_FULL == 1) -#define RTE_USART3_CK_FULL 1 -#define RTE_USART3_CK_PORT_FULL GPIOD -#define RTE_USART3_CK_BIT_FULL 10 -#else -#error "Invalid USART3_CK Pin Configuration!" -#endif - -// USART3_CTS Pin <0=>Not Used <1=>PD11 -#define RTE_USART3_CTS_PORT_ID_FULL 0 -#if (RTE_USART3_CTS_PORT_ID_FULL == 0) -#define RTE_USART3_CTS_FULL 0 -#elif (RTE_USART3_CTS_PORT_ID_FULL == 1) -#define RTE_USART3_CTS_FULL 1 -#define RTE_USART3_CTS_PORT_FULL GPIOD -#define RTE_USART3_CTS_BIT_FULL 11 -#else -#error "Invalid USART3_CTS Pin Configuration!" -#endif - -// USART3_RTS Pin <0=>Not Used <1=>PD12 -#define RTE_USART3_RTS_PORT_ID_FULL 0 -#if (RTE_USART3_RTS_PORT_ID_FULL == 0) -#define RTE_USART3_RTS_FULL 0 -#elif (RTE_USART3_RTS_PORT_ID_FULL == 1) -#define RTE_USART3_RTS_FULL 1 -#define RTE_USART3_RTS_PORT_FULL GPIOD -#define RTE_USART3_RTS_BIT_FULL 12 -#else -#error "Invalid USART3_RTS Pin Configuration!" -#endif -// - -#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1)) -#error "Invalid USART3 Pin Remap Configuration!" -#endif - -#if (RTE_USART3_REMAP_FULL) -#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL -#define RTE_USART3_TX RTE_USART3_TX_FULL -#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL -#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL -#define RTE_USART3_RX RTE_USART3_RX_FULL -#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL -#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL -#define RTE_USART3_CK RTE_USART3_CK_FULL -#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL -#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL -#define RTE_USART3_CTS RTE_USART3_CTS_FULL -#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL -#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL -#define RTE_USART3_RTS RTE_USART3_RTS_FULL -#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL -#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL -#elif (RTE_USART3_REMAP_PARTIAL) -#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL -#define RTE_USART3_TX RTE_USART3_TX_PARTIAL -#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL -#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL -#define RTE_USART3_RX RTE_USART3_RX_PARTIAL -#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL -#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL -#define RTE_USART3_CK RTE_USART3_CK_PARTIAL -#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL -#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL -#define RTE_USART3_CTS RTE_USART3_CTS_DEF -#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF -#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF -#define RTE_USART3_RTS RTE_USART3_RTS_DEF -#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF -#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF -#else -#define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP -#define RTE_USART3_TX RTE_USART3_TX_DEF -#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF -#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF -#define RTE_USART3_RX RTE_USART3_RX_DEF -#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF -#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF -#define RTE_USART3_CK RTE_USART3_CK_DEF -#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF -#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF -#define RTE_USART3_CTS RTE_USART3_CTS_DEF -#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF -#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF -#define RTE_USART3_RTS RTE_USART3_RTS_DEF -#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF -#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very high -// Sets DMA Channel priority -// -#define RTE_USART3_RX_DMA 0 -#define RTE_USART3_RX_DMA_NUMBER 1 -#define RTE_USART3_RX_DMA_CHANNEL 3 -#define RTE_USART3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <2=>2 -// Selects DMA Channel (only Channel 2 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very high -// Sets DMA Channel priority -// -#define RTE_USART3_TX_DMA 0 -#define RTE_USART3_TX_DMA_NUMBER 1 -#define RTE_USART3_TX_DMA_CHANNEL 2 -#define RTE_USART3_TX_DMA_PRIORITY 0 - -// - - -// UART4 (Universal asynchronous receiver transmitter) -// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART -#define RTE_UART4 0 -#define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP - -// UART4_TX Pin <0=>Not Used <1=>PC10 -#define RTE_UART4_TX_ID 0 -#if (RTE_UART4_TX_ID == 0) -#define RTE_UART4_TX 0 -#elif (RTE_UART4_TX_ID == 1) -#define RTE_UART4_TX 1 -#define RTE_UART4_TX_PORT GPIOC -#define RTE_UART4_TX_BIT 10 -#else -#error "Invalid UART4_TX Pin Configuration!" -#endif - -// UART4_RX Pin <0=>Not Used <1=>PC11 -#define RTE_UART4_RX_ID 0 -#if (RTE_UART4_RX_ID == 0) -#define RTE_UART4_RX 0 -#elif (RTE_UART4_RX_ID == 1) -#define RTE_UART4_RX 1 -#define RTE_UART4_RX_PORT GPIOC -#define RTE_UART4_RX_BIT 11 -#else -#error "Invalid UART4_RX Pin Configuration!" -#endif - - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very high -// Sets DMA Channel priority -// -#define RTE_UART4_RX_DMA 0 -#define RTE_UART4_RX_DMA_NUMBER 2 -#define RTE_UART4_RX_DMA_CHANNEL 3 -#define RTE_UART4_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very high -// Sets DMA Channel priority -// -#define RTE_UART4_TX_DMA 0 -#define RTE_UART4_TX_DMA_NUMBER 2 -#define RTE_UART4_TX_DMA_CHANNEL 5 -#define RTE_UART4_TX_DMA_PRIORITY 0 - -// - - -// UART5 (Universal asynchronous receiver transmitter) -// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART -#define RTE_UART5 0 -#define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP - -// UART5_TX Pin <0=>Not Used <1=>PC12 -#define RTE_UART5_TX_ID 0 -#if (RTE_UART5_TX_ID == 0) -#define RTE_UART5_TX 0 -#elif (RTE_UART5_TX_ID == 1) -#define RTE_UART5_TX 1 -#define RTE_UART5_TX_PORT GPIOC -#define RTE_UART5_TX_BIT 12 -#else -#error "Invalid UART5_TX Pin Configuration!" -#endif - -// UART5_RX Pin <0=>Not Used <1=>PD2 -#define RTE_UART5_RX_ID 0 -#if (RTE_UART5_RX_ID == 0) -#define RTE_UART5_RX 0 -#elif (RTE_UART5_RX_ID == 1) -#define RTE_UART5_RX 1 -#define RTE_UART5_RX_PORT GPIOD -#define RTE_UART5_RX_BIT 2 -#else -#error "Invalid UART5_RX Pin Configuration!" -#endif -// - - -// I2C1 (Inter-integrated Circuit Interface 1) -// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C -#define RTE_I2C1 0 - -// I2C1_SCL Pin <0=>PB6 -#define RTE_I2C1_SCL_PORT_ID_DEF 0 -#if (RTE_I2C1_SCL_PORT_ID_DEF == 0) -#define RTE_I2C1_SCL_PORT_DEF GPIOB -#define RTE_I2C1_SCL_BIT_DEF 6 -#else -#error "Invalid I2C1_SCL Pin Configuration!" -#endif - -// I2C1_SDA Pin <0=>PB7 -#define RTE_I2C1_SDA_PORT_ID_DEF 0 -#if (RTE_I2C1_SDA_PORT_ID_DEF == 0) -#define RTE_I2C1_SDA_PORT_DEF GPIOB -#define RTE_I2C1_SDA_BIT_DEF 7 -#else -#error "Invalid I2C1_SCL Pin Configuration!" -#endif - -// I2C1 Pin Remap -// Enable I2C1 Pin Remapping -#define RTE_I2C1_REMAP_FULL 0 - -// I2C1_SCL Pin <0=>PB8 -#define RTE_I2C1_SCL_PORT_ID_FULL 0 -#if (RTE_I2C1_SCL_PORT_ID_FULL == 0) -#define RTE_I2C1_SCL_PORT_FULL GPIOB -#define RTE_I2C1_SCL_BIT_FULL 8 -#else -#error "Invalid I2C1_SCL Pin Configuration!" -#endif - -// I2C1_SDA Pin <0=>PB9 -#define RTE_I2C1_SDA_PORT_ID_FULL 0 -#if (RTE_I2C1_SDA_PORT_ID_FULL == 0) -#define RTE_I2C1_SDA_PORT_FULL GPIOB -#define RTE_I2C1_SDA_BIT_FULL 9 -#else -#error "Invalid I2C1_SCL Pin Configuration!" -#endif - -// - -#if (RTE_I2C1_REMAP_FULL) -#define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP -#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL -#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL -#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL -#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL -#else -#define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP -#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF -#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF -#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF -#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF -#endif - - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <7=>7 -// Selects DMA Channel (only Channel 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C1_RX_DMA 0 -#define RTE_I2C1_RX_DMA_NUMBER 1 -#define RTE_I2C1_RX_DMA_CHANNEL 7 -#define RTE_I2C1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <6=>6 -// Selects DMA Channel (only Channel 6 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C1_TX_DMA 0 -#define RTE_I2C1_TX_DMA_NUMBER 1 -#define RTE_I2C1_TX_DMA_CHANNEL 6 -#define RTE_I2C1_TX_DMA_PRIORITY 0 - -// - - -// I2C2 (Inter-integrated Circuit Interface 2) -// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C -#define RTE_I2C2 0 -#define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP - -// I2C2_SCL Pin <0=>PB10 -#define RTE_I2C2_SCL_PORT_ID 0 -#if (RTE_I2C2_SCL_PORT_ID == 0) -#define RTE_I2C2_SCL_PORT GPIOB -#define RTE_I2C2_SCL_BIT 10 -#else -#error "Invalid I2C2_SCL Pin Configuration!" -#endif - -// I2C2_SDA Pin <0=>PB11 -#define RTE_I2C2_SDA_PORT_ID 0 -#if (RTE_I2C2_SDA_PORT_ID == 0) -#define RTE_I2C2_SDA_PORT GPIOB -#define RTE_I2C2_SDA_BIT 11 -#else -#error "Invalid I2C2_SCL Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C2_RX_DMA 1 -#define RTE_I2C2_RX_DMA_NUMBER 1 -#define RTE_I2C2_RX_DMA_CHANNEL 5 -#define RTE_I2C2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C2_TX_DMA 1 -#define RTE_I2C2_TX_DMA_NUMBER 1 -#define RTE_I2C2_TX_DMA_CHANNEL 4 -#define RTE_I2C2_TX_DMA_PRIORITY 0 - -// - - -// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] -// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI -#define RTE_SPI1 0 - -// SPI1_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..G, y = 0..15) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI1_NSS_PIN 1 -#define RTE_SPI1_NSS_PORT GPIO_PORT(0) -#define RTE_SPI1_NSS_BIT 4 - -// SPI1_SCK Pin <0=>PA5 -#define RTE_SPI1_SCK_PORT_ID_DEF 0 -#if (RTE_SPI1_SCK_PORT_ID_DEF == 0) -#define RTE_SPI1_SCK_PORT_DEF GPIOA -#define RTE_SPI1_SCK_BIT_DEF 5 -#else -#error "Invalid SPI1_SCK Pin Configuration!" -#endif - -// SPI1_MISO Pin <0=>Not Used <1=>PA6 -#define RTE_SPI1_MISO_PORT_ID_DEF 0 -#if (RTE_SPI1_MISO_PORT_ID_DEF == 0) -#define RTE_SPI1_MISO_DEF 0 -#elif (RTE_SPI1_MISO_PORT_ID_DEF == 1) -#define RTE_SPI1_MISO_DEF 1 -#define RTE_SPI1_MISO_PORT_DEF GPIOA -#define RTE_SPI1_MISO_BIT_DEF 6 -#else -#error "Invalid SPI1_MISO Pin Configuration!" -#endif - -// SPI1_MOSI Pin <0=>Not Used <1=>PA7 -#define RTE_SPI1_MOSI_PORT_ID_DEF 0 -#if (RTE_SPI1_MOSI_PORT_ID_DEF == 0) -#define RTE_SPI1_MOSI_DEF 0 -#elif (RTE_SPI1_MOSI_PORT_ID_DEF == 1) -#define RTE_SPI1_MOSI_DEF 1 -#define RTE_SPI1_MOSI_PORT_DEF GPIOA -#define RTE_SPI1_MOSI_BIT_DEF 7 -#else -#error "Invalid SPI1_MISO Pin Configuration!" -#endif - -// SPI1 Pin Remap -// Enable SPI1 Pin Remapping. -#define RTE_SPI1_REMAP 0 - -// SPI1_SCK Pin <0=>PB3 -#define RTE_SPI1_SCK_PORT_ID_FULL 0 -#if (RTE_SPI1_SCK_PORT_ID_FULL == 0) -#define RTE_SPI1_SCK_PORT_FULL GPIOB -#define RTE_SPI1_SCK_BIT_FULL 3 -#else -#error "Invalid SPI1_SCK Pin Configuration!" -#endif - -// SPI1_MISO Pin <0=>Not Used <1=>PB4 -#define RTE_SPI1_MISO_PORT_ID_FULL 0 -#if (RTE_SPI1_MISO_PORT_ID_FULL == 0) -#define RTE_SPI1_MISO_FULL 0 -#elif (RTE_SPI1_MISO_PORT_ID_FULL == 1) -#define RTE_SPI1_MISO_FULL 1 -#define RTE_SPI1_MISO_PORT_FULL GPIOB -#define RTE_SPI1_MISO_BIT_FULL 4 -#else -#error "Invalid SPI1_MISO Pin Configuration!" -#endif -// SPI1_MOSI Pin <0=>Not Used <1=>PB5 -#define RTE_SPI1_MOSI_PORT_ID_FULL 0 -#if (RTE_SPI1_MOSI_PORT_ID_FULL == 0) -#define RTE_SPI1_MOSI_FULL 0 -#elif (RTE_SPI1_MOSI_PORT_ID_FULL == 1) -#define RTE_SPI1_MOSI_FULL 1 -#define RTE_SPI1_MOSI_PORT_FULL GPIOB -#define RTE_SPI1_MOSI_BIT_FULL 5 -#else -#error "Invalid SPI1_MOSI Pin Configuration!" -#endif - -// - -#if (RTE_SPI1_REMAP) -#define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP -#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL -#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL -#define RTE_SPI1_MISO RTE_SPI1_MISO_FULL -#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL -#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL -#define RTE_SPI1_MOSI RTE_SPI1_MOSI_FULL -#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL -#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL -#else -#define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP -#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF -#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF -#define RTE_SPI1_MISO RTE_SPI1_MISO_DEF -#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF -#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF -#define RTE_SPI1_MOSI RTE_SPI1_MOSI_DEF -#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF -#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <2=>2 -// Selects DMA Channel (only Channel 2 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI1_RX_DMA 0 -#define RTE_SPI1_RX_DMA_NUMBER 1 -#define RTE_SPI1_RX_DMA_CHANNEL 2 -#define RTE_SPI1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI1_TX_DMA 0 -#define RTE_SPI1_TX_DMA_NUMBER 1 -#define RTE_SPI1_TX_DMA_CHANNEL 3 -#define RTE_SPI1_TX_DMA_PRIORITY 0 - -// - - -// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] -// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI -#define RTE_SPI2 0 - -// SPI2_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..G, y = 0..15) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI2_NSS_PIN 1 -#define RTE_SPI2_NSS_PORT GPIO_PORT(1) -#define RTE_SPI2_NSS_BIT 12 - -// SPI2_SCK Pin <0=>PB13 -#define RTE_SPI2_SCK_PORT_ID 0 -#if (RTE_SPI2_SCK_PORT_ID == 0) -#define RTE_SPI2_SCK_PORT GPIOB -#define RTE_SPI2_SCK_BIT 13 -#define RTE_SPI2_SCK_REMAP 0 -#else -#error "Invalid SPI2_SCK Pin Configuration!" -#endif - -// SPI2_MISO Pin <0=>Not Used <1=>PB14 -#define RTE_SPI2_MISO_PORT_ID 0 -#if (RTE_SPI2_MISO_PORT_ID == 0) -#define RTE_SPI2_MISO 0 -#elif (RTE_SPI2_MISO_PORT_ID == 1) -#define RTE_SPI2_MISO 1 -#define RTE_SPI2_MISO_PORT GPIOB -#define RTE_SPI2_MISO_BIT 14 -#define RTE_SPI2_MISO_REMAP 0 -#else -#error "Invalid SPI2_MISO Pin Configuration!" -#endif - -// SPI2_MOSI Pin <0=>Not Used <1=>PB15 -#define RTE_SPI2_MOSI_PORT_ID 0 -#if (RTE_SPI2_MOSI_PORT_ID == 0) -#define RTE_SPI2_MOSI 0 -#elif (RTE_SPI2_MOSI_PORT_ID == 1) -#define RTE_SPI2_MOSI 1 -#define RTE_SPI2_MOSI_PORT GPIOB -#define RTE_SPI2_MOSI_BIT 15 -#define RTE_SPI2_MOSI_REMAP 0 -#else -#error "Invalid SPI2_MISO Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI2_RX_DMA 0 -#define RTE_SPI2_RX_DMA_NUMBER 1 -#define RTE_SPI2_RX_DMA_CHANNEL 4 -#define RTE_SPI2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI2_TX_DMA 0 -#define RTE_SPI2_TX_DMA_NUMBER 1 -#define RTE_SPI2_TX_DMA_CHANNEL 5 -#define RTE_SPI2_TX_DMA_PRIORITY 0 - -// - - -// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] -// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI -#define RTE_SPI3 0 - -// SPI3_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..G, y = 0..15) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI3_NSS_PIN 1 -#define RTE_SPI3_NSS_PORT GPIO_PORT(0) -#define RTE_SPI3_NSS_BIT 15 - -// SPI3_SCK Pin <0=>PB3 -#define RTE_SPI3_SCK_PORT_ID_DEF 0 -#if (RTE_SPI3_SCK_PORT_ID_DEF == 0) -#define RTE_SPI3_SCK_PORT_DEF GPIOB -#define RTE_SPI3_SCK_BIT_DEF 3 -#else -#error "Invalid SPI3_SCK Pin Configuration!" -#endif - -// SPI3_MISO Pin <0=>Not Used <1=>PB4 -#define RTE_SPI3_MISO_PORT_ID_DEF 0 -#if (RTE_SPI3_MISO_PORT_ID_DEF == 0) -#define RTE_SPI3_MISO_DEF 0 -#elif (RTE_SPI3_MISO_PORT_ID_DEF == 1) -#define RTE_SPI3_MISO_DEF 1 -#define RTE_SPI3_MISO_PORT_DEF GPIOB -#define RTE_SPI3_MISO_BIT_DEF 4 -#else -#error "Invalid SPI3_MISO Pin Configuration!" -#endif - -// SPI3_MOSI <0=>Not Used Pin <1=>PB5 -#define RTE_SPI3_MOSI_PORT_ID_DEF 0 -#if (RTE_SPI3_MOSI_PORT_ID_DEF == 0) -#define RTE_SPI3_MOSI_DEF 0 -#elif (RTE_SPI3_MOSI_PORT_ID_DEF == 1) -#define RTE_SPI3_MOSI_DEF 1 -#define RTE_SPI3_MOSI_PORT_DEF GPIOB -#define RTE_SPI3_MOSI_BIT_DEF 5 -#else -#error "Invalid SPI3_MOSI Pin Configuration!" -#endif - -// SPI3 Pin Remap -// Enable SPI3 Pin Remapping. -// SPI 3 Pin Remapping is available only in connectivity line devices! -#define RTE_SPI3_REMAP 0 - -// SPI3_SCK Pin <0=>PC10 -#define RTE_SPI3_SCK_PORT_ID_FULL 0 -#if (RTE_SPI3_SCK_PORT_ID_FULL == 0) -#define RTE_SPI3_SCK_PORT_FULL GPIOC -#define RTE_SPI3_SCK_BIT_FULL 10 -#else -#error "Invalid SPI3_SCK Pin Configuration!" -#endif - -// SPI3_MISO Pin <0=>Not Used <1=>PC11 -#define RTE_SPI3_MISO_PORT_ID_FULL 0 -#if (RTE_SPI3_MISO_PORT_ID_FULL == 0) -#define RTE_SPI3_MISO_FULL 0 -#elif (RTE_SPI3_MISO_PORT_ID_FULL == 1) -#define RTE_SPI3_MISO_FULL 1 -#define RTE_SPI3_MISO_PORT_FULL GPIOC -#define RTE_SPI3_MISO_BIT_FULL 11 -#else -#error "Invalid SPI3_MISO Pin Configuration!" -#endif -// SPI3_MOSI Pin <0=>Not Used <1=>PC12 -#define RTE_SPI3_MOSI_PORT_ID_FULL 0 -#if (RTE_SPI3_MOSI_PORT_ID_FULL == 0) -#define RTE_SPI3_MOSI_FULL 0 -#elif (RTE_SPI3_MOSI_PORT_ID_FULL == 1) -#define RTE_SPI3_MOSI_FULL 1 -#define RTE_SPI3_MOSI_PORT_FULL GPIOC -#define RTE_SPI3_MOSI_BIT_FULL 12 -#else -#error "Invalid SPI3_MOSI Pin Configuration!" -#endif - -// - -#if (RTE_SPI3_REMAP) -#define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP -#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL -#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL -#define RTE_SPI3_MISO RTE_SPI3_MISO_FULL -#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL -#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL -#define RTE_SPI3_MOSI RTE_SPI3_MOSI_FULL -#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL -#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL -#else -#define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP -#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF -#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF -#define RTE_SPI3_MISO RTE_SPI3_MISO_DEF -#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF -#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF -#define RTE_SPI3_MOSI RTE_SPI3_MOSI_DEF -#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF -#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI3_RX_DMA 0 -#define RTE_SPI3_RX_DMA_NUMBER 2 -#define RTE_SPI3_RX_DMA_CHANNEL 1 -#define RTE_SPI3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Channel <2=>2 -// Selects DMA Channel (only Channel 2 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI3_TX_DMA 0 -#define RTE_SPI3_TX_DMA_NUMBER 2 -#define RTE_SPI3_TX_DMA_CHANNEL 2 -#define RTE_SPI3_TX_DMA_PRIORITY 0 - -// - - -// SDIO (Secure Digital Input/Output) [Driver_MCI0] -// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI -#define RTE_SDIO 0 - -// SDIO Peripheral Bus -// SDIO_CK Pin <0=>PC12 -#define RTE_SDIO_CK_PORT_ID 0 -#if (RTE_SDIO_CK_PORT_ID == 0) - #define RTE_SDIO_CK_PORT GPIOC - #define RTE_SDIO_CK_PIN 12 -#else - #error "Invalid SDIO_CLK Pin Configuration!" -#endif -// SDIO_CMD Pin <0=>PD2 -#define RTE_SDIO_CMD_PORT_ID 0 -#if (RTE_SDIO_CMD_PORT_ID == 0) - #define RTE_SDIO_CMD_PORT GPIOD - #define RTE_SDIO_CMD_PIN 2 -#else - #error "Invalid SDIO_CMD Pin Configuration!" -#endif -// SDIO_D0 Pin <0=>PC8 -#define RTE_SDIO_D0_PORT_ID 0 -#if (RTE_SDIO_D0_PORT_ID == 0) - #define RTE_SDIO_D0_PORT GPIOC - #define RTE_SDIO_D0_PIN 8 -#else - #error "Invalid SDIO_DAT0 Pin Configuration!" -#endif -// SDIO_D[1 .. 3] -#define RTE_SDIO_BUS_WIDTH_4 1 -// SDIO_D1 Pin <0=>PC9 -#define RTE_SDIO_D1_PORT_ID 0 -#if (RTE_SDIO_D1_PORT_ID == 0) - #define RTE_SDIO_D1_PORT GPIOC - #define RTE_SDIO_D1_PIN 9 -#else - #error "Invalid SDIO_D1 Pin Configuration!" -#endif -// SDIO_D2 Pin <0=>PC10 -#define RTE_SDIO_D2_PORT_ID 0 -#if (RTE_SDIO_D2_PORT_ID == 0) - #define RTE_SDIO_D2_PORT GPIOC - #define RTE_SDIO_D2_PIN 10 -#else - #error "Invalid SDIO_D2 Pin Configuration!" -#endif -// SDIO_D3 Pin <0=>PC11 -#define RTE_SDIO_D3_PORT_ID 0 -#if (RTE_SDIO_D3_PORT_ID == 0) - #define RTE_SDIO_D3_PORT GPIOC - #define RTE_SDIO_D3_PIN 11 -#else - #error "Invalid SDIO_D3 Pin Configuration!" -#endif -// SDIO_D[1 .. 3] -// SDIO_D[4 .. 7] -#define RTE_SDIO_BUS_WIDTH_8 0 -// SDIO_D4 Pin <0=>PB8 -#define RTE_SDIO_D4_PORT_ID 0 -#if (RTE_SDIO_D4_PORT_ID == 0) - #define RTE_SDIO_D4_PORT GPIOB - #define RTE_SDIO_D4_PIN 8 -#else - #error "Invalid SDIO_D4 Pin Configuration!" -#endif -// SDIO_D5 Pin <0=>PB9 -#define RTE_SDIO_D5_PORT_ID 0 -#if (RTE_SDIO_D5_PORT_ID == 0) - #define RTE_SDIO_D5_PORT GPIOB - #define RTE_SDIO_D5_PIN 9 -#else - #error "Invalid SDIO_D5 Pin Configuration!" -#endif -// SDIO_D6 Pin <0=>PC6 -#define RTE_SDIO_D6_PORT_ID 0 -#if (RTE_SDIO_D6_PORT_ID == 0) - #define RTE_SDIO_D6_PORT GPIOC - #define RTE_SDIO_D6_PIN 6 -#else - #error "Invalid SDIO_D6 Pin Configuration!" -#endif -// SDIO_D7 Pin <0=>PC7 -#define RTE_SDIO_D7_PORT_ID 0 -#if (RTE_SDIO_D7_PORT_ID == 0) - #define RTE_SDIO_D7_PORT GPIOC - #define RTE_SDIO_D7_PIN 7 -#else - #error "Invalid SDIO_D7 Pin Configuration!" -#endif -// SDIO_D[4 .. 7] -// SDIO Peripheral Bus - -// Card Detect Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SDIO_CD_EN 1 -#define RTE_SDIO_CD_ACTIVE 0 -#define RTE_SDIO_CD_PORT GPIO_PORT(5) -#define RTE_SDIO_CD_PIN 11 - -// Write Protect Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SDIO_WP_EN 0 -#define RTE_SDIO_WP_ACTIVE 1 -#define RTE_SDIO_WP_PORT GPIO_PORT(0) -#define RTE_SDIO_WP_PIN 10 - -// DMA -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SDIO_DMA_NUMBER 2 -#define RTE_SDIO_DMA_CHANNEL 4 -#define RTE_SDIO_DMA_PRIORITY 0 - -// - - -// CAN1 (Controller Area Network 1) [Driver_CAN1] -// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN -#define RTE_CAN1 0 - -// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 -#define RTE_CAN1_RX_PORT_ID 0 -#if (RTE_CAN1_RX_PORT_ID == 0) -#define RTE_CAN1_RX_PORT GPIOA -#define RTE_CAN1_RX_BIT 11 -#elif (RTE_CAN1_RX_PORT_ID == 1) -#define RTE_CAN1_RX_PORT GPIOB -#define RTE_CAN1_RX_BIT 8 -#elif (RTE_CAN1_RX_PORT_ID == 2) -#define RTE_CAN1_RX_PORT GPIOD -#define RTE_CAN1_RX_BIT 0 -#else -#error "Invalid CAN1_RX Pin Configuration!" -#endif - -// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 -#define RTE_CAN1_TX_PORT_ID 0 -#if (RTE_CAN1_TX_PORT_ID == 0) -#define RTE_CAN1_TX_PORT GPIOA -#define RTE_CAN1_TX_BIT 12 -#elif (RTE_CAN1_TX_PORT_ID == 1) -#define RTE_CAN1_TX_PORT GPIOB -#define RTE_CAN1_TX_BIT 9 -#elif (RTE_CAN1_TX_PORT_ID == 2) -#define RTE_CAN1_TX_PORT GPIOD -#define RTE_CAN1_TX_BIT 1 -#else -#error "Invalid CAN1_TX Pin Configuration!" -#endif - -// - - -// CAN2 (Controller Area Network 2) [Driver_CAN2] -// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN -#define RTE_CAN2 0 - -// CAN2_RX Pin <0=>PB5 <1=>PB12 -#define RTE_CAN2_RX_PORT_ID 0 -#if (RTE_CAN2_RX_PORT_ID == 0) -#define RTE_CAN2_RX_PORT GPIOB -#define RTE_CAN2_RX_BIT 5 -#elif (RTE_CAN2_RX_PORT_ID == 1) -#define RTE_CAN2_RX_PORT GPIOB -#define RTE_CAN2_RX_BIT 12 -#else -#error "Invalid CAN2_RX Pin Configuration!" -#endif - -// CAN2_TX Pin <0=>PB6 <1=>PB13 -#define RTE_CAN2_TX_PORT_ID 0 -#if (RTE_CAN2_TX_PORT_ID == 0) -#define RTE_CAN2_TX_PORT GPIOB -#define RTE_CAN2_TX_BIT 6 -#elif (RTE_CAN2_TX_PORT_ID == 1) -#define RTE_CAN2_TX_PORT GPIOB -#define RTE_CAN2_TX_BIT 13 -#else -#error "Invalid CAN2_TX Pin Configuration!" -#endif - -// - - -// ETH (Ethernet Interface) [Driver_ETH_MAC0] -// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC -#define RTE_ETH 0 - -// MII (Media Independent Interface) -// Enable Media Independent Interface pin configuration -#define RTE_ETH_MII 0 - -// ETH_MII_TX_CLK Pin <0=>PC3 -#define RTE_ETH_MII_TX_CLK_PORT_ID 0 -#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) -#define RTE_ETH_MII_TX_CLK_PORT GPIOC -#define RTE_ETH_MII_TX_CLK_PIN 3 -#else -#error "Invalid ETH_MII_TX_CLK Pin Configuration!" -#endif -// ETH_MII_TXD0 Pin <0=>PB12 -#define RTE_ETH_MII_TXD0_PORT_ID 0 -#if (RTE_ETH_MII_TXD0_PORT_ID == 0) -#define RTE_ETH_MII_TXD0_PORT GPIOB -#define RTE_ETH_MII_TXD0_PIN 12 -#else -#error "Invalid ETH_MII_TXD0 Pin Configuration!" -#endif -// ETH_MII_TXD1 Pin <0=>PB13 -#define RTE_ETH_MII_TXD1_PORT_ID 0 -#if (RTE_ETH_MII_TXD1_PORT_ID == 0) -#define RTE_ETH_MII_TXD1_PORT GPIOB -#define RTE_ETH_MII_TXD1_PIN 13 -#else -#error "Invalid ETH_MII_TXD1 Pin Configuration!" -#endif -// ETH_MII_TXD2 Pin <0=>PC2 -#define RTE_ETH_MII_TXD2_PORT_ID 0 -#if (RTE_ETH_MII_TXD2_PORT_ID == 0) -#define RTE_ETH_MII_TXD2_PORT GPIOC -#define RTE_ETH_MII_TXD2_PIN 2 -#else -#error "Invalid ETH_MII_TXD2 Pin Configuration!" -#endif -// ETH_MII_TXD3 Pin <0=>PB8 -#define RTE_ETH_MII_TXD3_PORT_ID 0 -#if (RTE_ETH_MII_TXD3_PORT_ID == 0) -#define RTE_ETH_MII_TXD3_PORT GPIOB -#define RTE_ETH_MII_TXD3_PIN 8 -#else -#error "Invalid ETH_MII_TXD3 Pin Configuration!" -#endif -// ETH_MII_TX_EN Pin <0=>PB11 -#define RTE_ETH_MII_TX_EN_PORT_ID 0 -#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) -#define RTE_ETH_MII_TX_EN_PORT GPIOB -#define RTE_ETH_MII_TX_EN_PIN 11 -#else -#error "Invalid ETH_MII_TX_EN Pin Configuration!" -#endif -// ETH_MII_RX_CLK Pin <0=>PA1 -#define RTE_ETH_MII_RX_CLK_PORT_ID 0 -#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) -#define RTE_ETH_MII_RX_CLK_PORT GPIOA -#define RTE_ETH_MII_RX_CLK_PIN 1 -#else -#error "Invalid ETH_MII_RX_CLK Pin Configuration!" -#endif -// ETH_MII_RXD0 Pin <0=>PC4 -#define RTE_ETH_MII_RXD0_DEF 0 - -// ETH_MII_RXD1 Pin <0=>PC5 -#define RTE_ETH_MII_RXD1_DEF 0 - -// ETH_MII_RXD2 Pin <0=>PB0 -#define RTE_ETH_MII_RXD2_DEF 0 - -// ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12 -#define RTE_ETH_MII_RXD3_DEF 0 - -// ETH_MII_RX_DV Pin <0=>PA7 -#define RTE_ETH_MII_RX_DV_DEF 0 - -// ETH_MII_RX_ER Pin <0=>PB10 -#define RTE_ETH_MII_RX_ER_PORT_ID 0 -#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) -#define RTE_ETH_MII_RX_ER_PORT GPIOB -#define RTE_ETH_MII_RX_ER_PIN 10 -#else -#error "Invalid ETH_MII_RX_ER Pin Configuration!" -#endif -// ETH_MII_CRS Pin <0=>PA0 -#define RTE_ETH_MII_CRS_PORT_ID 0 -#if (RTE_ETH_MII_CRS_PORT_ID == 0) -#define RTE_ETH_MII_CRS_PORT GPIOA -#define RTE_ETH_MII_CRS_PIN 0 -#else -#error "Invalid ETH_MII_CRS Pin Configuration!" -#endif -// ETH_MII_COL Pin <0=>PA3 -#define RTE_ETH_MII_COL_PORT_ID 0 -#if (RTE_ETH_MII_COL_PORT_ID == 0) -#define RTE_ETH_MII_COL_PORT GPIOA -#define RTE_ETH_MII_COL_PIN 3 -#else -#error "Invalid ETH_MII_COL Pin Configuration!" -#endif - -// Ethernet MAC I/O remapping -// Remap Ethernet pins -#define RTE_ETH_MII_REMAP 0 - -// ETH_MII_RXD0 Pin <1=>PD9 -#define RTE_ETH_MII_RXD0_REMAP 1 - -// ETH_MII_RXD1 Pin <1=>PD10 -#define RTE_ETH_MII_RXD1_REMAP 1 - -// ETH_MII_RXD2 Pin <1=>PD11 -#define RTE_ETH_MII_RXD2_REMAP 1 - -// ETH_MII_RXD3 Pin <1=>PD12 -#define RTE_ETH_MII_RXD3_REMAP 1 - -// ETH_MII_RX_DV Pin <1=>PD8 -#define RTE_ETH_MII_RX_DV_REMAP 1 -// - -// - -#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0)) -#define RTE_ETH_MII_RXD0_PORT GPIOC -#define RTE_ETH_MII_RXD0_PIN 4 -#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1)) -#define RTE_ETH_MII_RXD0_PORT GPIOD -#define RTE_ETH_MII_RXD0_PIN 9 -#else -#error "Invalid ETH_MII_RXD0 Pin Configuration!" -#endif - -#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0)) -#define RTE_ETH_MII_RXD1_PORT GPIOC -#define RTE_ETH_MII_RXD1_PIN 5 -#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1)) -#define RTE_ETH_MII_RXD1_PORT GPIOD -#define RTE_ETH_MII_RXD1_PIN 10 -#else -#error "Invalid ETH_MII_RXD1 Pin Configuration!" -#endif - -#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0)) -#define RTE_ETH_MII_RXD2_PORT GPIOB -#define RTE_ETH_MII_RXD2_PIN 0 -#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1)) -#define RTE_ETH_MII_RXD2_PORT GPIOD -#define RTE_ETH_MII_RXD2_PIN 11 -#else -#error "Invalid ETH_MII_RXD2 Pin Configuration!" -#endif - -#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0)) -#define RTE_ETH_MII_RXD3_PORT GPIOB -#define RTE_ETH_MII_RXD3_PIN 1 -#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1)) -#define RTE_ETH_MII_RXD3_PORT GPIOD -#define RTE_ETH_MII_RXD3_PIN 12 -#else -#error "Invalid ETH_MII_RXD3 Pin Configuration!" -#endif - -#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0)) -#define RTE_ETH_MII_RX_DV_PORT GPIOA -#define RTE_ETH_MII_RX_DV_PIN 7 -#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1)) -#define RTE_ETH_MII_RX_DV_PORT GPIOD -#define RTE_ETH_MII_RX_DV_PIN 8 -#else -#error "Invalid ETH_MII_RX_DV Pin Configuration!" -#endif - -// RMII (Reduced Media Independent Interface) -#define RTE_ETH_RMII 0 - -// ETH_RMII_TXD0 Pin <0=>PB12 -#define RTE_ETH_RMII_TXD0_PORT_ID 0 -#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) -#define RTE_ETH_RMII_TXD0_PORT GPIOB -#define RTE_ETH_RMII_TXD0_PIN 12 -#else -#error "Invalid ETH_RMII_TXD0 Pin Configuration!" -#endif -// ETH_RMII_TXD1 Pin <0=>PB13 -#define RTE_ETH_RMII_TXD1_PORT_ID 0 -#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) -#define RTE_ETH_RMII_TXD1_PORT GPIOB -#define RTE_ETH_RMII_TXD1_PIN 13 -#else -#error "Invalid ETH_RMII_TXD1 Pin Configuration!" -#endif -// ETH_RMII_TX_EN Pin <0=>PB11 -#define RTE_ETH_RMII_TX_EN_PORT_ID 0 -#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) -#define RTE_ETH_RMII_TX_EN_PORT GPIOB -#define RTE_ETH_RMII_TX_EN_PIN 11 -#else -#error "Invalid ETH_RMII_TX_EN Pin Configuration!" -#endif -// ETH_RMII_RXD0 Pin <0=>PC4 -#define RTE_ETH_RMII_RXD0_DEF 0 - -// ETH_RMII_RXD1 Pin <0=>PC5 -#define RTE_ETH_RMII_RXD1_DEF 0 - -// ETH_RMII_REF_CLK Pin <0=>PA1 -#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 -#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) -#define RTE_ETH_RMII_REF_CLK_PORT GPIOA -#define RTE_ETH_RMII_REF_CLK_PIN 1 -#else -#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" -#endif -// ETH_RMII_CRS_DV Pin <0=>PA7 -#define RTE_ETH_RMII_CRS_DV_DEF 0 - -// Ethernet MAC I/O remapping -// Remap Ethernet pins -#define RTE_ETH_RMII_REMAP 0 -// ETH_RMII_RXD0 Pin <1=>PD9 -#define RTE_ETH_RMII_RXD0_REMAP 1 - -// ETH_RMII_RXD1 Pin <1=>PD10 -#define RTE_ETH_RMII_RXD1_REMAP 1 - -// ETH_RMII_CRS_DV Pin <1=>PD8 -#define RTE_ETH_RMII_CRS_DV_REMAP 1 -// - -#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0)) -#define RTE_ETH_RMII_RXD0_PORT GPIOC -#define RTE_ETH_RMII_RXD0_PIN 4 -#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1)) -#define RTE_ETH_RMII_RXD0_PORT GPIOD -#define RTE_ETH_RMII_RXD0_PIN 9 -#else -#error "Invalid ETH_RMII_RXD0 Pin Configuration!" -#endif - -#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0)) -#define RTE_ETH_RMII_RXD1_PORT GPIOC -#define RTE_ETH_RMII_RXD1_PIN 5 -#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1)) -#define RTE_ETH_RMII_RXD1_PORT GPIOD -#define RTE_ETH_RMII_RXD1_PIN 10 -#else -#error "Invalid ETH_RMII_RXD1 Pin Configuration!" -#endif - -#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0)) -#define RTE_ETH_RMII_CRS_DV_PORT GPIOA -#define RTE_ETH_RMII_CRS_DV_PIN 7 -#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1)) -#define RTE_ETH_RMII_CRS_DV_PORT GPIOD -#define RTE_ETH_RMII_CRS_DV_PIN 8 -#else -#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" -#endif - -// - -// Management Data Interface -// ETH_MDC Pin <0=>PC1 -#define RTE_ETH_MDI_MDC_PORT_ID 0 -#if (RTE_ETH_MDI_MDC_PORT_ID == 0) -#define RTE_ETH_MDI_MDC_PORT GPIOC -#define RTE_ETH_MDI_MDC_PIN 1 -#else -#error "Invalid ETH_MDC Pin Configuration!" -#endif -// ETH_MDIO Pin <0=>PA2 -#define RTE_ETH_MDI_MDIO_PORT_ID 0 -#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) -#define RTE_ETH_MDI_MDIO_PORT GPIOA -#define RTE_ETH_MDI_MDIO_PIN 2 -#else -#error "Invalid ETH_MDIO Pin Configuration!" -#endif -// - -// Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled -#define RTE_ETH_REF_CLOCK_ID 0 -#if (RTE_ETH_REF_CLOCK_ID == 0) -#define RTE_ETH_REF_CLOCK 0 -#elif (RTE_ETH_REF_CLOCK_ID == 1) -#define RTE_ETH_REF_CLOCK 1 -#else -#error "Invalid MCO Ethernet Reference Clock Configuration!" -#endif -// - - -// USB Device Full-speed -// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device -#define RTE_USB_DEVICE 0 - -// CON On/Off Pin -// Configure Pin for driving D+ pull-up -// GPIO Pxy (x = A..G, y = 0..15) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_USB_DEVICE_CON_PIN 1 -#define RTE_USB_DEVICE_CON_ACTIVE 0 -#define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1) -#define RTE_USB_DEVICE_CON_BIT 14 - -// - - -// USB OTG Full-speed -#define RTE_USB_OTG_FS 0 - -// Host [Driver_USBH0] -// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host - -#define RTE_USB_OTG_FS_HOST 0 - -// VBUS Power On/Off Pin -// Configure Pin for driving VBUS -// GPIO Pxy (x = A..G, y = 0..15) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_FS_VBUS_PIN 1 -#define RTE_OTG_FS_VBUS_ACTIVE 0 -#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2) -#define RTE_OTG_FS_VBUS_BIT 9 - -// Overcurrent Detection Pin -// Configure Pin for overcurrent detection -// GPIO Pxy (x = A..G, y = 0..15) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_FS_OC_PIN 1 -#define RTE_OTG_FS_OC_ACTIVE 0 -#define RTE_OTG_FS_OC_PORT GPIO_PORT(4) -#define RTE_OTG_FS_OC_BIT 1 -// - -// - - -#endif /* __RTE_DEVICE_H */ diff --git a/Speed_Controller/RTE/Device/STM32F103RB/startup_stm32f10x_md.s b/Speed_Controller/RTE/Device/STM32F103RB/startup_stm32f10x_md.s deleted file mode 100644 index 74da96c..0000000 --- a/Speed_Controller/RTE/Device/STM32F103RB/startup_stm32f10x_md.s +++ /dev/null @@ -1,307 +0,0 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** -;* File Name : startup_stm32f10x_md.s -;* Author : MCD Application Team -;* Version : V3.5.0 -;* Date : 11-March-2011 -;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM -;* toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Configure the clock system -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Tamper - DCD RTC_IRQHandler ; RTC - DCD FLASH_IRQHandler ; Flash - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_2_IRQHandler ; ADC1_2 - DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX - DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD TIM1_BRK_IRQHandler ; TIM1 Break - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line - DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMPER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_2_IRQHandler [WEAK] - EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] - EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_IRQHandler [WEAK] - EXPORT TIM1_UP_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTCAlarm_IRQHandler [WEAK] - EXPORT USBWakeUp_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMPER_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -DMA1_Channel5_IRQHandler -DMA1_Channel6_IRQHandler -DMA1_Channel7_IRQHandler -ADC1_2_IRQHandler -USB_HP_CAN1_TX_IRQHandler -USB_LP_CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_IRQHandler -TIM1_UP_IRQHandler -TIM1_TRG_COM_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTCAlarm_IRQHandler -USBWakeUp_IRQHandler - - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/Speed_Controller/RTE/Device/STM32F103RB/system_stm32f10x.c b/Speed_Controller/RTE/Device/STM32F103RB/system_stm32f10x.c deleted file mode 100644 index 71efc85..0000000 --- a/Speed_Controller/RTE/Device/STM32F103RB/system_stm32f10x.c +++ /dev/null @@ -1,1094 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f10x.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier - * factors, AHB/APBx prescalers and Flash settings). - * This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f10x_xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the HSI (8 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to - * configure the system clock before to branch to main program. - * - * 3. If the system clock source selected by user fails to startup, the SystemInit() - * function will do nothing and HSI still used as system clock source. User can - * add some code to deal with this issue inside the SetSysClock() function. - * - * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on - * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. - * When HSE is used as system clock source, directly or through PLL, and you - * are using different crystal you have to adapt the HSE value to your own - * configuration. - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f10x_system - * @{ - */ - -/** @addtogroup STM32F10x_System_Private_Includes - * @{ - */ - -#include "stm32f10x.h" - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_Defines - * @{ - */ - -/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) - frequency (after reset the HSI is used as SYSCLK source) - - IMPORTANT NOTE: - ============== - 1. After each device reset the HSI is used as System clock source. - - 2. Please make sure that the selected System clock doesn't exceed your device's - maximum frequency. - - 3. If none of the define below is enabled, the HSI is used as System clock - source. - - 4. The System clock configuration functions provided within this file assume that: - - For Low, Medium and High density Value line devices an external 8MHz - crystal is used to drive the System clock. - - For Low, Medium and High density devices an external 8MHz crystal is - used to drive the System clock. - - For Connectivity line devices an external 25MHz crystal is used to drive - the System clock. - If you are using different crystal you have to adapt those functions accordingly. - */ - -#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) -/* #define SYSCLK_FREQ_HSE HSE_VALUE */ - #define SYSCLK_FREQ_24MHz 24000000 -#else -/* #define SYSCLK_FREQ_HSE HSE_VALUE */ -/* #define SYSCLK_FREQ_24MHz 24000000 */ -/* #define SYSCLK_FREQ_36MHz 36000000 */ -/* #define SYSCLK_FREQ_48MHz 48000000 */ -/* #define SYSCLK_FREQ_56MHz 56000000 */ -#define SYSCLK_FREQ_72MHz 72000000 -#endif - -/*!< Uncomment the following line if you need to use external SRAM mounted - on STM3210E-EVAL board (STM32 High density and XL-density devices) or on - STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ -#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) -/* #define DATA_IN_ExtSRAM */ -#endif - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_Variables - * @{ - */ - -/******************************************************************************* -* Clock Definitions -*******************************************************************************/ -#ifdef SYSCLK_FREQ_HSE - uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_24MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_36MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_48MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_56MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_72MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ -#else /*!< HSI Selected as System Clock source */ - uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ -#endif - -__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); - -#ifdef SYSCLK_FREQ_HSE - static void SetSysClockToHSE(void); -#elif defined SYSCLK_FREQ_24MHz - static void SetSysClockTo24(void); -#elif defined SYSCLK_FREQ_36MHz - static void SetSysClockTo36(void); -#elif defined SYSCLK_FREQ_48MHz - static void SetSysClockTo48(void); -#elif defined SYSCLK_FREQ_56MHz - static void SetSysClockTo56(void); -#elif defined SYSCLK_FREQ_72MHz - static void SetSysClockTo72(void); -#endif - -#ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemCoreClock variable. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -void SystemInit (void) -{ - /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ -#ifndef STM32F10X_CL - RCC->CFGR &= (uint32_t)0xF8FF0000; -#else - RCC->CFGR &= (uint32_t)0xF0FF0000; -#endif /* STM32F10X_CL */ - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ - RCC->CFGR &= (uint32_t)0xFF80FFFF; - -#ifdef STM32F10X_CL - /* Reset PLL2ON and PLL3ON bits */ - RCC->CR &= (uint32_t)0xEBFFFFFF; - - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x00FF0000; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; -#else - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) - #ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); - #endif /* DATA_IN_ExtSRAM */ -#endif - - /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ - /* Configure the Flash Latency cycles and enable prefetch buffer */ - SetSysClock(); - -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value - * 8 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value - * 8 MHz or 25 MHz, depedning on the product used), user has to ensure - * that HSE_VALUE is same as the real frequency of the crystal used. - * Otherwise, this function may have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * @param None - * @retval None - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0; - -#ifdef STM32F10X_CL - uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) - uint32_t prediv1factor = 0; -#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock */ - - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - -#ifndef STM32F10X_CL - pllmull = ( pllmull >> 18) + 2; - - if (pllsource == 0x00) - { - /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; - } - else - { - #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; - /* HSE oscillator clock selected as PREDIV1 clock entry */ - SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; - #else - /* HSE selected as PLL clock entry */ - if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) - {/* HSE oscillator clock divided by 2 */ - SystemCoreClock = (HSE_VALUE >> 1) * pllmull; - } - else - { - SystemCoreClock = HSE_VALUE * pllmull; - } - #endif - } -#else - pllmull = pllmull >> 18; - - if (pllmull != 0x0D) - { - pllmull += 2; - } - else - { /* PLL multiplication factor = PLL input clock * 6.5 */ - pllmull = 13 / 2; - } - - if (pllsource == 0x00) - { - /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; - } - else - {/* PREDIV1 selected as PLL clock entry */ - - /* Get PREDIV1 clock source and division factor */ - prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; - - if (prediv1source == 0) - { - /* HSE oscillator clock selected as PREDIV1 clock entry */ - SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; - } - else - {/* PLL2 clock selected as PREDIV1 clock entry */ - - /* Get PREDIV2 division factor and PLL2 multiplication factor */ - prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; - pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; - SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; - } - } -#endif /* STM32F10X_CL */ - break; - - default: - SystemCoreClock = HSI_VALUE; - break; - } - - /* Compute HCLK clock frequency ----------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. - * @param None - * @retval None - */ -static void SetSysClock(void) -{ -#ifdef SYSCLK_FREQ_HSE - SetSysClockToHSE(); -#elif defined SYSCLK_FREQ_24MHz - SetSysClockTo24(); -#elif defined SYSCLK_FREQ_36MHz - SetSysClockTo36(); -#elif defined SYSCLK_FREQ_48MHz - SetSysClockTo48(); -#elif defined SYSCLK_FREQ_56MHz - SetSysClockTo56(); -#elif defined SYSCLK_FREQ_72MHz - SetSysClockTo72(); -#endif - - /* If none of the define above is enabled, the HSI is used as System clock - source (default after reset) */ -} - -/** - * @brief Setup the external memory controller. Called in startup_stm32f10x.s - * before jump to __main - * @param None - * @retval None - */ -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f10x_xx.s/.c before jump to main. - * This function configures the external SRAM mounted on STM3210E-EVAL - * board (STM32 High density devices). This SRAM will be used as program - * data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ -/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is - required, then adjust the Register Addresses */ - - /* Enable FSMC clock */ - RCC->AHBENR = 0x00000114; - - /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ - RCC->APB2ENR = 0x000001E0; - -/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ -/*---------------- SRAM Address lines configuration -------------------------*/ -/*---------------- NOE and NWE configuration --------------------------------*/ -/*---------------- NE3 configuration ----------------------------------------*/ -/*---------------- NBL0, NBL1 configuration ---------------------------------*/ - - GPIOD->CRL = 0x44BB44BB; - GPIOD->CRH = 0xBBBBBBBB; - - GPIOE->CRL = 0xB44444BB; - GPIOE->CRH = 0xBBBBBBBB; - - GPIOF->CRL = 0x44BBBBBB; - GPIOF->CRH = 0xBBBB4444; - - GPIOG->CRL = 0x44BBBBBB; - GPIOG->CRH = 0x44444B44; - -/*---------------- FSMC Configuration ---------------------------------------*/ -/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ - - FSMC_Bank1->BTCR[4] = 0x00001011; - FSMC_Bank1->BTCR[5] = 0x00000200; -} -#endif /* DATA_IN_ExtSRAM */ - -#ifdef SYSCLK_FREQ_HSE -/** - * @brief Selects HSE as System clock source and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockToHSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - -#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 0 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - -#ifndef STM32F10X_CL - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; -#else - if (HSE_VALUE <= 24000000) - { - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; - } - else - { - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; - } -#endif /* STM32F10X_CL */ -#endif - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - - /* Select HSE as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; - - /* Wait till HSE is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_24MHz -/** - * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo24(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 0 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; -#endif - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | - RCC_CFGR_PLLMULL6); - - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); -#else - /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); -#endif /* STM32F10X_CL */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_36MHz -/** - * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo36(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - - /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | - RCC_CFGR_PLLMULL9); - - /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ - - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } - -#else - /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); -#endif /* STM32F10X_CL */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_48MHz -/** - * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo48(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ - - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } - - - /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | - RCC_CFGR_PLLMULL6); -#else - /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); -#endif /* STM32F10X_CL */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_56MHz -/** - * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo56(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 2 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ - - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } - - - /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | - RCC_CFGR_PLLMULL7); -#else - /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); - -#endif /* STM32F10X_CL */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_72MHz -/** - * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo72(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 2 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; - - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ - - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } - - - /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | - RCC_CFGR_PLLMULL9); -#else - /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | - RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); -#endif /* STM32F10X_CL */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#endif - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Speed_Controller/RTE/_Target_1/RTE_Components.h b/Speed_Controller/RTE/_Target_1/RTE_Components.h deleted file mode 100644 index fb78ea6..0000000 --- a/Speed_Controller/RTE/_Target_1/RTE_Components.h +++ /dev/null @@ -1,20 +0,0 @@ - -/* - * Auto generated Run-Time-Environment Component Configuration File - * *** Do not modify ! *** - * - * Project: 'Speed_Controller' - * Target: 'Target 1' - */ - -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - - -/* - * Define the Device Header File: - */ -#define CMSIS_device_header "stm32f10x.h" - - -#endif /* RTE_COMPONENTS_H */ diff --git a/Speed_Controller/RTE/_main/RTE_Components.h b/Speed_Controller/RTE/_main/RTE_Components.h deleted file mode 100644 index 0c94156..0000000 --- a/Speed_Controller/RTE/_main/RTE_Components.h +++ /dev/null @@ -1,20 +0,0 @@ - -/* - * Auto generated Run-Time-Environment Component Configuration File - * *** Do not modify ! *** - * - * Project: 'Speed_Controller' - * Target: 'Main' - */ - -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - - -/* - * Define the Device Header File: - */ -#define CMSIS_device_header "stm32f10x.h" - - -#endif /* RTE_COMPONENTS_H */ diff --git a/Speed_Controller/Speed_Controller.uvprojx b/Speed_Controller/Speed_Controller.uvprojx deleted file mode 100644 index ebb9bba..0000000 --- a/Speed_Controller/Speed_Controller.uvprojx +++ /dev/null @@ -1,514 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - Main - 0x4 - ARM-ADS - 5060528::V5.06 update 5 (build 528)::ARMCC - 0 - - - STM32F103RB - STMicroelectronics - Keil.STM32F1xx_DFP.2.3.0 - http://www.keil.com/pack/ - IRAM(0x20000000,0x5000) IROM(0x08000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) - 0 - $$Device:STM32F103RB$Device\Include\stm32f10x.h - - - - - - - - - - $$Device:STM32F103RB$SVD\STM32F103xx.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\Objects\ - Speed_Controller - 1 - 0 - 0 - 1 - 1 - .\Listings\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -REMAP - DCM.DLL - -pCM3 - SARMCM3.DLL - - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M3" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 8 - 0 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x5000 - - - 1 - 0x8000000 - 0x20000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x8000000 - 0x20000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x5000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - - - - - ..\Peripherals\CAN;..\Peripherals\virtual_com;.\src\ADC;.\src\encoder - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 0 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - - - - - - - - - - - - src - - - main.c - 1 - .\src\main.c - - - - - Peripherals - - - CAN.c - 1 - ..\Peripherals\CAN\CAN.c - - - CAN.h - 5 - ..\Peripherals\CAN\CAN.h - - - virtual_com.c - 1 - ..\Peripherals\virtual_com\virtual_com.c - - - virtual_com.h - 5 - ..\Peripherals\virtual_com\virtual_com.h - - - - - ADC - - - ADC.h - 5 - .\src\ADC\ADC.h - - - ADC.c - 1 - .\src\ADC\ADC.c - - - - - Encoder - - - encoder.c - 1 - .\src\Encoder\encoder.c - - - encoder.h - 5 - .\src\Encoder\encoder.h - - - - - Timer - - - Timer.c - 1 - .\src\Timer\Timer.c - - - Timer.h - 5 - .\src\Timer\Timer.h - - - - - ::CMSIS - - - ::Device - - - - - - - - - - - - - - - - - - - - - - - - RTE\Device\STM32F103RB\RTE_Device.h - - - - - - - - RTE\Device\STM32F103RB\startup_stm32f10x_md.s - - - - - - - - RTE\Device\STM32F103RB\system_stm32f10x.c - - - - - - - - - - diff --git a/Speed_Controller/platformio.ini b/Speed_Controller/platformio.ini new file mode 100644 index 0000000..8d0b57e --- /dev/null +++ b/Speed_Controller/platformio.ini @@ -0,0 +1,25 @@ +; PlatformIO Project Configuration File +; +; Build options: build flags, source filter +; Upload options: custom upload port, speed and extra flags +; Library options: dependencies, extra library storages +; Advanced options: extra scripting +; +; Please visit documentation for the other options and examples +; https://docs.platformio.org/page/projectconf.html + +[platformio] +include_dir = src +src_dir = src +lib_dir = ../Peripherals + +[env:nucleo_f103rb] +platform = ststm32 +board = nucleo_f103rb +framework = cmsis +build_type = debug +debug_tool = stlink +upload_protocol = stlink +debug_build_flags = -Werror -Og -ggdb +; Change MCU frequency +board_build.f_cpu = 36000000L diff --git a/Speed_Controller/src/ADC/ADC.h b/Speed_Controller/src/ADC/ADC.h index 1b08d10..8d23240 100644 --- a/Speed_Controller/src/ADC/ADC.h +++ b/Speed_Controller/src/ADC/ADC.h @@ -1,11 +1,11 @@ -#include "stm32f10x.h" +#ifndef ADC_H +#define ADC_H -#ifndef ADC_MODULE -#define ADC_MODULE +#include "stm32f103xb.h" #define ADC_ZERO_THRESHOLD 0x300 -/** +/** * Initializes an ADC for the regenerative braking toggle */ void ADCInit(void); @@ -15,4 +15,4 @@ void ADCInit(void); */ uint16_t ReadADC(void); -#endif +#endif /* ADC_H */ diff --git a/Speed_Controller/src/Encoder/encoder.h b/Speed_Controller/src/Encoder/encoder.h index 2289ba3..00e2448 100644 --- a/Speed_Controller/src/Encoder/encoder.h +++ b/Speed_Controller/src/Encoder/encoder.h @@ -1,7 +1,7 @@ -#include "stm32f10x.h" +#ifndef ENCODER_H +#define ENCODER_H -#ifndef ENCODER_MODULE -#define ENCODER_MODULE +#include "stm32f103xb.h" #define PEDAL_MAX 0xD0 #define PEDAL_MIN 0x0F @@ -17,4 +17,4 @@ void EncoderInit(void); */ uint16_t EncoderRead(void); -#endif +#endif /* ENCODER_H */ diff --git a/Speed_Controller/src/Timer/Timer.h b/Speed_Controller/src/Timer/Timer.h index 1d75945..8c0293f 100644 --- a/Speed_Controller/src/Timer/Timer.h +++ b/Speed_Controller/src/Timer/Timer.h @@ -1,8 +1,7 @@ -#include "stm32f10x.h" +#ifndef TIMER_H +#define TIMER_H -#define TIM2_PRESCALER 7199 -#define TRUE 1 -#define FALSE 0 +#include "stm32f103xb.h" /** Interrupt handler for Timer 2. */ @@ -23,4 +22,4 @@ void RestartTimer(void); */ void StopTimer(void); -extern int8_t timeoutFlag; +#endif /* TIMER_H */ diff --git a/Speed_Controller/src/clock_init/clock_init.c b/Speed_Controller/src/clock_init/clock_init.c new file mode 100644 index 0000000..1fb0644 --- /dev/null +++ b/Speed_Controller/src/clock_init/clock_init.c @@ -0,0 +1,150 @@ +#include "clock_init.h" + +#define HSE_STARTUP_TIMEOUT 16000 // cycles for roughly 2ms? (0.002s * 8000000 Hz) + +/** + * Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * + * This function should be used only after reset. + */ +void SetSysClockTo36Hsi(void) +{ + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + + /* Flash wait state */ + // Must be set depending on the system clock frequency + // 0 wait states - 0 < SYSCLK <= 24 MHz (default) + // 1 wait state - 24 < SYSCLK <= 48 MHz + // 2 wait states - 48 < SYSCLK <= 72 MHz + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)(0x1 << FLASH_ACR_LATENCY_Pos); + + /* HCLK = SYSCLK (HCLK is for AHB domain; 72MHz max) */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK (PCLK2 is for APB2 domain; 72MHz max) */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK (PCLK1 is for APB1 domain; 36MHz max) */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* PLL configuration: PLLCLK = HSI / 2 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t) ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLMULL9); + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while ((RCC->CR & RCC_CR_PLLRDY) == 0); + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t) ~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL); + + SystemCoreClockUpdate(); +} + +/** + * Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * + * This function should be used only after reset, and requires an external clock signal. + */ +void SetSysClockTo36HseBypass(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE in BYPASS mode (no crystal, oscillator bypassed by an external clock signal) */ + /* On a Nucleo board, this external clock signal comes from the built-in ST Link */ + RCC->CR |= (uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != 0) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Flash wait state */ + // Must be set depending on the system clock frequency + // 0 wait states - 0 < SYSCLK <= 24 MHz (default) + // 1 wait state - 24 < SYSCLK <= 48 MHz + // 2 wait states - 48 < SYSCLK <= 72 MHz + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)(0x1 << FLASH_ACR_LATENCY_Pos); + + /* HCLK = SYSCLK (HCLK is for AHB domain; 72MHz max) */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK (PCLK2 is for APB2 domain; 72MHz max) */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK (PCLK1 is for APB1 domain; 36MHz max) */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t) ~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while ((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t) ~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE / 2 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t) ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while ((RCC->CR & RCC_CR_PLLRDY) == 0); + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t) ~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL); + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + + SystemCoreClockUpdate(); +} diff --git a/Speed_Controller/src/clock_init/clock_init.h b/Speed_Controller/src/clock_init/clock_init.h new file mode 100644 index 0000000..c75e5a2 --- /dev/null +++ b/Speed_Controller/src/clock_init/clock_init.h @@ -0,0 +1,9 @@ +#ifndef CLOCK_INIT_H +#define CLOCK_INIT_H + +#include "stm32f103xb.h" + +void SetSysClockTo36Hsi(void); +void SetSysClockTo36HseBypass(void); + +#endif /* CLOCK_INIT_H */ diff --git a/Speed_Controller/src/main.c b/Speed_Controller/src/main.c index 4ff10c7..2536fee 100644 --- a/Speed_Controller/src/main.c +++ b/Speed_Controller/src/main.c @@ -1,10 +1,11 @@ -#include "stm32f10x.h" +#include "stm32f103xb.h" +#include "clock_init/clock_init.h" #include "ADC/ADC.h" #include "Encoder/encoder.h" +#include "Timer/Timer.h" #include "CAN.h" #include "virtual_com.h" -#include "Timer/Timer.h" #define DRIVE_CONTROL_ID 0x400 #define BATTERY_FULL_MSG 0x622 @@ -18,7 +19,7 @@ #define DEBUG_STATE FALSE #define READ_BATTERY_CHARGE FALSE -#define SEND_CAN_MSG FALSE +#define SEND_CAN_MSG TRUE #define FORWARD 0 From de7d0218bc7cfeffe305e3447a1d6ae3af56ab6e Mon Sep 17 00:00:00 2001 From: a2k-hanlon Date: Thu, 24 Feb 2022 23:51:17 -0800 Subject: [PATCH 02/13] Add CI build for Speed Controller --- .github/workflows/speed_controller.yml | 40 ++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 .github/workflows/speed_controller.yml diff --git a/.github/workflows/speed_controller.yml b/.github/workflows/speed_controller.yml new file mode 100644 index 0000000..9860daf --- /dev/null +++ b/.github/workflows/speed_controller.yml @@ -0,0 +1,40 @@ +name: Speed Controller CI + +on: + # Trigger the workflow on push but only for changes to relevant files + push: + paths: + - 'Speed_Controller/**' + - '.github/workflows/speed_controller.yml' + + # Allow running this workflow manually from the Actions tab + workflow_dispatch: + +jobs: + build: + runs-on: ubuntu-latest + + steps: + - uses: actions/checkout@v2 + - name: Cache pip + uses: actions/cache@v2 + with: + path: ~/.cache/pip + key: ${{ runner.os }}-pip-${{ hashFiles('**/requirements.txt') }} + restore-keys: | + ${{ runner.os }}-pip- + - name: Cache PlatformIO + uses: actions/cache@v2 + with: + path: ~/.platformio + key: ${{ runner.os }}-${{ hashFiles('**/lockfiles') }} + - name: Set up Python + uses: actions/setup-python@v2 + - name: Install PlatformIO + run: | + python -m pip install --upgrade pip + pip install --upgrade platformio + - name: Run PlatformIO Build + run: | + cd Speed_Controller + pio run -v From 4c996ddc07db8dacb62ea7960b7a2ba02fd9952d Mon Sep 17 00:00:00 2001 From: a2k-hanlon Date: Fri, 25 Feb 2022 00:26:40 -0800 Subject: [PATCH 03/13] Clean up virtual com driver and add baud selection --- Peripherals/virtual_com/virtual_com.c | 122 ++++++++++++++++---------- Peripherals/virtual_com/virtual_com.h | 34 +++---- 2 files changed, 87 insertions(+), 69 deletions(-) diff --git a/Peripherals/virtual_com/virtual_com.c b/Peripherals/virtual_com/virtual_com.c index b52cd00..5264c2a 100644 --- a/Peripherals/virtual_com/virtual_com.c +++ b/Peripherals/virtual_com/virtual_com.c @@ -1,92 +1,124 @@ /** * Function implementations for enabling virtual com logging. */ + #include "virtual_com.h" +// Baud = fclk / (16 * (mantissa + fraction / 16)) +typedef struct { + uint16_t mantissa; + uint8_t fraction; +} BaudParams_t; + +static const BaudParams_t baudParams[] = { + {234, 6}, // 9600 + {117, 3}, // 19200 + {39, 1}, // 57600 + {19, 8} // 115200 (actually 115384) +}; + /** - * Initializes virtual com. + * Initializes USART2 peripheral for virtual COM + * + * Assumes APB1 clock (PCLK1) of 36MHz + * + * @param baud Baud rate for serial communication */ -void VirtualComInit() +void VirtualComInit(BaudRate_t baud) { - // Enable GPIOA clock, AFIO - RCC->APB2ENR |= 0x5UL; - GPIOA->CRL &= ~(0xFF00UL); - GPIOA->CRL |= 0x4B00UL; - + // Enable GPIOA and AFIO clocks + RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_AFIOEN; + // Set up UART pins A2 and A3: + // Pin A3 as imput + // Pin A2 as alternate function output push-pull (highest speed) + GPIOA->CRL &= ~(GPIO_CRL_CNF3 | GPIO_CRL_MODE3 | GPIO_CRL_CNF2 | GPIO_CRL_MODE2); + GPIOA->CRL |= (0x1 << GPIO_CRL_CNF3_Pos) | (0x0 << GPIO_CRL_MODE3_Pos) | + (0x2 << GPIO_CRL_CNF2_Pos) | (0x3 << GPIO_CRL_MODE2_Pos); + // Enable USART2 clock - RCC->APB1ENR |= (0x1UL << 17); + RCC->APB1ENR |= RCC_APB1ENR_USART2EN; + USART2->CR2 = 0; USART2->CR3 = 0; - USART2->CR1 |= 0xC; - - // By Default, set baudrate to 9600 - USART2->BRR = 0xEA6UL; - + USART2->CR1 |= USART_CR1_TE | USART_CR1_RE; // Enable both receive and transmit + + // Set baudrate + // Baud = fclk / (16 * (mantissa + fraction / 16)) + USART2->BRR = (baudParams[baud].mantissa << USART_BRR_DIV_Mantissa_Pos) | + (baudParams[baud].fraction << USART_BRR_DIV_Fraction_Pos); + // Enable USART2 - USART2->CR1 |= 0x1 << 13; - + USART2->CR1 |= USART_CR1_UE; } /** - * Sends ASCII character through USART. + * Sends ASCII character through USART * - * @Param c: transmitted character + * @param c transmitted character */ void SendChar(char c) { // Write data to data register - USART2->DR = 0xFF & ((uint8_t) c); - + USART2->DR = 0xFF & ((uint8_t)c); + // Poll until character is transmitted - while (!((USART2->SR >> 7) & 0x1)); - - // For testing only (to mock hardware) - #ifdef TEST + while (!(USART2->SR & USART_SR_TXE)); + +// For testing only (to mock hardware) +#ifdef TEST USART2->SR = 0; - #endif +#endif } /** - * Sends string through USART. + * Sends string through USART * - * @Param str: transmitted string + * @param str transmitted string */ - void SendString(char* str) - { +void SendString(char *str) +{ int i; - + // Send each character separately for (i = 0; str[i] != '\0'; i++) { SendChar(str[i]); } - } +} /** * Sends 32-bit unsigned integer through USART (with padded zeros) - * Number will be represented in hexadecimal. - * - * @Param i: transmitted 32-bit unsigned integer + * Number will be represented in hexadecimal + * + * @param i transmitted 32-bit unsigned integer */ void SendInt(uint32_t i) { int index; - - SendChar(0x30); - SendChar(0x58); - + + SendChar('0'); + SendChar('x'); + for (index = 7; index >= 0; index--) { // Divide integer into half-bytes and send them separately - SendChar("0123456789ABCDEF"[(i >> (index*4)) & 0xFUL]); + SendChar("0123456789ABCDEF"[(i >> (index * 4)) & 0xFUL]); } } - - /** - * Sends a new line through USART + +/** + * Sends a CRLF new line through USART */ void SendLine(void) - { - SendChar(0xA); // Sends a line break - SendChar(0xD); // Moves cursor back to start of line - } +{ + SendChar('\r'); + SendChar('\n'); +} + +/** + * Sends a carriage return through USART, moving cursor back to start of current line + */ +void SendCR(void) +{ + SendChar('\r'); +} diff --git a/Peripherals/virtual_com/virtual_com.h b/Peripherals/virtual_com/virtual_com.h index e8f7436..0bbb3fb 100644 --- a/Peripherals/virtual_com/virtual_com.h +++ b/Peripherals/virtual_com/virtual_com.h @@ -11,7 +11,6 @@ * * If required, this implementation could be changed to interrupt-based, * with a transmitting/receiving queue and hardware control. - * */ #ifndef VIRTUAL_COM_H @@ -19,31 +18,18 @@ #include "stm32f103xb.h" -/** - * Sends ASCII character through USART. - * - * @Param c: transmitted character - */ -void SendChar(char c); +typedef enum { + BAUD_9600 = 0, + BAUD_19200 = 1, + BAUD_57600 = 2, + BAUD_115200 = 3 // CAUTION: probably works but clock division isn't bang on - has 0.15% error +} BaudRate_t; -/** - * Sends string through USART. - * - * @Param str: transmitted string - */ - void SendString(char* c); - -/** - * Sends 32-bit unsigned integer through USART (with padded zeros) - * Number will be represented in hexadecimal. - * - * @Param i: transmitted 32-bit unsigned integer - */ +void VirtualComInit(BaudRate_t baud); +void SendChar(char c); +void SendString(char* c); void SendInt(uint32_t i); - -/** - * Sends a new line through USART - */ void SendLine(void); +void SendCR(void); #endif /* VIRTUAL_COM_H */ From 766519bb7e16abd21202d442ac3b8debb5b6d23c Mon Sep 17 00:00:00 2001 From: a2k-hanlon Date: Fri, 25 Feb 2022 00:27:45 -0800 Subject: [PATCH 04/13] Clean up RTC driver --- Peripherals/RTC/RTC.c | 55 +++++++++++++++++++++---------------------- Peripherals/RTC/RTC.h | 5 +--- 2 files changed, 28 insertions(+), 32 deletions(-) diff --git a/Peripherals/RTC/RTC.c b/Peripherals/RTC/RTC.c index 636d378..a227f4b 100644 --- a/Peripherals/RTC/RTC.c +++ b/Peripherals/RTC/RTC.c @@ -1,34 +1,33 @@ #include "RTC.h" -/** Initializes the RTC Clock with the LSE Oscillator on the Nucleo-64 board, - using a prescalar value defined as a constant RTC_PRESCALAR. -**/ +/** + * Initializes the RTC Clock with the LSE Oscillator on the Nucleo-64 board, + * using a prescalar value defined as a constant RTC_PRESCALAR. + */ void RTCinit(void) { // Enable the Clocks - - RCC->APB1ENR |= 0x1 << 27; // Enable Backup Interface Clock - RCC->APB1ENR |= 0x1 << 28; // Enable Power Interface Clock - - //Set LSE Oscillator from Nucleo-64 Board to be RTC Clock - - PWR->CR |= 0x1 << 8; // Disable Write Protection to Backup Domain - RCC->BDCR |= 0x1 << 16; // Resets the entire Backup Domain as a precaution - RCC->BDCR &= ~(0x1 << 16); // Clear the bit from the Backup Domain Reset - RCC->BDCR |= 0x1; // Enable the LSE Clock (32.768 Khz) - - while (((RCC->BDCR >> 1) & 0x1) != 0x1); //While the LSE Clock is not stable yet, - - RCC->BDCR |= 0x1 << 8; // Set LSE Clock as RTC Clock - RCC->BDCR |= 0x11 << 15; // Enable RTC Clock - - //Configure RTC Clock - - RTC->CRL |= 0x1 << 4; // Enter RTC Configuration Mode - - RTC->PRLH = RTC_PRESCALAR >> 16; //Set Prescalar value to RTC_PRESCALAR + RCC->APB1ENR |= RCC_APB1ENR_BKPEN; // Enable Backup Interface Clock + RCC->APB1ENR |= RCC_APB1ENR_PWREN; // Enable Power Interface Clock + + // Set LSE Oscillator from Nucleo-64 Board to be RTC Clock + + PWR->CR |= PWR_CR_DBP; // Disable Write Protection to Backup Domain + RCC->BDCR |= RCC_BDCR_BDRST; // Resets the entire Backup Domain as a precaution + RCC->BDCR &= ~RCC_BDCR_BDRST; // Clear the bit from the Backup Domain Reset + RCC->BDCR |= RCC_BDCR_LSEON; // Enable the LSE Clock (32.768 Khz) + + while (!(RCC->BDCR & RCC_BDCR_LSERDY)); // While the LSE Clock is not stable yet, + + RCC->BDCR |= RCC_BDCR_RTCSEL_LSE; // Set LSE Clock as RTC Clock + RCC->BDCR |= RCC_BDCR_RTCEN; // Enable RTC Clock + + // Configure RTC + + RTC->CRL |= RTC_CRL_CNF; // Enter RTC Configuration Mode + + RTC->PRLH = RTC_PRESCALAR >> 16; // Set Prescalar value to RTC_PRESCALAR RTC->PRLL = 0xFFFF & RTC_PRESCALAR; - - RTC->CRL &= ~(0x1 << 4); // Exit RTC Configuration Mode - -} \ No newline at end of file + + RTC->CRL &= ~RTC_CRL_CNF; // Exit RTC Configuration Mode +} diff --git a/Peripherals/RTC/RTC.h b/Peripherals/RTC/RTC.h index e35a37c..1a1346d 100644 --- a/Peripherals/RTC/RTC.h +++ b/Peripherals/RTC/RTC.h @@ -3,11 +3,8 @@ #include "stm32f103xb.h" -#define RTC_PRESCALAR 2184 +#define RTC_PRESCALAR 2184 -/** Initializes the RTC Clock with the LSE Oscillator on the Nucleo-64 board, - using a prescalar value defined as a constant RTC_PRESCALAR. -**/ void RTCinit(void); #endif /* RTC_H */ From 79e10c324eeb43ef9ab075a6e185054e2c3775e7 Mon Sep 17 00:00:00 2001 From: a2k-hanlon Date: Fri, 25 Feb 2022 00:31:09 -0800 Subject: [PATCH 05/13] Clean up timer driver in Speed Controller --- Speed_Controller/src/Timer/Timer.c | 105 +++++++++++++++++------------ Speed_Controller/src/Timer/Timer.h | 21 ++---- 2 files changed, 69 insertions(+), 57 deletions(-) diff --git a/Speed_Controller/src/Timer/Timer.c b/Speed_Controller/src/Timer/Timer.c index ef54dd9..511d01e 100644 --- a/Speed_Controller/src/Timer/Timer.c +++ b/Speed_Controller/src/Timer/Timer.c @@ -1,61 +1,82 @@ #include "Timer.h" -int8_t timeoutFlag = FALSE; +#define TRUE 1 +#define FALSE 0 -/** Interrupt handler for Timer 2. +static volatile int8_t timeoutFlag = FALSE; + +/** + * Initializes a timer in one pulse mode to trigger a timing interrupt after a set interval + * + * Assumes APB2 timer clock of 36MHz + * + * @param period Period for triggering the timing interrupt in ms (must be < 65535 / 10) */ -void TIM2_IRQHandler(void) +void TimerInit(unsigned int period) { - - if (TIM2->SR & 0x1){ - - //Set a flag for action here. - timeoutFlag = TRUE; - - TIM2->SR &= ~(0x1); //reset the update interrupt flag - } - + RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; // Enable TIM2 clock + + TIM2->PSC = TIM2_PRESCALER; // Processor speed is 36MHz; set prescaler value for a clock frequency of 10kHz + + TIM2->CR1 &= ~TIM_CR1_DIR; // Set counter to upcount + TIM2->CR1 &= ~TIM_CR1_CKD; // Set the timer to use default clock division + TIM2->CR1 |= TIM_CR1_OPM; // Set the timer to use one pulse mode + + TIM2->ARR = 10 * period - 1;// Set autoreload value to set the period + + TIM2->DIER |= TIM_DIER_UIE; // Enable timing interrupt + NVIC_EnableIRQ(TIM2_IRQn); // Setup interrupt handler + + DBGMCU->CR |= DBGMCU_CR_DBG_TIM2_STOP; // Halt TIM2 upon debug halt + + TIM2->CR1 |= TIM_CR1_CEN; // Enable TIM2 } -/** Initializes a timer to trigger a timing interrupt periodically - * @param period: period for triggering the timing interrupt in ms +/** + * Restarts the counter on the timer */ -void TimerInit(int period){ - - RCC->APB1ENR |= 0x1; //enable TIM2 - - TIM2->PSC = TIM2_PRESCALER; //Processor speed is ~72MHZ, so set prescaler value for scaling, clock frequency of 10kHz - - TIM2->CR1 &= ~(0x1UL << 4); //set counter to upcount - - TIM2->ARR &= 0; - - TIM2->ARR = 10*period; //set autoreload to reset every period - - TIM2->CR1 &= (0x11UL << 8); //set the timer to use default clock division - - TIM2->CR1 |= 0x1UL << 3; //set the timer to use one pulse mode - - TIM2->CR1 |= 0x1UL; //enable TIM2 - - TIM2->DIER |= 0x1UL; //enable timing interrupt - NVIC_EnableIRQ(TIM2_IRQn); //setup interrupt handler +void RestartTimer(void) +{ + TIM2->CNT = 0; + TIM2->CR1 |= TIM_CR1_CEN; // Re-enable TIM2 } /** - * Restarts the counter on the timer + * Stops the counter on the timer */ -void RestartTimer(void){ - TIM2->CNT = 0x1; - TIM2->CR1 |= 0x1UL; //re-enable TIM2 +void StopTimer(void) +{ + TIM2->CR1 &= ~TIM_CR1_CEN; // Disable TIM2 +} +/** + * Get the timer timeout flag to see if the timer period has elapsed + * + * @returns The state of the timeout flag + */ +uint8_t GetTimeoutFlag(void) +{ + return timeoutFlag; } /** - * Stops the counter on the timer + * Clear the timer timeout flag */ -void StopTimer(void){ - TIM2->CR1 &= ~(0x1UL); //disable TIM2 - +void ClearTimeoutFlag(void) +{ + timeoutFlag = FALSE; } +/** + * Interrupt handler for Timer 2 + */ +void TIM2_IRQHandler(void) +{ + if (TIM2->SR & TIM_SR_UIF) // If update interrupt flag is set + { + // Set a flag for action here + timeoutFlag = TRUE; + + TIM2->SR &= ~(TIM_SR_UIF); // Clear the update interrupt flag + } +} diff --git a/Speed_Controller/src/Timer/Timer.h b/Speed_Controller/src/Timer/Timer.h index 8c0293f..9ea2d81 100644 --- a/Speed_Controller/src/Timer/Timer.h +++ b/Speed_Controller/src/Timer/Timer.h @@ -3,23 +3,14 @@ #include "stm32f103xb.h" -/** Interrupt handler for Timer 2. - */ -void TIM2_IRQHandler(void); +// Processor speed is 36MHz; set prescaler value for a clock frequency of 10kHz +#define TIM2_PRESCALER (3600 - 1) -/** Initializes a timer to trigger a timing interrupt periodically - * @param period: period for triggering the timing interrupt in ms - */ -void TimerInit(int period); - -/** - * Restarts the counter on the timer - */ +void TimerInit(unsigned int period); void RestartTimer(void); - -/** - * Stops the counter on the timer - */ void StopTimer(void); +uint8_t GetTimeoutFlag(void); +void ClearTimeoutFlag(void); +// void TIM2_IRQHandler(void) is defined in this module #endif /* TIMER_H */ From 2f4a444d844df653942cf0c5f1aec423393ff09b Mon Sep 17 00:00:00 2001 From: a2k-hanlon Date: Fri, 25 Feb 2022 00:35:04 -0800 Subject: [PATCH 06/13] Clean up encoder driver in Speed Controller --- Speed_Controller/src/Encoder/encoder.c | 106 ++++++++++++------------- Speed_Controller/src/Encoder/encoder.h | 9 +-- 2 files changed, 50 insertions(+), 65 deletions(-) diff --git a/Speed_Controller/src/Encoder/encoder.c b/Speed_Controller/src/Encoder/encoder.c index 9e0a1a2..bbf1f1a 100644 --- a/Speed_Controller/src/Encoder/encoder.c +++ b/Speed_Controller/src/Encoder/encoder.c @@ -1,68 +1,60 @@ #include "encoder.h" -#include "virtual_com.h" /** * Initializes the encoder for the accelerator pedal */ -void EncoderInit (void) { - - //Initialize AFIO Clock - RCC->APB2ENR |= 0x1; - - //TIM 1 Enable - RCC->APB2ENR |= 0x1 << 11; - - //Initialize GPIOA Clock - RCC->APB2ENR |= 0x1 << 2; - GPIOA->CRH &= 0; - GPIOA->CRH |= 0x00000044; - - //TIM 1 No Remap - AFIO->MAPR &= ~(0x11 << 6); - - TIM1->CCMR1 |= 0x01; //Map Channel 1 to TI1 - TIM1->CCMR1 |= 0x01 << 8; //Map Channel 2 to TI2 - - TIM1->CCER &= ~(0x1 << 1); - TIM1->CCER &= ~(0x1 << 3); - - TIM1->CCER &= ~(0x1 << 5); - TIM1->CCER &= ~(0x1 << 7); - - TIM1->CCER |= 0x1; - TIM1->CCER |= 0x1 << 4; - - TIM1->SMCR |= 0x011; - - TIM1->CR1 |= 0x1; - +void EncoderInit(void) +{ + // Initialize AFIO Clock + RCC->APB2ENR |= RCC_APB2ENR_AFIOEN; + + // TIM 1 Enable + RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; + + // Initialize GPIOA Clock + RCC->APB2ENR |= RCC_APB2ENR_IOPAEN; + // Configure pins A8 and A9 as inputs + GPIOA->CRH &= ~(GPIO_CRH_CNF9 | GPIO_CRH_MODE9 | GPIO_CRH_CNF8 | GPIO_CRH_MODE8); + GPIOA->CRH |= (0x1 << GPIO_CRH_CNF9_Pos) | (0x0 << GPIO_CRH_MODE9_Pos) | + (0x1 << GPIO_CRH_CNF8_Pos) | (0x0 << GPIO_CRH_MODE8_Pos); + + // TIM 1 no pin remap + AFIO->MAPR &= ~AFIO_MAPR_TIM1_REMAP; + + TIM1->CCMR1 |= 0x1 << TIM_CCMR1_CC1S_Pos; // Map capture/compare channel 1 to TI1 (Timer Input 1) + TIM1->CCMR1 |= 0x1 << TIM_CCMR1_CC2S_Pos; // Map capture/compare channel 2 to TI2 (Timer Input 2) + + // Enable capture/compare channels 1 and 2, other channels disabled and all polarities default + TIM1->CCER = (TIM_CCER_CC2E | TIM_CCER_CC1E); + + TIM1->SMCR |= 0x11 << TIM_SMCR_SMS_Pos; // Set timer to encoder mode 3 (clocked by both TI1FP1 and TI2FP2) + + TIM1->CR1 |= TIM_CR1_CEN; // Enable timer } /** * Reads a value from the encoder */ -uint16_t EncoderRead (void) { - - uint16_t Encoder_Reading = TIM1->CNT; - - if (Encoder_Reading < PEDAL_MIN) - { - Encoder_Reading = 0; - } - else if (Encoder_Reading < PEDAL_MAX) - { - Encoder_Reading = Encoder_Reading - PEDAL_MIN; - } - else if (Encoder_Reading < PEDAL_OVERLOAD) - { - Encoder_Reading = PEDAL_MAX - PEDAL_MIN; - } - else - { - Encoder_Reading = 0; - } - - - return Encoder_Reading; - +uint16_t EncoderRead(void) +{ + uint16_t encoderReading = TIM1->CNT; + + if (encoderReading < PEDAL_MIN) + { + encoderReading = 0; + } + else if (encoderReading < PEDAL_MAX) + { + encoderReading -= PEDAL_MIN; + } + else if (encoderReading < PEDAL_OVERLOAD) + { + encoderReading = PEDAL_MAX - PEDAL_MIN; + } + else + { + encoderReading = 0; + } + + return encoderReading; } diff --git a/Speed_Controller/src/Encoder/encoder.h b/Speed_Controller/src/Encoder/encoder.h index 00e2448..ac31884 100644 --- a/Speed_Controller/src/Encoder/encoder.h +++ b/Speed_Controller/src/Encoder/encoder.h @@ -3,18 +3,11 @@ #include "stm32f103xb.h" -#define PEDAL_MAX 0xD0 +#define PEDAL_MAX 0x70 #define PEDAL_MIN 0x0F #define PEDAL_OVERLOAD 0xFF -/** - * Initializes the encoder for the accelerator pedal - */ void EncoderInit(void); - -/** - * Reads a value from the encoder - */ uint16_t EncoderRead(void); #endif /* ENCODER_H */ From 5c010abe2a35f82ca256348cf3bd08ddce5002e0 Mon Sep 17 00:00:00 2001 From: a2k-hanlon Date: Fri, 25 Feb 2022 00:36:08 -0800 Subject: [PATCH 07/13] Correct encoder timer config in Speed Controller --- Speed_Controller/src/Encoder/encoder.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Speed_Controller/src/Encoder/encoder.c b/Speed_Controller/src/Encoder/encoder.c index bbf1f1a..92ae84f 100644 --- a/Speed_Controller/src/Encoder/encoder.c +++ b/Speed_Controller/src/Encoder/encoder.c @@ -27,7 +27,7 @@ void EncoderInit(void) // Enable capture/compare channels 1 and 2, other channels disabled and all polarities default TIM1->CCER = (TIM_CCER_CC2E | TIM_CCER_CC1E); - TIM1->SMCR |= 0x11 << TIM_SMCR_SMS_Pos; // Set timer to encoder mode 3 (clocked by both TI1FP1 and TI2FP2) + TIM1->SMCR |= 0x3 << TIM_SMCR_SMS_Pos; // Set timer to encoder mode 3 (clocked by both TI1FP1 and TI2FP2) TIM1->CR1 |= TIM_CR1_CEN; // Enable timer } From b271f02c4a6180e73646fc2a8e05062e5f859712 Mon Sep 17 00:00:00 2001 From: a2k-hanlon Date: Fri, 25 Feb 2022 01:25:21 -0800 Subject: [PATCH 08/13] Clean up ADC driver in Speed Controller --- Speed_Controller/src/ADC/ADC.c | 71 +++++++++++++++++++--------------- Speed_Controller/src/ADC/ADC.h | 10 ++--- 2 files changed, 43 insertions(+), 38 deletions(-) diff --git a/Speed_Controller/src/ADC/ADC.c b/Speed_Controller/src/ADC/ADC.c index e2e61e8..d45d2e3 100644 --- a/Speed_Controller/src/ADC/ADC.c +++ b/Speed_Controller/src/ADC/ADC.c @@ -1,57 +1,66 @@ #include "ADC.h" +#if ADC_DEBUG #include "virtual_com.h" +#endif /* ADC_DEBUG */ // 0 - 300 hex pot -/** - * Initializes an ADC for the regenerative braking toggle +/** + * Initializes an ADC for the regenerative braking control */ -void ADCInit(void){ - - // Init PA0 to analog input (0x0) - GPIOA->CRL &= ~(0xFUL); - +void ADCInit(void) +{ + // Init PA0 to analog input (CNF and MODE bits all 0) + GPIOA->CRL &= ~(GPIO_CRL_CNF0 | GPIO_CRL_MODE0); + // Configure ADC2 // Enable ADC clock RCC->APB2ENR |= RCC_APB2ENR_ADC2EN; - - // Enable config registers + + // Set config registers // By default, CR1 is set correctly + + // Enable continuous conversion mode ADC2->CR2 |= ADC_CR2_CONT; - - ADC2->SMPR2 |= 0x7UL; - - // Start ADC - ADC2->CR2 |= ADC_CR2_ADON; - ADC2->CR2 |= 0x8UL; - while ((ADC2->CR2 >> 3) & 0x1UL); - ADC2->CR2 |= 0x4UL; - while ((ADC2->CR2 >> 2) & 0x1UL); - ADC2->CR2 |= 0x1UL; - + + // Set ADC2 Channel 0 to longest sampling time (239.5 cycles) + ADC2->SMPR2 |= 0x7UL << ADC_SMPR2_SMP0_Pos; + + ADC2->CR2 |= ADC_CR2_ADON; // Power up ADC + ADC2->CR2 |= ADC_CR2_RSTCAL; // Reset ADC calibration + while (ADC2->CR2 & ADC_CR2_RSTCAL); // Wait for completion of calibration reset + ADC2->CR2 |= ADC_CR2_CAL; // Initialize ADC calibration + while (ADC2->CR2 & ADC_CR2_CAL); // Wait for completion of calibration + ADC2->CR2 |= ADC_CR2_ADON; // Start ADC Conversion } /** * Reads a value from the ADC + * + * If ADC_DEBUG is on (true), prints the reading to the virtual COM as well + * If ADC_REVERSE_READING is on (true), the reading is negated and offset by ADC_ZERO_THRESHOLD + * + * @returns Either the raw ADC reading or (ADC_ZERO_THRESHOLD - raw reading) depending on ADC_REVERSE_READING */ -uint16_t ReadADC(void){ - +uint16_t ReadADC(void) +{ uint16_t ADC_reading = ADC2->DR; - - //SendString(" Raw ADC Reading:"); - //SendInt(ADC_reading); - - /* + +#if ADC_DEBUG + SendString(" Raw ADC Reading:"); + SendInt(ADC_reading); +#endif /* ADC_DEBUG */ + +#if ADC_REVERSE_READING if (ADC_reading > ADC_ZERO_THRESHOLD) { - ADC_reading = 0x000; + ADC_reading = 0x0; } else { ADC_reading = ADC_ZERO_THRESHOLD - ADC_reading; } - */ - +#endif /* ADC_REVERSE_READING */ + return ADC_reading; } - diff --git a/Speed_Controller/src/ADC/ADC.h b/Speed_Controller/src/ADC/ADC.h index 8d23240..c5e098f 100644 --- a/Speed_Controller/src/ADC/ADC.h +++ b/Speed_Controller/src/ADC/ADC.h @@ -3,16 +3,12 @@ #include "stm32f103xb.h" +// Options for ReadADC() +#define ADC_DEBUG 0 +#define ADC_REVERSE_READING 0 #define ADC_ZERO_THRESHOLD 0x300 -/** - * Initializes an ADC for the regenerative braking toggle - */ void ADCInit(void); - -/** - * Reads a value from the ADC - */ uint16_t ReadADC(void); #endif /* ADC_H */ From 0ff2e0ea6be42ceb65ba1579733d294e7f4c7c57 Mon Sep 17 00:00:00 2001 From: a2k-hanlon Date: Fri, 25 Feb 2022 01:48:47 -0800 Subject: [PATCH 09/13] Clean up Speed Controller main.c --- Speed_Controller/src/main.c | 426 +++++++++++++++++++----------------- 1 file changed, 226 insertions(+), 200 deletions(-) diff --git a/Speed_Controller/src/main.c b/Speed_Controller/src/main.c index 2536fee..e7f6742 100644 --- a/Speed_Controller/src/main.c +++ b/Speed_Controller/src/main.c @@ -11,280 +11,306 @@ #define BATTERY_FULL_MSG 0x622 #define BATT_BASE 0x620 -#define ADC_MAX 0xFFF // TODO: find out what the actual ADC_MAX is -#define ADC_MIN 0 // TODO: find out what the actual ADC_MIN is +#define ADC_MAX 0xFFF // TODO: find out what the actual ADC_MAX is +#define ADC_MIN 0 // TODO: find out what the actual ADC_MIN is #define TRUE 1 #define FALSE 0 -#define DEBUG_STATE FALSE +#define PRINT_DEBUG FALSE #define READ_BATTERY_CHARGE FALSE #define SEND_CAN_MSG TRUE #define FORWARD 0 -union { +static union +{ float float_var; - uint8_t chars[4]; + uint8_t byte[4]; } u; -union { +static union +{ float float_var; - uint8_t chars[4]; + uint8_t byte[4]; } v; -CAN_msg_t CAN_drive; - -uint8_t reverse_toggle = 0; -uint8_t old_reverse_toggle = 0; - -/** - * When called it updates the CAN_drive and then sends the CAN_drive to the motor controller - * Takes Current (0.000 - 1.000) you want the car to be at, and Velocity(any number in m/s) you want the car to be at - * Note: NEVER pass in a negative velocity, the forwards and backwards is taken care of with the switch on the dashboard and this function. - */ -void sendMotorCommand(float curr, float vel) -{ - - //Set velocity based on input and the reverse toggle, and also sets the current from the input - if(reverse_toggle == FORWARD) - { - v.float_var = vel; - } else - { - v.float_var = -(vel); - } - - u.float_var = curr; - - #if DEBUG_STATE - SendString(" ,Direction: "); - if(v.float_var > 0) { SendString("Forwards"); } - if(v.float_var < 0) { SendString("Backwards"); } - #endif - - //Set current - CAN_drive.data[4] = u.chars[0]; - CAN_drive.data[5] = u.chars[1]; - CAN_drive.data[6] = u.chars[2]; - CAN_drive.data[7] = u.chars[3]; - - //set velocity - CAN_drive.data[0] = v.chars[0]; - CAN_drive.data[1] = v.chars[1]; - CAN_drive.data[2] = v.chars[2]; - CAN_drive.data[3] = v.chars[3]; - - #if SEND_CAN_MSG - CANSend(&CAN_drive); - #endif - - RestartTimer(); -} - -/** - * When called this will change the direction that the car will be going - */ -void sendReverseToggle() { - //Toggles the dirrection of the car, regardless of that direction - v.float_var = -(v.float_var); +static CAN_msg_t CAN_drive; - CAN_drive.data[0] = v.chars[0]; - CAN_drive.data[1] = v.chars[1]; - CAN_drive.data[2] = v.chars[2]; - CAN_drive.data[3] = v.chars[3]; +static uint8_t reverse_toggle = 0; +static uint8_t old_reverse_toggle = 0; - #if DEBUG_STATE - SendString(" ,Toggle reverse"); - #endif - - #if SEND_CAN_MSG - CANSend(&CAN_drive); - #endif - - RestartTimer(); -} +static void sendMotorCommand(float curr, float vel); +static void sendReverseToggle(void); int main(void) { - + // SetSysClockTo36Hsi(); + SetSysClockTo36HseBypass(); + CANInit(CAN_500KBPS); + EncoderInit(); ADCInit(); TimerInit(200); - VirtualComInit(); - - //Setup of RegenToggle - RCC->APB2ENR |= (0x1 << 4); //Clock C enable - GPIOC->CRH &= ~(0xF); //Reset C8 - GPIOC->CRH |= (0x4); //Enable C8 as Input - - GPIOC->CRL &= ~(0xF << 24); //C6 - GPIOC->CRL |= (0x4 << 24); //C6 - - //CAN receive setup + VirtualComInit(BAUD_115200); + + SendString("RESET RESET RESET RESET RESET RESET \r\n\n\n\n\n"); + + // Setup regen toggle + RCC->APB2ENR |= RCC_APB2ENR_IOPCEN; // Enable GPIO port C clock + GPIOC->CRH &= ~(GPIO_CRH_CNF8 | GPIO_CRH_MODE8); // Reset pin C8 config + GPIOC->CRH |= (GPIO_CRH_CNF8_0); // Enable pin C8 as input + + // Setup reverse toggle + GPIOC->CRL &= ~(GPIO_CRL_CNF6 | GPIO_CRL_MODE6); // Reset pin C6 config + GPIOC->CRL |= (GPIO_CRH_CNF8_0); // Enable pin C6 as input + + // CAN receive setup CAN_msg_t CAN_rx_msg; - - //CAN motor command setup + + // CAN motor command setup CAN_drive.len = 8; CAN_drive.id = DRIVE_CONTROL_ID + 1; - + sendMotorCommand(0, 0); - + volatile uint16_t encoder_reading; volatile uint16_t regen_reading; +#if PRINT_DEBUG + volatile uint16_t encoder_timer_count; +#endif /* PRINT_DEBUG */ uint16_t old_encoder_reading = 0x0000; uint16_t old_regen_reading = 0x0000; - + uint8_t battery_percent = 0x00; uint8_t regen_toggle = 0x00; - while(1) + while (1) { - //Gets all new values + // Gets all new values +#if PRINT_DEBUG + encoder_timer_count = TIM1->CNT; +#endif /* PRINT_DEBUG */ encoder_reading = EncoderRead(); regen_reading = (ReadADC() >> 6) << 6; - regen_toggle = ((GPIOC->IDR >> 8) & 0x1); - reverse_toggle = ((GPIOC->IDR >> 6) & 0x1); - - if(CANMsgAvail()) + regen_toggle = (GPIOC->IDR >> GPIO_IDR_IDR8_Pos) & 0x1; + reverse_toggle = (GPIOC->IDR >> GPIO_IDR_IDR6_Pos) & 0x1; + + if (CANMsgAvail()) { CANReceive(&CAN_rx_msg); - - if(CAN_rx_msg.id == BATT_BASE + 6) + + if (CAN_rx_msg.id == BATT_BASE + 6) { - #if READ_BATTERY_CHARGE - battery_percent = (int8_t) CAN_rx_msg.data[0]; //TODO: Confirm battery percent value in Elithion manual - #else - battery_percent = 70; - #endif +#if READ_BATTERY_CHARGE + battery_percent = (int8_t)CAN_rx_msg.data[0]; // TODO: Confirm battery percent value in Elithion manual +#else /* !READ_BATTERY_CHARGE */ + battery_percent = 70; +#endif /* READ_BATTERY_CHARGE */ } } - if(reverse_toggle != old_reverse_toggle) + if (reverse_toggle != old_reverse_toggle) { sendReverseToggle(); } - #if DEBUG_STATE - //SendString(" rgn tgl: "); - //SendInt(regen_toggle); +#if PRINT_DEBUG + // SendString(" rgn tgl: "); + // SendInt(regen_toggle); - //SendString(" bat prc: "); - //SendInt(battery_percent); + // SendString(" bat prc: "); + // SendInt(battery_percent); - //SendString(" old rgn: "); - //SendInt(old_regen_reading); + // SendString(" old rgn: "); + // SendInt(old_regen_reading); - SendString(" new rgn: "); - SendInt(regen_reading); + SendString(" new rgn: "); + SendInt(regen_reading); - //SendString(" old enc: "); - //SendInt(old_encoder_reading); + // SendString(" old enc: "); + // SendInt(old_encoder_reading); - SendString(" new enc: "); - SendInt(encoder_reading); - #endif + SendString(" new enc: "); + SendInt(encoder_reading); + SendString(" new cnt: "); + SendInt(encoder_timer_count); +#endif /* PRINT_DEBUG */ - //If Regen is on and battery is below 98%, then regenerative braking is enabled - if(regen_toggle == TRUE && battery_percent < 98) + // If Regen is on and battery is below 98%, then regenerative braking is enabled + if (regen_toggle == TRUE && battery_percent < 98) { - /* - regen zero //regen NOT altered //encoder zero //encoder altered --> send drive msg - regen zero //regen NOT altered //encoder NOT zero //encoder altered --> send drive msg - regen zero //regen altered //encoder NOT zero //encoder altered --> send drive msg to go back to accelerating - regen zero //regen altered //encoder NOT zero //encoder NOT altered --> send drive msg to go back to accelerating - - regen zero //regen altered //encoder zero //encoder altered --> send regen msg to set regen to zero - regen zero //regen altered //encoder zero //encoder NOT altered --> send regen msg to set regen to zero - regen NOT zero //regen altered //encoder zero //encoder altered --> send regen msg - regen NOT zero //regen altered //encoder NOT zero //encoder altered --> send regen msg - regen NOT zero //regen altered //encoder zero //encoder NOT altered --> send regen msg - regen NOT zero //regen altered //encoder NOT zero //encoder NOT altered --> send regen msg - - regen zero //regen NOT altered //encoder zero //encoder NOT altered --> don't send any msg; wait for timout or update - regen zero //regen NOT altered //encoder NOT zero //encoder NOT altered --> don't send any msg; wait for timout or update - regen NOT zero //regen NOT altered //encoder zero //encoder altered --> don't send any msg; wait for timeout or update - regen NOT zero //regen NOT altered //encoder zero //encoder NOT altered --> don't send any msg; wait for timeout or update - regen NOT zero //regen NOT altered //encoder NOT zero //encoder altered --> don't send any msg; wait for timeout or update - regen NOT zero //regen NOT altered //encoder NOT zero //encoder NOT altered --> don't send any msg; wait for timout or update - */ - - //a NON altered state - - #if DEBUG_STATE - SendString(" ,rgn en "); - #endif - - //send a new regen message - if( (old_regen_reading != regen_reading) && (regen_reading != 0 || (regen_reading == 0 && encoder_reading == 0))) + /* + regen zero //regen NOT altered //encoder zero //encoder altered --> send drive msg + regen zero //regen NOT altered //encoder NOT zero //encoder altered --> send drive msg + regen zero //regen altered //encoder NOT zero //encoder altered --> send drive msg to go back to accelerating + regen zero //regen altered //encoder NOT zero //encoder NOT altered --> send drive msg to go back to accelerating + + regen zero //regen altered //encoder zero //encoder altered --> send regen msg to set regen to zero + regen zero //regen altered //encoder zero //encoder NOT altered --> send regen msg to set regen to zero + regen NOT zero //regen altered //encoder zero //encoder altered --> send regen msg + regen NOT zero //regen altered //encoder NOT zero //encoder altered --> send regen msg + regen NOT zero //regen altered //encoder zero //encoder NOT altered --> send regen msg + regen NOT zero //regen altered //encoder NOT zero //encoder NOT altered --> send regen msg + + regen zero //regen NOT altered //encoder zero //encoder NOT altered --> don't send any msg; wait for timout or update + regen zero //regen NOT altered //encoder NOT zero //encoder NOT altered --> don't send any msg; wait for timout or update + regen NOT zero //regen NOT altered //encoder zero //encoder altered --> don't send any msg; wait for timeout or update + regen NOT zero //regen NOT altered //encoder zero //encoder NOT altered --> don't send any msg; wait for timeout or update + regen NOT zero //regen NOT altered //encoder NOT zero //encoder altered --> don't send any msg; wait for timeout or update + regen NOT zero //regen NOT altered //encoder NOT zero //encoder NOT altered --> don't send any msg; wait for timout or update + */ + + // a NON altered state + +#if PRINT_DEBUG + SendString(", rgn en "); +#endif /* PRINT_DEBUG */ + + // send a new regen message + if ((old_regen_reading != regen_reading) && (regen_reading != 0 || (regen_reading == 0 && encoder_reading == 0))) { - - #if DEBUG_STATE - SendString(" ,new rgn "); - #endif - //sends knob percentage and velocity - sendMotorCommand((float) regen_reading/ADC_MAX, 0.000); +#if PRINT_DEBUG + SendString(", new rgn "); +#endif /* PRINT_DEBUG */ + // sends knob percentage and velocity + sendMotorCommand((float)regen_reading / ADC_MAX, 0.000); } - //The encoder reading has changed, or no regen is applied at the moment, send a new drive message - else if( (old_encoder_reading != encoder_reading && regen_reading == old_regen_reading && regen_reading == 0) || - (regen_reading == 0 && regen_reading != old_regen_reading && encoder_reading != 0) ) + // The encoder reading has changed, or no regen is applied at the moment, send a new drive message + else if ((old_encoder_reading != encoder_reading && regen_reading == old_regen_reading && regen_reading == 0) || + (regen_reading == 0 && regen_reading != old_regen_reading && encoder_reading != 0)) { - #if DEBUG_STATE - SendString(" ,new drv "); - #endif - - //Sends pedal percentage and velocity - sendMotorCommand((float) encoder_reading/(PEDAL_MAX - PEDAL_MIN), 100.000); +#if PRINT_DEBUG + SendString(", new drv "); +#endif /* PRINT_DEBUG */ + // Sends pedal percentage and velocity + sendMotorCommand((float)encoder_reading / (PEDAL_MAX - PEDAL_MIN), 100.000); } - - } - else + } + else { - #if DEBUG_STATE - SendString(" ,rgn den "); - #endif +#if PRINT_DEBUG + SendString(", rgn den "); +#endif /* PRINT_DEBUG */ - //If the encoder count changed, send new drive CAN message - if(old_encoder_reading != encoder_reading) + // If the encoder count changed, send new drive CAN message + if (old_encoder_reading != encoder_reading) { - #if DEBUG_STATE - SendString(" ,new drv "); - #endif +#if PRINT_DEBUG + SendString(", new drv "); +#endif /* PRINT_DEBUG */ - sendMotorCommand((float) encoder_reading/(PEDAL_MAX - PEDAL_MIN), 100.000); + sendMotorCommand((float)encoder_reading / (PEDAL_MAX - PEDAL_MIN), 100.000); } - } - - //If a timeout occured, send the previously sent CAN drive message - if(timeoutFlag == TRUE) - { - #if DEBUG_STATE - SendString(" ,timout "); - #endif - - #if SEND_CAN_MSG - CANSend(&CAN_drive); - #endif - - timeoutFlag = FALSE; + } + + // If a timeout occured, send the previously sent CAN drive message + if (GetTimeoutFlag() == TRUE) + { +#if PRINT_DEBUG + SendString(", timout "); +#endif /* PRINT_DEBUG */ + +#if SEND_CAN_MSG + CANSend(&CAN_drive); +#endif /* SEND_CAN_MSG */ + + ClearTimeoutFlag(); RestartTimer(); } - + old_regen_reading = regen_reading; old_encoder_reading = encoder_reading; old_reverse_toggle = reverse_toggle; - - #if DEBUG_STATE - SendLine(); - #endif - + +#if PRINT_DEBUG + SendLine(); +#endif /* PRINT_DEBUG */ + } +} + + +/** + * Update the CAN_drive and then sends the CAN_drive to the motor controller + * + * @param curr Current (0.000 - 1.000) you want the car to be at + * @param vel Velocity (any number in m/s) you want the car to be at + * + * @note NEVER pass in a negative velocity, the forwards and backwards is taken care of with + * the switch on the dashboard and this function. + */ +static void sendMotorCommand(float curr, float vel) +{ + // Set velocity based on input and the reverse toggle, and also sets the current from the input + if (reverse_toggle == FORWARD) + { + v.float_var = vel; + } + else + { + v.float_var = -(vel); } - + + u.float_var = curr; + +#if PRINT_DEBUG + SendString(", Direction: "); + if (v.float_var > 0) + { + SendString("Forwards"); + } + if (v.float_var < 0) + { + SendString("Backwards"); + } +#endif /* PRINT_DEBUG */ + + // Set current + CAN_drive.data[4] = u.byte[0]; + CAN_drive.data[5] = u.byte[1]; + CAN_drive.data[6] = u.byte[2]; + CAN_drive.data[7] = u.byte[3]; + + // set velocity + CAN_drive.data[0] = u.byte[0]; + CAN_drive.data[1] = u.byte[1]; + CAN_drive.data[2] = u.byte[2]; + CAN_drive.data[3] = u.byte[3]; + +#if SEND_CAN_MSG + CANSend(&CAN_drive); +#endif /* SEND_CAN_MSG */ + + RestartTimer(); +} + +/** + * Change the direction that the car will be going + */ +static void sendReverseToggle() +{ + // Toggles the dirrection of the car, regardless of that direction + v.float_var = -(v.float_var); + + CAN_drive.data[0] = u.byte[0]; + CAN_drive.data[1] = u.byte[1]; + CAN_drive.data[2] = u.byte[2]; + CAN_drive.data[3] = u.byte[3]; + +#if PRINT_DEBUG + SendString(", Toggle reverse"); +#endif /* PRINT_DEBUG */ + +#if SEND_CAN_MSG + CANSend(&CAN_drive); +#endif /* SEND_CAN_MSG */ + + RestartTimer(); } From f581957666e4cfa88148fb57c29ec199b74680fb Mon Sep 17 00:00:00 2001 From: a2k-hanlon Date: Fri, 25 Feb 2022 01:58:15 -0800 Subject: [PATCH 10/13] Start clean up of CAN driver --- Peripherals/CAN/CAN.c | 276 +++++++++++++++++++++--------------------- Peripherals/CAN/CAN.h | 83 +++++-------- 2 files changed, 164 insertions(+), 195 deletions(-) diff --git a/Peripherals/CAN/CAN.c b/Peripherals/CAN/CAN.c index c14a27a..9c1075e 100644 --- a/Peripherals/CAN/CAN.c +++ b/Peripherals/CAN/CAN.c @@ -1,180 +1,176 @@ - /** - * Function implementations for enabling and using CAN messaging. + * Function implementations for enabling and using CAN messaging */ + #include "CAN.h" #include "virtual_com.h" -CAN_bit_timing_config_t can_configs[6] = {{2, 13, 45}, {2, 15, 20}, {2, 13, 18}, {2, 13, 9}, {2, 15, 4}, {2, 15, 2}}; +const CAN_bit_timing_config_t can_configs[6] = {{2, 13, 45}, {2, 15, 20}, {2, 13, 18}, {2, 13, 9}, {2, 15, 4}, {2, 15, 2}}; - /** - * Initializes the CAN controller with specified bit rate. - * - * @params: bitrate - Specified bitrate. If this value is not one of the defined constants, bit rate will be defaulted to 125KBS + * Initializes the CAN controller with specified bit rate * + * @param bitrate Specified bitrate. If this value is not one of the defined constants, bit rate will be defaulted to 125KBS */ - void CANInit(enum BITRATE bitrate) - { - RCC->APB1ENR |= 0x2000000UL; // Enable CAN clock - RCC->APB2ENR |= 0x1UL; // Enable AFIO clock - AFIO->MAPR &= 0xFFFF9FFF; // reset CAN remap - AFIO->MAPR |= 0x00004000; // et CAN remap, use PB8, PB9 - - RCC->APB2ENR |= 0x8UL; // Enable GPIOB clock - GPIOB->CRH &= ~(0xFFUL); - GPIOB->CRH |= 0xB8UL; // Configure PB8 and PB9 +void CANInit(enum BITRATE bitrate) +{ + RCC->APB1ENR |= 0x2000000UL; // Enable CAN clock + RCC->APB2ENR |= 0x1UL; // Enable AFIO clock + AFIO->MAPR &= 0xFFFF9FFF; // reset CAN remap + AFIO->MAPR |= 0x00004000; // et CAN remap, use PB8, PB9 + + RCC->APB2ENR |= 0x8UL; // Enable GPIOB clock + GPIOB->CRH &= ~(0xFFUL); + GPIOB->CRH |= 0xB8UL; // Configure PB8 and PB9 GPIOB->ODR |= 0x1UL << 8; - - CAN1->MCR = 0x51UL; // Set CAN to initialization mode - - // Set bit rates - CAN1->BTR &= ~(((0x03) << 24) | ((0x07) << 20) | ((0x0F) << 16) | (0x1FF)); - CAN1->BTR |= (((can_configs[bitrate].TS2-1) & 0x07) << 20) | (((can_configs[bitrate].TS1-1) & 0x0F) << 16) | ((can_configs[bitrate].BRP-1) & 0x1FF); - + + CAN1->MCR = 0x51UL; // Set CAN to initialization mode + + // Set bit rates + CAN1->BTR &= ~(((0x03) << 24) | ((0x07) << 20) | ((0x0F) << 16) | (0x1FF)); + CAN1->BTR |= (((can_configs[bitrate].TS2 - 1) & 0x07) << 20) | (((can_configs[bitrate].TS1 - 1) & 0x0F) << 16) | ((can_configs[bitrate].BRP - 1) & 0x1FF); + // Configure Filters to default values - CAN1->FM1R |= 0x1C << 8; // Assign all filters to CAN1 - CAN1->FMR |= 0x1UL; // Set to filter initialization mode - CAN1->FA1R &= ~(0x1UL); // Deactivate filter 0 - CAN1->FS1R |= 0x1UL; // Set first filter to single 32 bit configuration - + CAN1->FM1R |= 0x1C << 8; // Assign all filters to CAN1 + CAN1->FMR |= 0x1UL; // Set to filter initialization mode + CAN1->FA1R &= ~(0x1UL); // Deactivate filter 0 + CAN1->FS1R |= 0x1UL; // Set first filter to single 32 bit configuration + CAN1->sFilterRegister[0].FR1 = 0x0UL; // Set filter registers to 0 CAN1->sFilterRegister[0].FR2 = 0x0UL; // Set filter registers to 0 - CAN1->FM1R &= ~(0x1UL); // Set filter to mask mode - - CAN1->FFA1R &= ~(0x1UL); // Apply filter to FIFO 0 - CAN1->FA1R |= 0x1UL; // Activate filter 0 - - CAN1->FMR &= ~(0x1UL); // Deactivate initialization mode - CAN1->MCR &= ~(0x1UL); // Set CAN to normal mode - - while (CAN1->MSR & 0x1UL); - - } - - void CANSetFilter(uint16_t id) - { - static uint32_t filterID = 0; - - if (filterID == 112) - { - return; - } - - CAN1->FMR |= 0x1UL; // Set to filter initialization mode - - switch(filterID%4) - { - case 0: - // if we need another filter bank, initialize it - CAN1->FA1R |= 0x1UL <<(filterID/4); - CAN1->FM1R |= 0x1UL << (filterID/4); - CAN1->FS1R &= ~(0x1UL << (filterID/4)); - - CAN1->sFilterRegister[filterID/4].FR1 = (id << 5) | (id << 21); - CAN1->sFilterRegister[filterID/4].FR2 = (id << 5) | (id << 21); - break; - case 1: - CAN1->sFilterRegister[filterID/4].FR1 &= 0x0000FFFF; - CAN1->sFilterRegister[filterID/4].FR1 |= id << 21; - break; - case 2: - CAN1->sFilterRegister[filterID/4].FR2 = (id << 5) | (id << 21); - break; - case 3: - CAN1->sFilterRegister[filterID/4].FR2 &= 0x0000FFFF; - CAN1->sFilterRegister[filterID/4].FR2 |= id << 21; - break; - } - filterID++; - CAN1->FMR &= ~(0x1UL); // Deactivate initialization mode - } - -void CANSetFilters(uint16_t* ids, uint8_t num) + CAN1->FM1R &= ~(0x1UL); // Set filter to mask mode + + CAN1->FFA1R &= ~(0x1UL); // Apply filter to FIFO 0 + CAN1->FA1R |= 0x1UL; // Activate filter 0 + + CAN1->FMR &= ~(0x1UL); // Deactivate initialization mode + CAN1->MCR &= ~(0x1UL); // Set CAN to normal mode + + while (CAN1->MSR & 0x1UL); +} + +void CANSetFilter(uint16_t id) +{ + static uint32_t filterID = 0; + + if (filterID == 112) + { + return; + } + + CAN1->FMR |= 0x1UL; // Set to filter initialization mode + + switch (filterID % 4) + { + case 0: + // if we need another filter bank, initialize it + CAN1->FA1R |= 0x1UL << (filterID / 4); + CAN1->FM1R |= 0x1UL << (filterID / 4); + CAN1->FS1R &= ~(0x1UL << (filterID / 4)); + + CAN1->sFilterRegister[filterID / 4].FR1 = (id << 5) | (id << 21); + CAN1->sFilterRegister[filterID / 4].FR2 = (id << 5) | (id << 21); + break; + case 1: + CAN1->sFilterRegister[filterID / 4].FR1 &= 0x0000FFFF; + CAN1->sFilterRegister[filterID / 4].FR1 |= id << 21; + break; + case 2: + CAN1->sFilterRegister[filterID / 4].FR2 = (id << 5) | (id << 21); + break; + case 3: + CAN1->sFilterRegister[filterID / 4].FR2 &= 0x0000FFFF; + CAN1->sFilterRegister[filterID / 4].FR2 |= id << 21; + break; + } + filterID++; + CAN1->FMR &= ~(0x1UL); // Deactivate initialization mode +} + +void CANSetFilters(uint16_t *ids, uint8_t num) { for (int i = 0; i < num; i++) { CANSetFilter(ids[i]); } } - + /** - * Decodes CAN messages from the data registers and populates a - * CAN message struct with the data fields. - * + * Decodes CAN messages from the data registers and populates a + * CAN message struct with the data fields + * * @preconditions A valid CAN message is received - * @params CAN_rx_msg - CAN message struct that will be populated - * + * @param CAN_rx_msg CAN message struct that will be populated */ - void CANReceive(CAN_msg_t* CAN_rx_msg) - { - CAN_rx_msg->id = (CAN1->sFIFOMailBox[0].RIR >> 21) & 0x7FFUL; +void CANReceive(CAN_msg_t *CAN_rx_msg) +{ + CAN_rx_msg->id = (CAN1->sFIFOMailBox[0].RIR >> 21) & 0x7FFUL; CAN_rx_msg->len = (CAN1->sFIFOMailBox[0].RDTR) & 0xFUL; - - CAN_rx_msg->data[0] = 0xFFUL & CAN1->sFIFOMailBox[0].RDLR; + + CAN_rx_msg->data[0] = 0xFFUL & CAN1->sFIFOMailBox[0].RDLR; CAN_rx_msg->data[1] = 0xFFUL & (CAN1->sFIFOMailBox[0].RDLR >> 8); CAN_rx_msg->data[2] = 0xFFUL & (CAN1->sFIFOMailBox[0].RDLR >> 16); CAN_rx_msg->data[3] = 0xFFUL & (CAN1->sFIFOMailBox[0].RDLR >> 24); - CAN_rx_msg->data[4] = 0xFFUL & CAN1->sFIFOMailBox[0].RDHR; + CAN_rx_msg->data[4] = 0xFFUL & CAN1->sFIFOMailBox[0].RDHR; CAN_rx_msg->data[5] = 0xFFUL & (CAN1->sFIFOMailBox[0].RDHR >> 8); CAN_rx_msg->data[6] = 0xFFUL & (CAN1->sFIFOMailBox[0].RDHR >> 16); CAN_rx_msg->data[7] = 0xFFUL & (CAN1->sFIFOMailBox[0].RDHR >> 24); - + CAN1->RF0R |= 0x20UL; - } - +} + /** - * Encodes CAN messages using the CAN message struct and populates the - * data registers with the sent. - * + * Encodes CAN messages using the CAN message struct and populates the + * data registers with the sent + * * @preconditions A valid CAN message is received - * @params CAN_rx_msg - CAN message struct that will be populated - * + * @param CAN_rx_msg CAN message struct that will be populated */ - void CANSend(CAN_msg_t* CAN_tx_msg) - { +void CANSend(CAN_msg_t *CAN_tx_msg) +{ volatile int count = 0; - - CAN1->sTxMailBox[0].TIR = (CAN_tx_msg->id) << 21; - + + CAN1->sTxMailBox[0].TIR = (CAN_tx_msg->id) << 21; + CAN1->sTxMailBox[0].TDTR &= ~(0xF); CAN1->sTxMailBox[0].TDTR |= CAN_tx_msg->len & 0xFUL; - - CAN1->sTxMailBox[0].TDLR = (((uint32_t) CAN_tx_msg->data[3] << 24) | - ((uint32_t) CAN_tx_msg->data[2] << 16) | - ((uint32_t) CAN_tx_msg->data[1] << 8) | - ((uint32_t) CAN_tx_msg->data[0] )); - CAN1->sTxMailBox[0].TDHR = (((uint32_t) CAN_tx_msg->data[7] << 24) | - ((uint32_t) CAN_tx_msg->data[6] << 16) | - ((uint32_t) CAN_tx_msg->data[5] << 8) | - ((uint32_t) CAN_tx_msg->data[4] )); - - CAN1->sTxMailBox[0].TIR |= 0x1UL; - while(CAN1->sTxMailBox[0].TIR & 0x1UL && count++ < 1000000); - - if (!(CAN1->sTxMailBox[0].TIR & 0x1UL)) return; - - //Sends error log to screen - while (CAN1->sTxMailBox[0].TIR & 0x1UL) - { - SendInt(CAN1->ESR); - SendLine(); - SendInt(CAN1->MSR); - SendLine(); - SendInt(CAN1->TSR); - SendLine(); - SendLine(); - } - } - - /** - * Returns whether there are CAN messages available. + + CAN1->sTxMailBox[0].TDLR = (((uint32_t)CAN_tx_msg->data[3] << 24) | + ((uint32_t)CAN_tx_msg->data[2] << 16) | + ((uint32_t)CAN_tx_msg->data[1] << 8) | + ((uint32_t)CAN_tx_msg->data[0])); + CAN1->sTxMailBox[0].TDHR = (((uint32_t)CAN_tx_msg->data[7] << 24) | + ((uint32_t)CAN_tx_msg->data[6] << 16) | + ((uint32_t)CAN_tx_msg->data[5] << 8) | + ((uint32_t)CAN_tx_msg->data[4])); + + CAN1->sTxMailBox[0].TIR |= 0x1UL; + while (CAN1->sTxMailBox[0].TIR & 0x1UL && count++ < 1000000); + + if (!(CAN1->sTxMailBox[0].TIR & 0x1UL)) + { + return; + } + + // Sends error log to screen + while (CAN1->sTxMailBox[0].TIR & 0x1UL) + { + SendInt(CAN1->ESR); + SendLine(); + SendInt(CAN1->MSR); + SendLine(); + SendInt(CAN1->TSR); + SendLine(); + SendLine(); + } +} + +/** + * Returns whether there are CAN messages available * * @returns If pending CAN messages are in the CAN controller - * */ - uint8_t CANMsgAvail(void) - { - return CAN1->RF0R & 0x3UL; +uint8_t CANMsgAvail(void) +{ + return CAN1->RF0R & 0x3UL; } - diff --git a/Peripherals/CAN/CAN.h b/Peripherals/CAN/CAN.h index 9629ff1..ac491ea 100644 --- a/Peripherals/CAN/CAN.h +++ b/Peripherals/CAN/CAN.h @@ -1,87 +1,60 @@ /** * This is the header file for the CAN driver. - * + * * The CAN controller configured will have no ID filters, and the - * bit rate is set to 400KBS. + * bit rate is set to 400KBS. * - * Polling will be required by the user, since the functions executed when CAN + * Polling will be required by the user, since the functions executed when CAN * messages are received are too complex and long, and will not be suitable to - * be placed in a interrupt handler (the alternative is to have the interrupt + * be placed in a interrupt handler (the alternative is to have the interrupt * set a valid bit and poll that bit in the main loop. Unfortunately, clearing - * the interrupt mask means setting the pending number of CAN messages to 0, + * the interrupt mask means setting the pending number of CAN messages to 0, * which means, depending on the rate of messages being received, some messages * will be dropped.) * - * Note: Please define the following fields in the main file + * Note: Please define the following fields in the main file * (or any file that will include this header file): * - CAN_msg_t CAN_rx_msg * - CAN_msg_t CAN_tx_msg */ -#include "stm32f10x.h" - #ifndef CAN_H #define CAN_H -enum BITRATE{CAN_50KBPS, CAN_100KBPS, CAN_125KBPS, CAN_250KBPS, CAN_500KBPS, CAN_1000KBPS}; +#include "stm32f103xb.h" + +enum BITRATE +{ + CAN_50KBPS, + CAN_100KBPS, + CAN_125KBPS, + CAN_250KBPS, + CAN_500KBPS, + CAN_1000KBPS +}; typedef struct { uint16_t id; - uint8_t data[8]; - uint8_t len; + uint8_t data[8]; + uint8_t len; } CAN_msg_t; -typedef const struct +typedef struct { uint8_t TS2; uint8_t TS1; uint8_t BRP; } CAN_bit_timing_config_t; -extern CAN_bit_timing_config_t can_configs[6]; +extern const CAN_bit_timing_config_t can_configs[6]; -/** - * Initializes the CAN controller with specified bit rate. - * - * @params: bitrate - Specified bitrate. If this value is not one of the defined constants, bit rate will be defaulted to 125KBS - * - */ - void CANInit(enum BITRATE bitrate); - -/** - * Decodes CAN messages from the data registers and populates a - * CAN message struct with the data fields. - * - * @preconditions A valid CAN message is received - * @params CAN_rx_msg - CAN message struct that will be populated - * - */ - void CANReceive(CAN_msg_t* CAN_rx_msg); - -/** - * Encodes CAN messages using the CAN message struct and populates the - * data registers with the sent. - * - * @params CAN_rx_msg - CAN message struct that will be populated - * - */ - void CANSend(CAN_msg_t* CAN_tx_msg); - - void CANSetFilter(uint16_t id); - - void CANSetFilters(uint16_t* ids, uint8_t num); - -/** - * Returns whether there are CAN messages available. - * - * @returns If pending CAN messages are in the CAN controller - * - */ - uint8_t CANMsgAvail(void); - - extern CAN_msg_t CAN_rx_msg; // Holds receiving CAN messages - extern CAN_msg_t CAN_tx_msg; // Holds transmitted CAN messagess +void CANInit(enum BITRATE bitrate); +void CANReceive(CAN_msg_t *CAN_rx_msg); +void CANSend(CAN_msg_t *CAN_tx_msg); +void CANSetFilter(uint16_t id); +void CANSetFilters(uint16_t *ids, uint8_t num); +uint8_t CANMsgAvail(void); -#endif +#endif /* CAN_H */ From 4ac61e8da10aaf1a1f8df11df712c0d5b1c68282 Mon Sep 17 00:00:00 2001 From: a2k-hanlon Date: Fri, 25 Feb 2022 02:00:51 -0800 Subject: [PATCH 11/13] Add Peripherals folder to trigger for Speed Controller CI --- .github/workflows/speed_controller.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/speed_controller.yml b/.github/workflows/speed_controller.yml index 9860daf..2672922 100644 --- a/.github/workflows/speed_controller.yml +++ b/.github/workflows/speed_controller.yml @@ -5,6 +5,7 @@ on: push: paths: - 'Speed_Controller/**' + - 'Peripherals/**' - '.github/workflows/speed_controller.yml' # Allow running this workflow manually from the Actions tab From 620def9681e60ed1611274fcfceb36ea5d3e5b17 Mon Sep 17 00:00:00 2001 From: a2k-hanlon Date: Sat, 26 Feb 2022 00:18:03 -0800 Subject: [PATCH 12/13] Complete clean up of CAN driver --- Peripherals/CAN/CAN.c | 159 ++++++++++++++++++++++++++++-------------- Peripherals/CAN/CAN.h | 12 ++-- 2 files changed, 113 insertions(+), 58 deletions(-) diff --git a/Peripherals/CAN/CAN.c b/Peripherals/CAN/CAN.c index 9c1075e..5c18252 100644 --- a/Peripherals/CAN/CAN.c +++ b/Peripherals/CAN/CAN.c @@ -5,7 +5,18 @@ #include "CAN.h" #include "virtual_com.h" -const CAN_bit_timing_config_t can_configs[6] = {{2, 13, 45}, {2, 15, 20}, {2, 13, 18}, {2, 13, 9}, {2, 15, 4}, {2, 15, 2}}; +// For non-connectivity line MCU models, there are 14 filter banks, and +// each bank is configured to hold 4 IDs; 14 * 4 = 56 +#define MAX_NUM_FILTERS 56 + +const CAN_bit_timing_config_t can_configs[6] = { + {2, 13, 45}, // CAN_50KBPS + {2, 15, 20}, // CAN_100KBPS + {2, 13, 18}, // CAN_125KBPS + {2, 13, 9}, // CAN_250KBPS + {2, 15, 4}, // CAN_500KBPS + {2, 15, 2} // CAN_1000KBP +}; /** * Initializes the CAN controller with specified bit rate @@ -14,85 +25,129 @@ const CAN_bit_timing_config_t can_configs[6] = {{2, 13, 45}, {2, 15, 20}, {2, 13 */ void CANInit(enum BITRATE bitrate) { - RCC->APB1ENR |= 0x2000000UL; // Enable CAN clock - RCC->APB2ENR |= 0x1UL; // Enable AFIO clock - AFIO->MAPR &= 0xFFFF9FFF; // reset CAN remap - AFIO->MAPR |= 0x00004000; // et CAN remap, use PB8, PB9 + RCC->APB2ENR |= RCC_APB2ENR_AFIOEN; // Enable AFIO clock + AFIO->MAPR &= ~AFIO_MAPR_CAN_REMAP; // reset CAN remap + AFIO->MAPR |= 0x2 << AFIO_MAPR_CAN_REMAP_Pos; // Set CAN remap, use PB8, PB9 - RCC->APB2ENR |= 0x8UL; // Enable GPIOB clock - GPIOB->CRH &= ~(0xFFUL); - GPIOB->CRH |= 0xB8UL; // Configure PB8 and PB9 - GPIOB->ODR |= 0x1UL << 8; + // Configure PB8 for CAN RX and PB9 for CAN TX + RCC->APB2ENR |= RCC_APB2ENR_IOPBEN; // Enable GPIOB clock + GPIOB->CRH &= ~(GPIO_CRH_CNF9 | GPIO_CRH_MODE9 | GPIO_CRH_CNF8 | GPIO_CRH_MODE8); + GPIOB->CRH |= (0x2 << GPIO_CRH_CNF9_Pos) | (0x3 << GPIO_CRH_MODE9_Pos) | // Alternate function output push-pull, fastest speed + (0x2 << GPIO_CRH_CNF8_Pos) | (0x0 << GPIO_CRH_MODE8_Pos); // Input - CAN1->MCR = 0x51UL; // Set CAN to initialization mode + RCC->APB1ENR |= RCC_APB1ENR_CAN1EN; // Enable CAN clock + + // Enable auto bus management, disable automatic retransmission, and set CAN to initialization mode + // Note: SLEEP and DBF (debug freeze) bits are also cleared + CAN1->MCR = CAN_MCR_ABOM | CAN_MCR_NART | CAN_MCR_INRQ; // Set bit rates - CAN1->BTR &= ~(((0x03) << 24) | ((0x07) << 20) | ((0x0F) << 16) | (0x1FF)); - CAN1->BTR |= (((can_configs[bitrate].TS2 - 1) & 0x07) << 20) | (((can_configs[bitrate].TS1 - 1) & 0x0F) << 16) | ((can_configs[bitrate].BRP - 1) & 0x1FF); + CAN1->BTR &= ~(CAN_BTR_SJW | CAN_BTR_TS2 | CAN_BTR_TS1 | CAN_BTR_BRP); + CAN1->BTR |= (((can_configs[bitrate].TS2 - 1) & 0x7) << CAN_BTR_TS2_Pos) | // Time segment 2 + (((can_configs[bitrate].TS1 - 1) & 0xF) << CAN_BTR_TS1_Pos) | // Time segment 1 + (((can_configs[bitrate].BRP - 1) & 0x1FF) << CAN_BTR_BRP_Pos); // Baud rate prescaler + + // Configure default values + CAN1->FMR |= CAN_FMR_FINIT; // Set to filter initialization mode + CAN1->FMR |= 0x1C << CAN_FMR_CAN2SB_Pos; // Assign all filters to CAN1 + CAN1->FA1R &= ~CAN_FA1R_FACT0; // Deactivate filter 0 + CAN1->FS1R |= CAN_FS1R_FSC0; // Set filter 0 to single 32-bit scale configuration - // Configure Filters to default values - CAN1->FM1R |= 0x1C << 8; // Assign all filters to CAN1 - CAN1->FMR |= 0x1UL; // Set to filter initialization mode - CAN1->FA1R &= ~(0x1UL); // Deactivate filter 0 - CAN1->FS1R |= 0x1UL; // Set first filter to single 32 bit configuration + // Set filter bank 0 filters to 0 + CAN1->sFilterRegister[0].FR1 = 0x0UL; + CAN1->sFilterRegister[0].FR2 = 0x0UL; - CAN1->sFilterRegister[0].FR1 = 0x0UL; // Set filter registers to 0 - CAN1->sFilterRegister[0].FR2 = 0x0UL; // Set filter registers to 0 - CAN1->FM1R &= ~(0x1UL); // Set filter to mask mode + CAN1->FM1R &= ~CAN_FM1R_FBM0; // Set filter to mask mode - CAN1->FFA1R &= ~(0x1UL); // Apply filter to FIFO 0 - CAN1->FA1R |= 0x1UL; // Activate filter 0 + CAN1->FFA1R &= ~CAN_FFA1R_FFA0; // Apply filter to FIFO 0 + CAN1->FA1R |= CAN_FA1R_FACT0; // Activate filter 0 - CAN1->FMR &= ~(0x1UL); // Deactivate initialization mode - CAN1->MCR &= ~(0x1UL); // Set CAN to normal mode + CAN1->FMR &= ~CAN_FMR_FINIT; // Exit filter initialization mode + CAN1->MCR &= ~CAN_MCR_INRQ; // Set CAN to normal mode - while (CAN1->MSR & 0x1UL); + while (CAN1->MSR & 0x1UL); // Wait for CAN to enter normal mode } -void CANSetFilter(uint16_t id) +/** + * Configures the next available CAN receive filter to pass the given ID + * + * @param id The ID to accept + * + * @returns 0 if successful, -1 if all of the filters are in use + */ +int CANSetFilter(uint16_t id) { static uint32_t filterID = 0; - if (filterID == 112) + if (filterID == MAX_NUM_FILTERS) { - return; + return -1; } - CAN1->FMR |= 0x1UL; // Set to filter initialization mode + CAN1->FMR |= CAN_FMR_FINIT; // Enter filter initialization mode + // Configure the next available filter bank + // Note that the leftshifts by 5 and 21 are to align the 11 bit ID to the highest 11 bits of each 16 bit word + // Once a filter bank is initialized, no slot should be left empty (implies an open filter for ID 0) switch (filterID % 4) { case 0: // if we need another filter bank, initialize it - CAN1->FA1R |= 0x1UL << (filterID / 4); - CAN1->FM1R |= 0x1UL << (filterID / 4); - CAN1->FS1R &= ~(0x1UL << (filterID / 4)); + CAN1->FA1R |= 0x1UL << (filterID / 4); // Activate filter + CAN1->FM1R |= 0x1UL << (filterID / 4); // Put filter in identifier list mode + CAN1->FS1R &= ~(0x1UL << (filterID / 4)); // Put filter in dual 16-bit scale configuration + // Assign the new ID to all 4 slots in bank CAN1->sFilterRegister[filterID / 4].FR1 = (id << 5) | (id << 21); CAN1->sFilterRegister[filterID / 4].FR2 = (id << 5) | (id << 21); break; case 1: + // Write the new ID to 2nd slot CAN1->sFilterRegister[filterID / 4].FR1 &= 0x0000FFFF; CAN1->sFilterRegister[filterID / 4].FR1 |= id << 21; break; case 2: + // Write the new ID to 3rd and 4th slots CAN1->sFilterRegister[filterID / 4].FR2 = (id << 5) | (id << 21); break; case 3: + // Write the new ID to the 4th slot CAN1->sFilterRegister[filterID / 4].FR2 &= 0x0000FFFF; CAN1->sFilterRegister[filterID / 4].FR2 |= id << 21; break; } filterID++; - CAN1->FMR &= ~(0x1UL); // Deactivate initialization mode + CAN1->FMR &= ~CAN_FMR_FINIT; // Exit filter initialization mode + + return 0; } -void CANSetFilters(uint16_t *ids, uint8_t num) +/** + * Configures the CAN receive filters to pass the given IDs + * + * This function should only be called once + * + * @param ids Array of IDs to accept + * @param num Size of ids array + * + * @returns 0 if successful, -1 if too many IDs are given, -2 if function has been called before + */ +int CANSetFilters(uint16_t *ids, uint8_t num) { + static int filtersConfigured = 0; + + // Only run once + if (filtersConfigured) return -2; + filtersConfigured = 1; + + if (num > MAX_NUM_FILTERS) return -1; + for (int i = 0; i < num; i++) { CANSetFilter(ids[i]); } + + return 0; } /** @@ -104,8 +159,8 @@ void CANSetFilters(uint16_t *ids, uint8_t num) */ void CANReceive(CAN_msg_t *CAN_rx_msg) { - CAN_rx_msg->id = (CAN1->sFIFOMailBox[0].RIR >> 21) & 0x7FFUL; - CAN_rx_msg->len = (CAN1->sFIFOMailBox[0].RDTR) & 0xFUL; + CAN_rx_msg->id = (CAN1->sFIFOMailBox[0].RIR >> CAN_RI0R_STID_Pos) & 0x7FFUL; // Get 11-bit standard msg ID + CAN_rx_msg->len = CAN1->sFIFOMailBox[0].RDTR & 0xFUL; // Get 4-bit msg length CAN_rx_msg->data[0] = 0xFFUL & CAN1->sFIFOMailBox[0].RDLR; CAN_rx_msg->data[1] = 0xFFUL & (CAN1->sFIFOMailBox[0].RDLR >> 8); @@ -116,7 +171,7 @@ void CANReceive(CAN_msg_t *CAN_rx_msg) CAN_rx_msg->data[6] = 0xFFUL & (CAN1->sFIFOMailBox[0].RDHR >> 16); CAN_rx_msg->data[7] = 0xFFUL & (CAN1->sFIFOMailBox[0].RDHR >> 24); - CAN1->RF0R |= 0x20UL; + CAN1->RF0R |= CAN_RF0R_RFOM0; // Release the RX FIFO 0 output mailbox } /** @@ -130,30 +185,32 @@ void CANSend(CAN_msg_t *CAN_tx_msg) { volatile int count = 0; - CAN1->sTxMailBox[0].TIR = (CAN_tx_msg->id) << 21; + CAN1->sTxMailBox[0].TIR = (CAN_tx_msg->id) << CAN_TI0R_STID_Pos; // Set msg ID - CAN1->sTxMailBox[0].TDTR &= ~(0xF); - CAN1->sTxMailBox[0].TDTR |= CAN_tx_msg->len & 0xFUL; + // Set msg length + CAN1->sTxMailBox[0].TDTR &= ~CAN_TDT0R_DLC; + CAN1->sTxMailBox[0].TDTR |= CAN_tx_msg->len & 0xF; - CAN1->sTxMailBox[0].TDLR = (((uint32_t)CAN_tx_msg->data[3] << 24) | - ((uint32_t)CAN_tx_msg->data[2] << 16) | - ((uint32_t)CAN_tx_msg->data[1] << 8) | - ((uint32_t)CAN_tx_msg->data[0])); CAN1->sTxMailBox[0].TDHR = (((uint32_t)CAN_tx_msg->data[7] << 24) | ((uint32_t)CAN_tx_msg->data[6] << 16) | ((uint32_t)CAN_tx_msg->data[5] << 8) | ((uint32_t)CAN_tx_msg->data[4])); + CAN1->sTxMailBox[0].TDLR = (((uint32_t)CAN_tx_msg->data[3] << 24) | + ((uint32_t)CAN_tx_msg->data[2] << 16) | + ((uint32_t)CAN_tx_msg->data[1] << 8) | + ((uint32_t)CAN_tx_msg->data[0])); - CAN1->sTxMailBox[0].TIR |= 0x1UL; - while (CAN1->sTxMailBox[0].TIR & 0x1UL && count++ < 1000000); + CAN1->sTxMailBox[0].TIR |= CAN_TI0R_TXRQ; // Request transmission + // Wait for transmit mailbox to be empty, or timeout + while (CAN1->sTxMailBox[0].TIR & CAN_TI0R_TXRQ && count++ < 1000000); - if (!(CAN1->sTxMailBox[0].TIR & 0x1UL)) + if (!(CAN1->sTxMailBox[0].TIR & CAN_TI0R_TXRQ)) // If transmit mailbox is empty (ie. transmission successful) { return; } // Sends error log to screen - while (CAN1->sTxMailBox[0].TIR & 0x1UL) + while (CAN1->sTxMailBox[0].TIR & CAN_TI0R_TXRQ) // While transmit mailbox is not empty { SendInt(CAN1->ESR); SendLine(); @@ -166,11 +223,11 @@ void CANSend(CAN_msg_t *CAN_tx_msg) } /** - * Returns whether there are CAN messages available + * Returns the number ofCAN messages available (pending in the RX FIFO) * - * @returns If pending CAN messages are in the CAN controller + * @returns Count of pending CAN messages in the RX FIFO (0-3) */ uint8_t CANMsgAvail(void) { - return CAN1->RF0R & 0x3UL; + return (CAN1->RF0R & CAN_RF0R_RFOM0) >> CAN_RF0R_RFOM0_Pos; } diff --git a/Peripherals/CAN/CAN.h b/Peripherals/CAN/CAN.h index ac491ea..a801f57 100644 --- a/Peripherals/CAN/CAN.h +++ b/Peripherals/CAN/CAN.h @@ -43,18 +43,16 @@ typedef struct typedef struct { - uint8_t TS2; - uint8_t TS1; - uint8_t BRP; + uint8_t TS2; // Time segment 1 + uint8_t TS1; // Time segment 2 + uint8_t BRP; // Baud rate prescaler } CAN_bit_timing_config_t; -extern const CAN_bit_timing_config_t can_configs[6]; - void CANInit(enum BITRATE bitrate); void CANReceive(CAN_msg_t *CAN_rx_msg); void CANSend(CAN_msg_t *CAN_tx_msg); -void CANSetFilter(uint16_t id); -void CANSetFilters(uint16_t *ids, uint8_t num); +int CANSetFilter(uint16_t id); +int CANSetFilters(uint16_t *ids, uint8_t num); uint8_t CANMsgAvail(void); #endif /* CAN_H */ From 5ccb7c5d35b0e63882f51a989d65de4a5b3093f9 Mon Sep 17 00:00:00 2001 From: a2k-hanlon Date: Thu, 24 Mar 2022 22:05:17 -0700 Subject: [PATCH 13/13] Fix accidentally renamed setpoint variables --- Speed_Controller/src/main.c | 46 ++++++++++++++++++------------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/Speed_Controller/src/main.c b/Speed_Controller/src/main.c index e7f6742..89101cd 100644 --- a/Speed_Controller/src/main.c +++ b/Speed_Controller/src/main.c @@ -17,7 +17,7 @@ #define TRUE 1 #define FALSE 0 -#define PRINT_DEBUG FALSE +#define PRINT_DEBUG TRUE #define READ_BATTERY_CHARGE FALSE #define SEND_CAN_MSG TRUE @@ -27,13 +27,13 @@ static union { float float_var; uint8_t byte[4]; -} u; +} current_setpoint; static union { float float_var; uint8_t byte[4]; -} v; +} velocity_setpoint; static CAN_msg_t CAN_drive; @@ -251,38 +251,38 @@ static void sendMotorCommand(float curr, float vel) // Set velocity based on input and the reverse toggle, and also sets the current from the input if (reverse_toggle == FORWARD) { - v.float_var = vel; + velocity_setpoint.float_var = vel; } else { - v.float_var = -(vel); + velocity_setpoint.float_var = -(vel); } - u.float_var = curr; + current_setpoint.float_var = curr; #if PRINT_DEBUG SendString(", Direction: "); - if (v.float_var > 0) + if (velocity_setpoint.float_var > 0) { SendString("Forwards"); } - if (v.float_var < 0) + if (velocity_setpoint.float_var < 0) { SendString("Backwards"); } #endif /* PRINT_DEBUG */ - // Set current - CAN_drive.data[4] = u.byte[0]; - CAN_drive.data[5] = u.byte[1]; - CAN_drive.data[6] = u.byte[2]; - CAN_drive.data[7] = u.byte[3]; - // set velocity - CAN_drive.data[0] = u.byte[0]; - CAN_drive.data[1] = u.byte[1]; - CAN_drive.data[2] = u.byte[2]; - CAN_drive.data[3] = u.byte[3]; + CAN_drive.data[0] = velocity_setpoint.byte[0]; + CAN_drive.data[1] = velocity_setpoint.byte[1]; + CAN_drive.data[2] = velocity_setpoint.byte[2]; + CAN_drive.data[3] = velocity_setpoint.byte[3]; + + // Set current + CAN_drive.data[4] = current_setpoint.byte[0]; + CAN_drive.data[5] = current_setpoint.byte[1]; + CAN_drive.data[6] = current_setpoint.byte[2]; + CAN_drive.data[7] = current_setpoint.byte[3]; #if SEND_CAN_MSG CANSend(&CAN_drive); @@ -297,12 +297,12 @@ static void sendMotorCommand(float curr, float vel) static void sendReverseToggle() { // Toggles the dirrection of the car, regardless of that direction - v.float_var = -(v.float_var); + velocity_setpoint.float_var = -(velocity_setpoint.float_var); - CAN_drive.data[0] = u.byte[0]; - CAN_drive.data[1] = u.byte[1]; - CAN_drive.data[2] = u.byte[2]; - CAN_drive.data[3] = u.byte[3]; + CAN_drive.data[0] = velocity_setpoint.byte[0]; + CAN_drive.data[1] = velocity_setpoint.byte[1]; + CAN_drive.data[2] = velocity_setpoint.byte[2]; + CAN_drive.data[3] = velocity_setpoint.byte[3]; #if PRINT_DEBUG SendString(", Toggle reverse");