Issues with printf function

[mp-17]

Hello everyone,

I tried to use the printf function within a test program, but it does not work. While debugging, I found some potential problems in the system + environment.

TL;DR:

1. If you just need to have a working printf, change this address and this address to 0x90000000.
2. To avoid possible errors with custom programs, remove this file.

Details:

1. The TB checks the write address biu_pad_awaddr against 32'h10015000 to find a write
   https://github.com/T-head-Semi/openc906/blob/main/smart_run/logical/tb/tb.v#L285
   but the fputc function does not store to that address.
2. There are two definitions of the fputc function:
   https://github.com/T-head-Semi/openc906/blob/main/smart_run/tests/lib/clib/fputc.c
   https://github.com/T-head-Semi/openc906/blob/main/smart_run/tests/lib/clib/printf.c
   From what I see, coremark compiles only because the file tests/lib/newlib_wrap/clib/printf.c is overwritten by tests/lib/newlib_wrap/printf.c (https://github.com/T-head-Semi/openc906/blob/main/smart_run/setup/smart_cfg.mk#L59)
3. I suppose that the definition in https://github.com/T-head-Semi/openc906/blob/main/smart_run/tests/lib/clib/printf.c is wrong, as it uses a non-standard instruction to load a value from a shifted address, with the wrong syntax.
4. https://github.com/T-head-Semi/openc906/blob/main/smart_run/tests/lib/clib/fputc.c makes sense, but the address is not the one checked by the TB.
5. I removed the https://github.com/T-head-Semi/openc906/blob/main/smart_run/tests/lib/clib/printf.c file, and fixed the address here and here, and printf now works.
6. The address to be checked cannot be the one suggested, and cannot be the one used by the c910 core. The write of the fputc function must go to the top without stopping at the cache (so it must be in a non-cacheable region). The manual says that when virtual memory is not used, the PMA settings can be found in C906_RTL_FACTORY/gen_rtl/mmu/rtl/sysmap.h. There, we see that up to 0x8fffffff, the region is cacheable (the settings for c910 are different). Then, up to 0xbfffffff, it is not cacheable.
7. If we set the address to 32'h9000_0000 (both in the tb.v and in the fputc.c), printf works.

Be aware that if you want to use peripherals, either the sysmap.h or the APB rules must be changed, as it seems to me that the UART and all the other peripherals are in the cacheable region as well. So, I guess the best thing to do would be to remap the peripherals and the sysmap.h to have something consistent.

Thanks in advance for further suggestions and comments!
Matteo