xuantie: pmu: Support cycles&instructions overflow interrupt #1
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The Sscofpmf spec does not define overflow interrupts for cycles & instructions [1]. But this is indispensable in performance profiling. Xuantie added registers mhpmevent0 and mhpmevent2, with addresses 0x7E0 and 0x7E1 respectively, which are used to configure cycles & instructions. At the same time, mxstatus[8] is newly defined as ofint to control whether the cycles and instructions events of HPCP can generate interrupt 13 (lcofip). When it is 1, an interrupt can be generated, and when it is 0, an interrupt cannot be generated. This patch is used to support the above functions. [1] riscvarchive/riscv-count-overflow#5 Signed-off-by: Chen Pei <[email protected]>
guoren83
approved these changes
Nov 18, 2024
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The Sscofpmf spec does not define overflow interrupts for cycles & instructions [1]. But this is indispensable in performance profiling.
Xuantie added registers mhpmevent0 and mhpmevent2, with addresses 0x7E0 and 0x7E1 respectively, which are used to configure cycles & instructions.
At the same time, mxstatus[8] is newly defined as ofint to control whether the cycles and instructions events of HPCP can generate interrupt 13 (lcofip). When it is 1, an interrupt can be generated, and when it is 0, an interrupt cannot be generated.
This patch is used to support the above functions. Changes to mxstatus will be committed in zsb [2].
[1] riscvarchive/riscv-count-overflow#5
[2] https://github.com/XUANTIE-RV/zero_stage_boot