- Synopsis
-
Tests if a single bit is set.
- Mnemonic
-
th.tst rd, rs1, imm6
- Encoding
{reg:[
{ bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] },
{ bits: 5, name: 'rd' },
{ bits: 3, name: 0x1, attr: ['Arithmetic'] },
{ bits: 5, name: 'rs1' },
{ bits: 6, name: 'imm6' },
{ bits: 6, name: 0x22 },
]}
- Description
-
This instruction tests if a single bit is set. If so, rd will be set to 1. Otherwise, rd will be set to 0.
- Operation
if (reg[rs1] & (1 << imm6))
rd := 1
else
rd := 0- Permission
-
This instruction can be executed in all privilege levels.
- Exceptions
-
This instruction does not trigger any exceptions.
- Included in
| Extension |
|---|
XTheadBs ([xtheadbs]) |