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XuanTie’s vector extension (XTheadVector)

Frozen
 The XTheadVector extension is stable.

Extension version: 1.0.

The XTheadVector extension is not a custom-extension, but a non-standard non-conforming extension. The encoding space of the XTheadVector instructions overlaps with those of the V extension. This encoding space conflict is not on purpose, but the result of issues in the past that have been resolved since. Therefore, the XTheadVector extension and the V extension are in conflict. In other words, tools should not allow to enable the XTheadVector extension and the V extension at the same time and should report an error if both are enabled by the user.

The XTheadVector extension adds 32 vector registers, and six unprivileged CSRs (th.vstart, th.vxsat, th.vxrm, th.vl, th.vtype and th.vlenb) , which also overlap with those of the V extension (vstart, vxsat, vxrm, vl, vtype and vlenb). Similar to the V extension, the XTheadVector extension defines two vector status bits VS ([24:23]) in the mstatus and sstatus CSRs.

The instructions set of XTheadVector overlaps with the V Extension v0.7.1(https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1). But here are some changes:

  • In order to facilitate VLEN calculation, The XTheadVector extension adopts the definition of the V extension to add VLENB unprivileged register th.vlenb.

  • The five unprivileged CSRs vstart, vxsat, vxrm, vl and vtype are prefixed with th., for example, vstart is changed to th.vstart.

  • All instructions are prefixed with th., for example, vmv.v.v is changed to th.vmv.v.v.

  • The extension Zvamo is renamed to XTheadZvamo.

  • The extension Zvlsseg (chapter 7.8) is not a subextension but a mandatory part of XTheadVector.

  • The Chapter 19. Divided Element Extension ('Zvediv') is not part of XTheadVector.

  • Beyond the instructions and pseudo instructions in the referenced specification, the following additional pseudo instructions are defined in order to improve compatibility with RVV 1.0:

    th.vmmv.m vd,vs         => th.vmand.mm vd,vs,vs
th.vneg.v vd,vs         => th.vrsub.vx vd,vs,x0
th.vncvt.x.x.v vd,vs,vm => th.vnsrl.vx vd,vs,x0,vm
th.vfneg.v vd,vs        => th.vfsgnjn.vv vd,vs,vs
th.vfabs.v vd,vs        => th.vfsgnjx.vv vd,vs,vs

While similar to the V Extension v0.7.1, XTheadVector still exhibits some distinctions when compared to the V Extension v1.0 (available at github.com/riscv/riscv-v-spec/releases/tag/v1.0). Here is a comprehensive list of the differences:

  • Different encoding of vsetvl/th.vsetvl.

  • No vsetivli instruction.

  • Cannot configure vta and vma vsetvl instruction, the fixed value is TAMU.

  • No whole register move instructions.

  • No fractional lmul.

  • Different load/store instructions.

  • Different name of vector indexed instructions.

  • Destination vector register cannot overlap source vector register group for vmadc/vmsbc/widen arithmetic/narrow arithmetic.

  • No vlm/vsm instructions.

  • Different vnsrl/vnsra/vfncvt suffix (vv/vx/vi vs wv/wx/wi).

  • Different size of mask mode (1.0 is vl and xtheadvector is vlen).

Availability

The XTheadVector extension is available if and only if all of the following conditions are met:

  • The value of the mvendor CSR is 0x5b7 ('XuanTie')

  • Bit 21 of the misa CSR is 1 ('V')

  • The value of the mimpid CSR is 0

These conditions not only reliably identify existing CPUs with XTheadVector (C906V, C920, and R920), but also ensure that future XuanTie CPUs without XTheadVector won’t be falsely detected (in this case mimpid won’t be 0).