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Pull requests: Xilinx/RapidWright

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Pull requests list

2024.2.0
#1113 opened Nov 22, 2024 by clavin-xlnx • Draft
Tile.getWireConnections() not consistent with Vivado
#1096 opened Nov 6, 2024 by eddieh-xlnx • Draft
@clavin-xlnx
1
[TestSite] Add xcvp1902 SLR test
#1084 opened Oct 16, 2024 by eddieh-xlnx • Draft 2024.2.0
@clavin-xlnx
1
[DesignTools] makeBlackbox() to use phys netlist not logical needs new release Dependent on the next future release
#1044 opened Aug 7, 2024 by eddieh-xlnx • Draft
4
[Interchange] Prototype multi-message support for logical and physical netlists
#1031 opened Jul 13, 2024 by clavin-xlnx Loading…
[RWRoute] Adjust wire base costs + cross SLR estimates
#1030 opened Jul 12, 2024 by eddieh-xlnx • Draft
1
[DesignTools.deletePblock()]: utility to delete a pblock
#1020 opened Jun 30, 2024 by Licheng-Guo Loading…
5
[Interchange] Exports DeviceResources Routing (Wires and Nodes) Info in Multiple Messages
#1017 opened Jun 25, 2024 by clavin-xlnx Loading…
Adding shape support for DREAMPlaceFPGA inputs and Interchange Netlist
#1011 opened Jun 21, 2024 by clavin-xlnx Loading…
3
[TestDeviceResources] Test/verify xcau10p
#1004 opened Jun 13, 2024 by eddieh-xlnx • Draft
Node.getAllWiresInNode() returns empty list when Vivado doesn't bug
#1002 opened Jun 12, 2024 by eddieh-xlnx • Draft
@clavin-xlnx
2
[DeviceResourcesWriter] Output resource timings for US+
#1001 opened Jun 12, 2024 by eddieh-xlnx • Draft
5
[EDIFTools] Adds support for lower hierarchy connection
#944 opened Jan 17, 2024 by clavin-xlnx Loading…
1
Adds a tieoff method for module instances with unconnected inputs
#811 opened Sep 7, 2023 by clavin-xlnx Loading…
6
Draft approach for running tutorials in JUnit tests
#773 opened Jul 27, 2023 by clavin-xlnx • Draft
Add flag to filter static sources
#771 opened Jul 27, 2023 by clavin-xlnx Loading…
Create phys nets from logical
#770 opened Jul 26, 2023 by haydenc-amd Loading…
19
Inconsistent behaviour for Cell.getSitePinFromLogicalPin() bug
#473 opened Jul 14, 2022 by eddieh-xlnx • Draft
6
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