diff --git a/himbaechel/uarch/example/constids.inc b/himbaechel/uarch/example/constids.inc index 29f7c3f779..eca9b10827 100644 --- a/himbaechel/uarch/example/constids.inc +++ b/himbaechel/uarch/example/constids.inc @@ -26,6 +26,18 @@ X(LUT_OUT) X(FF_OUT) X(TILE_CLK) +X(RAM_IN) +X(RAM_OUT) + +X(IO_I) +X(IO_O) +X(IO_T) +X(IO_PAD) +X(GCLK) + +X(CLK_ROUTE) + X(LOGIC) X(BRAM) X(IO) +X(NULL) diff --git a/himbaechel/uarch/example/example.cc b/himbaechel/uarch/example/example.cc index 3e148b4f32..caf70f31bb 100644 --- a/himbaechel/uarch/example/example.cc +++ b/himbaechel/uarch/example/example.cc @@ -183,44 +183,44 @@ struct ExampleImpl : HimbaechelAPI el.type = GraphicElement::TYPE_LINE; el.style = style; int z; - switch (wire_type.index) + switch(tile_type.index) { - case id_LUT_INPUT.index: - z = (tilewire - TILE_WIRE_L0_I0) / 4; - el.x1 = loc.x + 0.10; - el.x2 = el.x1 + 0.05; - el.y1 = loc.y + 0.85 - z * 0.1 - ((tilewire - TILE_WIRE_L0_I0) % 4 + 1) * 0.01; - el.y2 = el.y1; - g.push_back(el); - break; - case id_LUT_OUT.index: - z = tilewire - TILE_WIRE_L0_O; - el.x1 = loc.x + 0.40; - el.x2 = el.x1 + 0.05; - el.y1 = loc.y + 0.85 - z * 0.1 - 0.025; - el.y2 = el.y1; - g.push_back(el); - break; - case id_FF_DATA.index: - z = tilewire - TILE_WIRE_L0_D; - el.x1 = loc.x + 0.50; - el.x2 = el.x1 + 0.05; - el.y1 = loc.y + 0.85 - z * 0.1 - 0.025; - el.y2 = el.y1; - g.push_back(el); - break; - case id_FF_OUT.index: - z = tilewire - TILE_WIRE_L0_Q; - el.x1 = loc.x + 0.80; - el.x2 = el.x1 + 0.05; - el.y1 = loc.y + 0.85 - z * 0.1 - 0.025; - el.y2 = el.y1; - g.push_back(el); - break; - case id_TILE_CLK.index: - switch(tile_type.index) + case id_LOGIC.index: + switch (wire_type.index) { - case id_LOGIC.index: + case id_LUT_INPUT.index: + z = (tilewire - TILE_WIRE_L0_I0) / 4; + el.x1 = loc.x + 0.10; + el.x2 = el.x1 + 0.05; + el.y1 = loc.y + 0.85 - z * 0.1 - ((tilewire - TILE_WIRE_L0_I0) % 4 + 1) * 0.01; + el.y2 = el.y1; + g.push_back(el); + break; + case id_LUT_OUT.index: + z = tilewire - TILE_WIRE_L0_O; + el.x1 = loc.x + 0.40; + el.x2 = el.x1 + 0.05; + el.y1 = loc.y + 0.85 - z * 0.1 - 0.025; + el.y2 = el.y1; + g.push_back(el); + break; + case id_FF_DATA.index: + z = tilewire - TILE_WIRE_L0_D; + el.x1 = loc.x + 0.50; + el.x2 = el.x1 + 0.05; + el.y1 = loc.y + 0.85 - z * 0.1 - 0.025; + el.y2 = el.y1; + g.push_back(el); + break; + case id_FF_OUT.index: + z = tilewire - TILE_WIRE_L0_Q; + el.x1 = loc.x + 0.80; + el.x2 = el.x1 + 0.05; + el.y1 = loc.y + 0.85 - z * 0.1 - 0.025; + el.y2 = el.y1; + g.push_back(el); + break; + case id_TILE_CLK.index: for(int i=0;i<8; i++) { GraphicElement el; el.type = GraphicElement::TYPE_LINE; @@ -232,9 +232,63 @@ struct ExampleImpl : HimbaechelAPI g.push_back(el); } break; - case id_BRAM.index: + } + break; + case id_BRAM.index: + switch (wire_type.index) + { + case id_RAM_IN.index: + z = tilewire - TILE_WIRE_RAM_WA0; + el.x1 = loc.x + 0.20; + el.x2 = el.x1 + 0.05; + el.y1 = loc.y + 0.78 - z * 0.015; + el.y2 = el.y1; + g.push_back(el); + break; + case id_RAM_OUT.index: + z = tilewire - TILE_WIRE_RAM_DO0; + el.x1 = loc.x + 0.75; + el.x2 = el.x1 + 0.05; + el.y1 = loc.y + 0.78 - z * 0.015; + el.y2 = el.y1; + g.push_back(el); + break; + case id_TILE_CLK.index: + el.x1 = loc.x + 0.6; + el.x2 = el.x1; + el.y1 = loc.y + 0.20; + el.y2 = el.y1 - 0.05; + g.push_back(el); + break; + } + break; + case id_IO.index: + switch (wire_type.index) + { + case id_IO_I.index: + break; + case id_IO_O.index: + break; + case id_IO_T.index: + break; + case id_IO_PAD.index: + break; + case id_TILE_CLK.index: + break; + case id_GCLK.index: + break; + } + break; + case id_NULL.index: + switch (wire_type.index) + { + case id_CLK_ROUTE.index: + break; + case id_GND.index: + break; + case id_VCC.index: break; - case id_IO.index: + case id_TILE_CLK.index: break; } break; diff --git a/himbaechel/uarch/example/gfx.h b/himbaechel/uarch/example/gfx.h index 3486b290b7..24ca5436fb 100644 --- a/himbaechel/uarch/example/gfx.h +++ b/himbaechel/uarch/example/gfx.h @@ -94,6 +94,63 @@ enum GfxTileWireId TILE_WIRE_L5_Q, TILE_WIRE_L6_Q, TILE_WIRE_L7_Q, + + TILE_WIRE_RAM_WA0, + TILE_WIRE_RAM_WA1, + TILE_WIRE_RAM_WA2, + TILE_WIRE_RAM_WA3, + TILE_WIRE_RAM_WA4, + TILE_WIRE_RAM_WA5, + TILE_WIRE_RAM_WA6, + TILE_WIRE_RAM_WA7, + TILE_WIRE_RAM_WA8, + + TILE_WIRE_RAM_RA0, + TILE_WIRE_RAM_RA1, + TILE_WIRE_RAM_RA2, + TILE_WIRE_RAM_RA3, + TILE_WIRE_RAM_RA4, + TILE_WIRE_RAM_RA5, + TILE_WIRE_RAM_RA6, + TILE_WIRE_RAM_RA7, + TILE_WIRE_RAM_RA8, + + TILE_WIRE_RAM_WE0, + TILE_WIRE_RAM_WE1, + + TILE_WIRE_RAM_DI0, + TILE_WIRE_RAM_DI1, + TILE_WIRE_RAM_DI2, + TILE_WIRE_RAM_DI3, + TILE_WIRE_RAM_DI4, + TILE_WIRE_RAM_DI5, + TILE_WIRE_RAM_DI6, + TILE_WIRE_RAM_DI7, + TILE_WIRE_RAM_DI8, + TILE_WIRE_RAM_DI9, + TILE_WIRE_RAM_DI10, + TILE_WIRE_RAM_DI11, + TILE_WIRE_RAM_DI12, + TILE_WIRE_RAM_DI13, + TILE_WIRE_RAM_DI14, + TILE_WIRE_RAM_DI15, + + TILE_WIRE_RAM_DO0, + TILE_WIRE_RAM_DO1, + TILE_WIRE_RAM_DO2, + TILE_WIRE_RAM_DO3, + TILE_WIRE_RAM_DO4, + TILE_WIRE_RAM_DO5, + TILE_WIRE_RAM_DO6, + TILE_WIRE_RAM_DO7, + TILE_WIRE_RAM_DO8, + TILE_WIRE_RAM_DO9, + TILE_WIRE_RAM_DO10, + TILE_WIRE_RAM_DO11, + TILE_WIRE_RAM_DO12, + TILE_WIRE_RAM_DO13, + TILE_WIRE_RAM_DO14, + TILE_WIRE_RAM_DO15, }; NEXTPNR_NAMESPACE_END