From 05d1693d20de80b703a7ecea156c7969401eefcf Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Thu, 19 Sep 2024 22:00:41 +1000 Subject: [PATCH] stm32/boards: Add definition for STM32H747I-DISCO. Signed-off-by: Andrew Leech --- .../boards/STM32H747I-DISCO/mpconfigboard.h | 92 +++++++++---------- ports/stm32/boards/STM32H747I-DISCO/pins.csv | 53 ++++++----- 2 files changed, 77 insertions(+), 68 deletions(-) diff --git a/ports/stm32/boards/STM32H747I-DISCO/mpconfigboard.h b/ports/stm32/boards/STM32H747I-DISCO/mpconfigboard.h index 69e6203a61c4..73f0a7639bb5 100644 --- a/ports/stm32/boards/STM32H747I-DISCO/mpconfigboard.h +++ b/ports/stm32/boards/STM32H747I-DISCO/mpconfigboard.h @@ -130,12 +130,12 @@ #define MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2 (27) // Reserve 1MiB at the end for compatibility with alternate firmware that places WiFi blob here. #define MICROPY_HW_SPIFLASH_SIZE_BITS (120 * 1024 * 1024) -#define MICROPY_HW_QSPIFLASH_CS (pyb_pin_QSPI2_CS) -#define MICROPY_HW_QSPIFLASH_SCK (pyb_pin_QSPI2_CLK) -#define MICROPY_HW_QSPIFLASH_IO0 (pyb_pin_QSPI2_D0) -#define MICROPY_HW_QSPIFLASH_IO1 (pyb_pin_QSPI2_D1) -#define MICROPY_HW_QSPIFLASH_IO2 (pyb_pin_QSPI2_D2) -#define MICROPY_HW_QSPIFLASH_IO3 (pyb_pin_QSPI2_D3) +#define MICROPY_HW_QSPIFLASH_CS (pyb_pin_QSPI1_CS) +#define MICROPY_HW_QSPIFLASH_SCK (pyb_pin_QSPI1_CLK) +#define MICROPY_HW_QSPIFLASH_IO0 (pyb_pin_QSPI1_D0) +#define MICROPY_HW_QSPIFLASH_IO1 (pyb_pin_QSPI1_D1) +#define MICROPY_HW_QSPIFLASH_IO2 (pyb_pin_QSPI1_D2) +#define MICROPY_HW_QSPIFLASH_IO3 (pyb_pin_QSPI1_D3) // SPI flash #1, block device config extern const struct _mp_spiflash_config_t spiflash_config; @@ -150,14 +150,14 @@ extern struct _spi_bdev_t spi_bdev; #define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_2 // UART config -#define MICROPY_HW_UART1_TX (pin_A9) -#define MICROPY_HW_UART1_RX (pin_A10) +#define MICROPY_HW_UART1_TX (pyb_pin_UART1_TX) +#define MICROPY_HW_UART1_RX (pyb_pin_UART1_RX) #define MICROPY_HW_UART_REPL PYB_UART_1 #define MICROPY_HW_UART_REPL_BAUD 115200 // UART config -#define MICROPY_HW_UART8_TX (pin_J8) -#define MICROPY_HW_UART8_RX (pin_J9) +#define MICROPY_HW_UART8_TX (pyb_pin_UART8_TX) +#define MICROPY_HW_UART8_RX (pyb_pin_UART8_RX) // UART7 config // #define MICROPY_HW_UART7_TX (pyb_pin_BT_TXD) @@ -166,22 +166,22 @@ extern struct _spi_bdev_t spi_bdev; // #define MICROPY_HW_UART7_CTS (pyb_pin_BT_CTS) // I2C buses -#define MICROPY_HW_I2C1_SCL (pin_B6) -#define MICROPY_HW_I2C1_SDA (pin_B7) +// #define MICROPY_HW_I2C1_SCL (pin_B6) +// #define MICROPY_HW_I2C1_SDA (pin_B7) -#define MICROPY_HW_I2C3_SCL (pin_H7) -#define MICROPY_HW_I2C3_SDA (pin_H8) +// #define MICROPY_HW_I2C3_SCL (pin_H7) +// #define MICROPY_HW_I2C3_SDA (pin_H8) // SPI buses -#define MICROPY_HW_SPI1_NSS (pin_C13) -#define MICROPY_HW_SPI1_SCK (pin_B3) -#define MICROPY_HW_SPI1_MISO (pin_B4) -#define MICROPY_HW_SPI1_MOSI (pin_D7) +// #define MICROPY_HW_SPI1_NSS (pin_C13) +// #define MICROPY_HW_SPI1_SCK (pin_B3) +// #define MICROPY_HW_SPI1_MISO (pin_B4) +// #define MICROPY_HW_SPI1_MOSI (pin_D7) -#define MICROPY_HW_SPI2_NSS (pin_I0) -#define MICROPY_HW_SPI2_SCK (pin_I1) -#define MICROPY_HW_SPI2_MISO (pin_C2) -#define MICROPY_HW_SPI2_MOSI (pin_C3) +// #define MICROPY_HW_SPI2_NSS (pin_I0) +// #define MICROPY_HW_SPI2_SCK (pin_I1) +// #define MICROPY_HW_SPI2_MISO (pin_C2) +// #define MICROPY_HW_SPI2_MOSI (pin_C3) // USRSW is pulled low. Pressing the button makes the input go high. #define MICROPY_HW_USRSW_PIN (pin_C13) @@ -197,25 +197,25 @@ extern struct _spi_bdev_t spi_bdev; #define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin)) // SD Card SDMMC -#define MICROPY_HW_SDCARD_SDMMC (2) -#define MICROPY_HW_SDCARD_CK (pin_D6) -#define MICROPY_HW_SDCARD_CMD (pin_D7) -#define MICROPY_HW_SDCARD_D0 (pin_B14) -#define MICROPY_HW_SDCARD_D1 (pin_B15) -#define MICROPY_HW_SDCARD_D2 (pin_B3) -#define MICROPY_HW_SDCARD_D3 (pin_B4) -#define MICROPY_HW_SDCARD_MOUNT_AT_BOOT (0) +// #define MICROPY_HW_SDCARD_SDMMC (2) +// #define MICROPY_HW_SDCARD_CK (pin_D6) +// #define MICROPY_HW_SDCARD_CMD (pin_D7) +// #define MICROPY_HW_SDCARD_D0 (pin_B14) +// #define MICROPY_HW_SDCARD_D1 (pin_B15) +// #define MICROPY_HW_SDCARD_D2 (pin_B3) +// #define MICROPY_HW_SDCARD_D3 (pin_B4) +// #define MICROPY_HW_SDCARD_MOUNT_AT_BOOT (0) // FDCAN bus -#define MICROPY_HW_CAN1_NAME "FDCAN1" -#define MICROPY_HW_CAN1_TX (pin_H13) -#define MICROPY_HW_CAN1_RX (pin_B8) +// #define MICROPY_HW_CAN1_NAME "FDCAN1" +// #define MICROPY_HW_CAN1_TX (pin_H13) +// #define MICROPY_HW_CAN1_RX (pin_B8) // USB config #define MICROPY_HW_USB_HS (1) -#define MICROPY_HW_USB_HS_ULPI_NXT (pin_H4) -#define MICROPY_HW_USB_HS_ULPI_STP (pin_C0) -#define MICROPY_HW_USB_HS_ULPI_DIR (pin_I11) +#define MICROPY_HW_USB_HS_ULPI_NXT (pyb_pin_USB_HS_NXT) +#define MICROPY_HW_USB_HS_ULPI_STP (pyb_pin_USB_HS_STP) +#define MICROPY_HW_USB_HS_ULPI_DIR (pyb_pin_USB_HS_DIR) #define MICROPY_HW_USB_HS_ULPI3320 (1) #define MICROPY_HW_USB_CDC_RX_DATA_SIZE (1024) @@ -227,7 +227,7 @@ extern struct _spi_bdev_t spi_bdev; // SDRAM TODO update to: 8M x 32bit SDRAM is connected to SDRAM Bank1 of the STM32H747XIH6 FMC #define MICROPY_HW_SDRAM_SIZE (256 * 1024 * 1024 / 8) // 256 Mbit #define MICROPY_HW_SDRAM_STARTUP_TEST (1) -#define MICROPY_HW_SDRAM_TEST_FAIL_ON_ERROR (true) +#define MICROPY_HW_SDRAM_TEST_FAIL_ON_ERROR (false) // #define MICROPY_HW_FMC_SWAP_BANKS (1) // Timing configuration for 200MHz/2=100MHz (10ns) @@ -326,15 +326,15 @@ extern struct _spi_bdev_t spi_bdev; #define MICROPY_HW_FMC_D31 (pin_I10) // Ethernet via RMII -#define MICROPY_HW_ETH_MDC (pin_C1) -#define MICROPY_HW_ETH_MDIO (pin_A2) -#define MICROPY_HW_ETH_RMII_REF_CLK (pin_A1) -#define MICROPY_HW_ETH_RMII_CRS_DV (pin_A7) -#define MICROPY_HW_ETH_RMII_RXD0 (pin_C4) -#define MICROPY_HW_ETH_RMII_RXD1 (pin_C5) -#define MICROPY_HW_ETH_RMII_TX_EN (pin_G11) -#define MICROPY_HW_ETH_RMII_TXD0 (pin_G13) -#define MICROPY_HW_ETH_RMII_TXD1 (pin_G12) +#define MICROPY_HW_ETH_MDC (pyb_pin_ETH_MDC) +#define MICROPY_HW_ETH_MDIO (pyb_pin_ETH_MDIO) +#define MICROPY_HW_ETH_RMII_REF_CLK (pyb_pin_ETH_RMII_REF_CLK) +#define MICROPY_HW_ETH_RMII_CRS_DV (pyb_pin_ETH_RMII_CRS_DV) +#define MICROPY_HW_ETH_RMII_RXD0 (pyb_pin_ETH_RMII_RXD0) +#define MICROPY_HW_ETH_RMII_RXD1 (pyb_pin_ETH_RMII_RXD1) +#define MICROPY_HW_ETH_RMII_TX_EN (pyb_pin_ETH_RMII_TX_EN) +#define MICROPY_HW_ETH_RMII_TXD0 (pyb_pin_ETH_RMII_TXD0) +#define MICROPY_HW_ETH_RMII_TXD1 (pyb_pin_ETH_RMII_TXD1) // #define MICROPY_HW_USB_VID 0x2341 // #define MICROPY_HW_USB_PID 0x055B diff --git a/ports/stm32/boards/STM32H747I-DISCO/pins.csv b/ports/stm32/boards/STM32H747I-DISCO/pins.csv index 4ce108571211..580c0883667a 100644 --- a/ports/stm32/boards/STM32H747I-DISCO/pins.csv +++ b/ports/stm32/boards/STM32H747I-DISCO/pins.csv @@ -198,13 +198,15 @@ A7,PA6 UART1_TX,PA9 UART1_RX,PA10 -UART4_TX,PA0 -UART4_RX,PI9 -UART6_TX,PG14 -UART6_RX,PG9 + +#UART4_TX,PA0 +#UART4_RX,PI9 +#UART6_TX,PG14 +#UART6_RX,PG9 + UART8_TX,PJ8 UART8_RX,PJ9 --ETH_RST,PJ15 + -ETH_RMII_REF_CLK,PA1 -ETH_MDIO,-PA2 -ETH_RMII_CRS_DV,-PA7 @@ -214,6 +216,7 @@ UART8_RX,PJ9 -ETH_RMII_TX_EN,PG11 -ETH_RMII_TXD0,PG13 -ETH_RMII_TXD1,PG12 + -USB_HS_CLK,-PA5 -USB_HS_STP,-PC0 -USB_HS_NXT,-PH4 @@ -226,24 +229,30 @@ UART8_RX,PJ9 -USB_HS_D5,PB12 -USB_HS_D6,PB13 -USB_HS_D7,PB5 --USB_HS_RST,PJ4 --USB_DM,PA11 --USB_DP,PA12 + + #BOOT0,BOOT0 -OSCEN,PH1 -DAC1,PA4 -DAC2,-PA5 -I2C1_SDA,PB7 -I2C1_SCL,PB6 -I2C3_SDA,PH8 -I2C3_SCL,PH7 --QSPI2_CS,PG6 --QSPI2_CLK,-PF10 --QSPI2_D0,PD11 --QSPI2_D1,PD12 --QSPI2_D2,-PF7 --QSPI2_D3,PD13 --SE05X_EN,-PI12 + +# DAC1,PA4 +# DAC2,-PA5 +# I2C1_SDA,PB7 +# I2C1_SCL,PB6 +# I2C3_SDA,PH8 +# I2C3_SCL,PH7 + +-QSPI1_CS,PG6 +-QSPI1_CLK,PB2 +-QSPI1_D0,PD11 +-QSPI1_D1,PF9 +-QSPI1_D2,PF7 +-QSPI1_D3,PF6 + +-QSPI2_D0,PH2 +-QSPI2_D1,PH3 +-QSPI2_D2,PG9 +-QSPI2_D3,PG14 + + LEDR,PI12 LEDG,PI13