From 9b339e5c5aa08ae7083524849118266bec45ce15 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Fri, 13 Dec 2024 21:41:44 +1100 Subject: [PATCH] renesas-ra/boards/WEACT_RA4M1_CORE: Add board profile. Signed-off-by: Andrew Leech --- .../boards/WEACT_RA4M1_CORE/.gitignore | 11 + .../boards/WEACT_RA4M1_CORE/board.json | 15 + .../boards/WEACT_RA4M1_CORE/configuration.xml | 588 ++++++++++++++++++ .../boards/WEACT_RA4M1_CORE/manifest.py | 1 + .../boards/WEACT_RA4M1_CORE/mpconfigboard.h | 72 +++ .../boards/WEACT_RA4M1_CORE/mpconfigboard.mk | 18 + .../boards/WEACT_RA4M1_CORE/pins.csv | 62 ++ .../boards/WEACT_RA4M1_CORE/ra4m1_ek.ld | 302 +++++++++ .../boards/WEACT_RA4M1_CORE/ra4m1_ek_conf.h | 30 + .../ra_cfg/fsp_cfg/bsp/board_cfg.h | 13 + .../ra_cfg/fsp_cfg/bsp/bsp_cfg.h | 62 ++ .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h | 5 + .../fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 11 + .../ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 83 +++ .../ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h | 16 + .../ra_cfg/fsp_cfg/r_adc_cfg.h | 13 + .../ra_cfg/fsp_cfg/r_cgc_cfg.h | 14 + .../ra_cfg/fsp_cfg/r_dtc_cfg.h | 14 + .../ra_cfg/fsp_cfg/r_flash_lp_cfg.h | 15 + .../ra_cfg/fsp_cfg/r_gpt_cfg.h | 16 + .../ra_cfg/fsp_cfg/r_icu_cfg.h | 13 + .../ra_cfg/fsp_cfg/r_ioport_cfg.h | 13 + .../ra_cfg/fsp_cfg/r_lpm_cfg.h | 14 + .../ra_cfg/fsp_cfg/r_rtc_cfg.h | 14 + .../ra_cfg/fsp_cfg/r_sci_uart_cfg.h | 17 + .../ra_cfg/fsp_cfg/r_spi_cfg.h | 18 + .../WEACT_RA4M1_CORE/ra_gen/bsp_clock_cfg.h | 21 + .../WEACT_RA4M1_CORE/ra_gen/common_data.c | 50 ++ .../WEACT_RA4M1_CORE/ra_gen/common_data.h | 40 ++ .../boards/WEACT_RA4M1_CORE/ra_gen/hal_data.c | 560 +++++++++++++++++ .../boards/WEACT_RA4M1_CORE/ra_gen/hal_data.h | 125 ++++ .../boards/WEACT_RA4M1_CORE/ra_gen/main.c | 6 + .../boards/WEACT_RA4M1_CORE/ra_gen/pin_data.c | 115 ++++ .../WEACT_RA4M1_CORE/ra_gen/vector_data.c | 43 ++ .../WEACT_RA4M1_CORE/ra_gen/vector_data.h | 64 ++ 35 files changed, 2474 insertions(+) create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/.gitignore create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/board.json create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/configuration.xml create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/manifest.py create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/mpconfigboard.h create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/mpconfigboard.mk create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/pins.csv create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra4m1_ek.ld create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra4m1_ek_conf.h create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/bsp/board_cfg.h create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/bsp/bsp_cfg.h create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_adc_cfg.h create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_cgc_cfg.h create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_dtc_cfg.h create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_flash_lp_cfg.h create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_gpt_cfg.h create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_icu_cfg.h create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_ioport_cfg.h create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_lpm_cfg.h create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_rtc_cfg.h create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_sci_uart_cfg.h create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_spi_cfg.h create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/bsp_clock_cfg.h create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/common_data.c create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/common_data.h create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/hal_data.c create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/hal_data.h create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/main.c create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/pin_data.c create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/vector_data.c create mode 100644 ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/vector_data.h diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/.gitignore b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/.gitignore new file mode 100644 index 000000000000..c7336988b974 --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/.gitignore @@ -0,0 +1,11 @@ +/.settings/ +/cmake/ +/ra/ +/script/ +/src/ +/.api_xml +/.secure_azone +/.secure_xml +/buildinfo.json +/memory_regions.ld +/ra_cfg.txt diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/board.json b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/board.json new file mode 100644 index 000000000000..48794404269e --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/board.json @@ -0,0 +1,15 @@ +{ + "deploy": [ + "../deploy.md" + ], + "docs": "", + "features": [], + "images": [ + "ek_ra4m1_board.jpg" + ], + "mcu": "ra4m1", + "product": "WEACT_RA4M1_CORE", + "thumbnail": "", + "url": "https://github.com/WeActStudio/WeActStudio.RA4M1_64Pin_CoreBoard", + "vendor": "WeAct Studio" +} diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/configuration.xml b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/configuration.xml new file mode 100644 index 000000000000..79a86579b5af --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/configuration.xml @@ -0,0 +1,588 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Arm CMSIS Version 5 - Core (M) + Arm.CMSIS5.5.9.0+renesas.0.fsp.4.4.0.pack + + + Board Support Package Common Files + Renesas.RA.4.4.0.pack + + + A/D Converter + Renesas.RA.4.4.0.pack + + + Data Transfer Controller + Renesas.RA.4.4.0.pack + + + Flash Memory Low Power + Renesas.RA.4.4.0.pack + + + I/O Port + Renesas.RA.4.4.0.pack + + + Real Time Clock + Renesas.RA.4.4.0.pack + + + SCI UART + Renesas.RA.4.4.0.pack + + + Serial Peripheral Interface + Renesas.RA.4.4.0.pack + + + Board support package for R7FA4M1AB3CFP + Renesas.RA_mcu_ra4m1.4.4.0.pack + + + Board support package for RA4M1 + Renesas.RA_mcu_ra4m1.4.4.0.pack + + + Board support package for RA4M1 - FSP Data + Renesas.RA_mcu_ra4m1.4.4.0.pack + + + Custom Board Support Files + Renesas.RA_board_custom.4.4.0.pack + + + Clock Generation Circuit + Renesas.RA.4.4.0.pack + + + General PWM Timer + Renesas.RA.4.4.0.pack + + + External Interrupt + Renesas.RA.4.4.0.pack + + + Low Power Modes + Renesas.RA.4.4.0.pack + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/manifest.py b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/manifest.py new file mode 100644 index 000000000000..ee2b4620dd46 --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/manifest.py @@ -0,0 +1 @@ +include("$(MPY_DIR)/extmod/asyncio") diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/mpconfigboard.h b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/mpconfigboard.h new file mode 100644 index 000000000000..776719d84baa --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/mpconfigboard.h @@ -0,0 +1,72 @@ +// MCU config +#define MICROPY_HW_BOARD_NAME "WEACT_RA4M1_CORE" +#define MICROPY_HW_MCU_NAME "RA4M1" +#define MICROPY_HW_MCU_SYSCLK 48000000 +#define MICROPY_HW_MCU_PCLK 48000000 + +// module config +// #define MICROPY_CONFIG_ROM_LEVEL (MICROPY_CONFIG_ROM_LEVEL_BASIC_FEATURES) +// #define MICROPY_ENABLE_FINALISER (1) + +#define MICROPY_EMIT_THUMB (0) +#define MICROPY_EMIT_INLINE_THUMB (0) +#define MICROPY_PY_BUILTINS_COMPLEX (0) +#define MICROPY_PY_GENERATOR_PEND_THROW (0) +#define MICROPY_PY_MATH (0) +#define MICROPY_PY_HEAPQ (0) +#define MICROPY_PY_THREAD (0) // disable ARM_THUMB_FP using vldr due to RA has single float only + +// peripheral config +#define MICROPY_HW_ENABLE_RTC (1) +#define MICROPY_HW_RTC_SOURCE (1) // 0: subclock, 1:LOCO (32.768khz) +#define MICROPY_HW_ENABLE_ADC (1) +#define MICROPY_HW_HAS_FLASH (1) +#define MICROPY_HW_ENABLE_USBDEV (1) +#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (1) + +// board config + +// UART +// #define MICROPY_HW_UART0_TX (pin_P411) +// #define MICROPY_HW_UART0_RX (pin_P410) +// #define MICROPY_HW_UART1_TX (pin_P401) // PMOD B +// #define MICROPY_HW_UART1_RX (pin_P402) // PMOD B +// #define MICROPY_HW_UART1_CTS (pin_P403) // PMOD B +// #define MICROPY_HW_UART2_TX (pin_P302) +// #define MICROPY_HW_UART2_RX (pin_P301) +// #define MICROPY_HW_UART2_CTS (pin_P203) // (Conflict with SPI1) +#define MICROPY_HW_UART9_TX (pyb_pin_MBTX9) // REPL +#define MICROPY_HW_UART9_RX (pyb_pin_MBRX9) // REPL +#define MICROPY_HW_UART_REPL HW_UART_9 +#define MICROPY_HW_UART_REPL_BAUD 115200 + +// I2C (not supported) +// #define MICROPY_HW_I2C0_SCL (pin_P204) // Conflict with SPI1 +// #define MICROPY_HW_I2C0_SDA (pin_P407) // Conflict with USB_VBUS +// #define MICROPY_HW_I2C0_SCL (pin_P400) // Conflict with PMOD B (GPIO) +// #define MICROPY_HW_I2C0_SDA (pin_P401) // Conflict with PMOD B (TXD1) +// #define MICROPY_HW_I2C1_SCL (pin_P100) // Conflict with PMOD A (MISOA_A) +// #define MICROPY_HW_I2C1_SDA (pin_P101) // Conflict with PMOD A (MOSIA_A) + +// SPI +// #define MICROPY_HW_SPI0_SSL (pin_P103) // PMOD A +// #define MICROPY_HW_SPI0_RSPCK (pin_P102) // PMOD A +// #define MICROPY_HW_SPI0_MISO (pin_P100) // PMOD A +// #define MICROPY_HW_SPI0_MOSI (pin_P101) // PMOD A +// #define MICROPY_HW_SPI1_SSL (pin_P206) // Use SSLB1 due to SSLB0 is used for TSCAP +// #define MICROPY_HW_SPI1_RSPCK (pin_P204) // Disable (vector not registered) +// #define MICROPY_HW_SPI1_MISO (pin_P202) // Disable (vector not registered) +// #define MICROPY_HW_SPI1_MOSI (pin_P203) // Disable (vector not registered) + +// Switch +#define MICROPY_HW_HAS_SWITCH (1) +#define MICROPY_HW_USRSW_PIN (pyb_pin_USERSW) +#define MICROPY_HW_USRSW_PULL (MP_HAL_PIN_PULL_UP) +#define MICROPY_HW_USRSW_EXTI_MODE (MP_HAL_PIN_TRIGGER_FALLING) +#define MICROPY_HW_USRSW_PRESSED (0) + +// LEDs +#define MICROPY_HW_LED1 (pyb_pin_LED1) +#define MICROPY_HW_LED_ON(pin) mp_hal_pin_high(pin) +#define MICROPY_HW_LED_OFF(pin) mp_hal_pin_low(pin) +#define MICROPY_HW_LED_TOGGLE(pin) mp_hal_pin_toggle(pin) diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/mpconfigboard.mk b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/mpconfigboard.mk new file mode 100644 index 000000000000..feb736dfa77a --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/mpconfigboard.mk @@ -0,0 +1,18 @@ +CMSIS_MCU = RA4M1 +MCU_SERIES = m4 +LD_FILES = boards/WEACT_RA4M1_CORE/ra4m1_ek.ld + +# MicroPython settings +MICROPY_VFS_LFS2 = 1 +MICROPY_VFS_FAT = 0 +USE_FSP_LPM = 0 + +CFLAGS+=-DDEFAULT_DBG_CH=0 \ + -DCFG_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED \ + -DCFG_TUSB_RHPORT0_MODE=OPT_MODE_DEVICE \ + -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED \ + -DCFG_TUSB_MCU=OPT_MCU_RAXXX \ + -DBOARD_TUD_RHPORT=0 + +# Don't include default frozen modules because MCU is tight on flash space +FROZEN_MANIFEST ?= boards/WEACT_RA4M1_CORE/manifest.py diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/pins.csv b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/pins.csv new file mode 100644 index 000000000000..7793efb9e079 --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/pins.csv @@ -0,0 +1,62 @@ +P000,P000 +P001,P001 +P002,P002 +P003,P003 +P004,P004 +VREF,P010 +P011,P011 +P012,P012 +P013,P013 +P014,P014 +P015,P015 +P100,P100 +P101,P101 +P102,P102 +P103,P103 +P104,P104 +P105,P105 +P106,P106 +P107,P107 +P109,P109 +P110,P110 +P111,P111 +P112,P112 +P113,P113 +P200,P200 +MD,P201 +P204,P204 +P205,P205 +P206,P206 +P301,P301 +P302,P302 +P303,P303 +P304,P304 +P400,P400 +P401,P401 +P402,P402 +P408,P408 +P409,P409 +P410,P410 +P411,P411 +P500,P500 +P501,P501 +P502,P502 +SWCLK,P300 +SWDIO,P108 +SWO,P109 +TDI,P110 +TSCAP,P112 +MD,P201 +USERSW,P013 +BOOTSW,P201 +MDSW,P201 +LED1,P012 +MBRX9,P110 +MBTX9,P109 +USBDP,P914 +USBDM,P915 +USB_VBUS,P407 +VREFL,P013 +VREFH,P012 +VREFH0,P010 +VREFL0,P011 diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra4m1_ek.ld b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra4m1_ek.ld new file mode 100644 index 000000000000..c9853ecd2fa7 --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra4m1_ek.ld @@ -0,0 +1,302 @@ +/* + Linker File for RA4M1 MCU +*/ + +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00039000 /* 226KB/256KB */ + FLASH_FS (r) : ORIGIN = 0x00039000, LENGTH = 0x00007000 /* 36KB/256KB */ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* 32KB */ + DATA_FLASH (rx) : ORIGIN = 0x40100000, LENGTH = 0x00002000 /* 8KB */ + ID_CODE (rx) : ORIGIN = 0x01010018, LENGTH = 0x00000020 /* 32bytes */ +} + +/* Library configurations */ +/*GROUP(libgcc.a libc.a libm.a libnosys.a) */ + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + _stext = .; + __ROM_Start = .; + + /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much + * space because ROM registers are at address 0x400 and there is very little space + * in between. */ + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + __end__ = .; + + /* ROM Registers start at address 0x00000400 */ + . = __ROM_Start + 0x400; + KEEP(*(.rom_registers*)) + + /* Reserving 0x100 bytes of space for ROM registers. */ + . = __ROM_Start + 0x500; + + *(.text*) + + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + __usb_dev_descriptor_start_fs = .; + KEEP(*(.usb_device_desc_fs*)) + __usb_cfg_descriptor_start_fs = .; + KEEP(*(.usb_config_desc_fs*)) + __usb_interface_descriptor_start_fs = .; + KEEP(*(.usb_interface_desc_fs*)) + __usb_descriptor_end_fs = .; + __usb_dev_descriptor_start_hs = .; + KEEP(*(.usb_device_desc_hs*)) + __usb_cfg_descriptor_start_hs = .; + KEEP(*(.usb_config_desc_hs*)) + __usb_interface_descriptor_start_hs = .; + KEEP(*(.usb_interface_desc_hs*)) + __usb_descriptor_end_hs = .; + + KEEP(*(.eh_frame*)) + + __ROM_End = .; + _etext = .; + } > FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + _sidata = .; + _sdata = .; + __data_start__ = .; + *(vtable) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM AT > FLASH + + + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + __noinit_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* Stacks are stored in this section. */ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + __StackLimit = .; + /* Main stack */ + KEEP(*(.stack)) + __StackTop = .; + /* Thread stacks */ + KEEP(*(.stack*)) + __StackTopAll = .; + _estack = .; + } > RAM + + PROVIDE(__stack = __StackTopAll); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* Data flash. */ + .data_flash : + { + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + } > DATA_FLASH + + .id_code (NOLOAD): + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE +} +/* produce a link error if there is not this amount of RAM for these sections */ +/* _minimum_stack_size = 2K; */ +/* _minimum_heap_size = 16K; */ + +/* Define tho top end of the stack. The stack is full descending so begins just + above last byte of RAM. Note that EABI requires the stack to be 8-byte + aligned for a call. */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_start = ORIGIN(RAM); +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_start = __HeapBase; /* heap starts just after statically allocated memory */ +_heap_end = __HeapLimit; /* tunable */ + +_micropy_hw_internal_flash_storage_start = ORIGIN(FLASH_FS); +_micropy_hw_internal_flash_storage_end = ORIGIN(FLASH_FS) + LENGTH(FLASH_FS); diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra4m1_ek_conf.h b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra4m1_ek_conf.h new file mode 100644 index 000000000000..261073cfe98e --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra4m1_ek_conf.h @@ -0,0 +1,30 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RA4M1_EK_CONF_H +#define RA4M1_EK_CONF_H + +#define DEBUG_CH 0 + +#endif /* RA4M1_EK_CONF_H */ diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/bsp/board_cfg.h b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/bsp/board_cfg.h new file mode 100644 index 000000000000..825f8cd3290e --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/bsp/board_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef BOARD_CFG_H_ +#define BOARD_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + void bsp_init(void * p_args); + + #ifdef __cplusplus + } + #endif +#endif /* BOARD_CFG_H_ */ diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000000..8091669deac0 --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,62 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #include "bsp_clock_cfg.h" + #include "bsp_mcu_family_cfg.h" + #include "board_cfg.h" + #define RA_NOT_DEFINED 0 + #ifndef BSP_CFG_RTOS + #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else + #define BSP_CFG_RTOS (0) + #endif + #endif + #ifndef BSP_CFG_RTC_USED + #define BSP_CFG_RTC_USED (1) + #endif + #undef RA_NOT_DEFINED + #if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) + #endif + #define BSP_CFG_MCU_VCC_MV (3300) + #define BSP_CFG_STACK_MAIN_BYTES (0x900) + #define BSP_CFG_HEAP_BYTES (0x4880) + #define BSP_CFG_PARAM_CHECKING_ENABLE (0) + #define BSP_CFG_ASSERT (0) + #define BSP_CFG_ERROR_LOG (0) + + #define BSP_CFG_PFS_PROTECT ((1)) + + #define BSP_CFG_C_RUNTIME_INIT ((1)) + #define BSP_CFG_EARLY_INIT ((0)) + + #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) + #endif + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE + #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS + #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + #endif + + #ifdef __cplusplus + } + #endif +#endif /* BSP_CFG_H_ */ diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 000000000000..444d32e5606c --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (4) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000000..243fad9b63b5 --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA4M1AB3CFP + #define BSP_MCU_FEATURE_SET ('A') + #define BSP_ROM_SIZE_BYTES (262144) + #define BSP_RAM_SIZE_BYTES (32768) + #define BSP_DATA_FLASH_SIZE_BYTES (8192) + #define BSP_PACKAGE_LQFP + #define BSP_PACKAGE_PINS (100) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 000000000000..d3422e563a00 --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,83 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #include "bsp_mcu_device_pn_cfg.h" + #include "bsp_mcu_device_cfg.h" + #include "../../../ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h" + #include "bsp_clock_cfg.h" + #define BSP_MCU_GROUP_RA4M1 (1) + #define BSP_LOCO_HZ (32768) + #define BSP_MOCO_HZ (8000000) + #define BSP_SUB_CLOCK_HZ (32768) + #if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (24000000) + #elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (32000000) + #elif BSP_CFG_HOCO_FREQUENCY == 4 + #define BSP_HOCO_HZ (48000000) + #elif BSP_CFG_HOCO_FREQUENCY == 5 + #define BSP_HOCO_HZ (64000000) + #else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" + #endif + #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) + #define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) + + #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) + #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) + #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) + #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) + #define OFS_SEQ5 (1 << 28) | (1 << 30) + #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) + #define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) + #define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC) + #define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF) + #define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC) + #define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) + #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT + #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (7) + #endif + /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ + #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + + /* + ID Code + Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. + WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. + */ + #if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) + #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) + #else + /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ + #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) + #endif + + #ifdef __cplusplus + } + #endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h new file mode 100644 index 000000000000..5447a2dafc36 --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h @@ -0,0 +1,16 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_ioport.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +extern const ioport_cfg_t g_bsp_pin_cfg; /* RA4M1-EK.pincfg */ + +void BSP_PinConfigSecurityInit(); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* BSP_PIN_CFG_H_ */ diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_adc_cfg.h b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_adc_cfg.h new file mode 100644 index 000000000000..be8a4272068a --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_adc_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_ADC_CFG_H_ +#define R_ADC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define ADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_ADC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_cgc_cfg.h b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_cgc_cfg.h new file mode 100644 index 000000000000..0501e2be4201 --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_cgc_cfg.h @@ -0,0 +1,14 @@ +/* generated configuration header file - do not edit */ +#ifndef R_CGC_CFG_H_ +#define R_CGC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define CGC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define CGC_CFG_USE_LOW_VOLTAGE_MODE RA_NOT_DEFINED + +#ifdef __cplusplus +} +#endif +#endif /* R_CGC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_dtc_cfg.h b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_dtc_cfg.h new file mode 100644 index 000000000000..fea5e9c9a040 --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_dtc_cfg.h @@ -0,0 +1,14 @@ +/* generated configuration header file - do not edit */ +#ifndef R_DTC_CFG_H_ +#define R_DTC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define DTC_CFG_VECTOR_TABLE_SECTION_NAME ".fsp_dtc_vector_table" + +#ifdef __cplusplus +} +#endif +#endif /* R_DTC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_flash_lp_cfg.h b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_flash_lp_cfg.h new file mode 100644 index 000000000000..6a9b00c639cf --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_flash_lp_cfg.h @@ -0,0 +1,15 @@ +/* generated configuration header file - do not edit */ +#ifndef R_FLASH_LP_CFG_H_ +#define R_FLASH_LP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define FLASH_LP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (1) + #define FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_FLASH_LP_CFG_H_ */ diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_gpt_cfg.h b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_gpt_cfg.h new file mode 100644 index 000000000000..68e2ae123996 --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_gpt_cfg.h @@ -0,0 +1,16 @@ +/* generated configuration header file - do not edit */ +#ifndef R_GPT_CFG_H_ +#define R_GPT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define GPT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define GPT_CFG_OUTPUT_SUPPORT_ENABLE (0) +#define GPT_CFG_WRITE_PROTECT_ENABLE (0) +#define GPT_CFG_GPTCLK_BYPASS 1 + +#ifdef __cplusplus +} +#endif +#endif /* R_GPT_CFG_H_ */ diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_icu_cfg.h b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_icu_cfg.h new file mode 100644 index 000000000000..85fb06ed55fe --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_icu_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_ICU_CFG_H_ +#define R_ICU_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_ICU_CFG_H_ */ diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_ioport_cfg.h b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 000000000000..d2688bf5ba39 --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_IOPORT_CFG_H_ */ diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_lpm_cfg.h b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_lpm_cfg.h new file mode 100644 index 000000000000..1b306b5551fc --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_lpm_cfg.h @@ -0,0 +1,14 @@ +/* generated configuration header file - do not edit */ +#ifndef R_LPM_CFG_H_ +#define R_LPM_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define LPM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define LPM_CFG_STANDBY_LIMIT (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_LPM_CFG_H_ */ diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_rtc_cfg.h b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_rtc_cfg.h new file mode 100644 index 000000000000..7e95d5eacd91 --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_rtc_cfg.h @@ -0,0 +1,14 @@ +/* generated configuration header file - do not edit */ +#ifndef R_RTC_CFG_H_ +#define R_RTC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define RTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define RTC_CFG_OPEN_SET_CLOCK_SOURCE (1) + +#ifdef __cplusplus +} +#endif +#endif /* R_RTC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_sci_uart_cfg.h b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_sci_uart_cfg.h new file mode 100644 index 000000000000..073c426579d4 --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_sci_uart_cfg.h @@ -0,0 +1,17 @@ +/* generated configuration header file - do not edit */ +#ifndef R_SCI_UART_CFG_H_ +#define R_SCI_UART_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define SCI_UART_CFG_FIFO_SUPPORT (0) + #define SCI_UART_CFG_DTC_SUPPORTED (0) + #define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0) + #define SCI_UART_CFG_RS485_SUPPORT (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_SCI_UART_CFG_H_ */ diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_spi_cfg.h b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_spi_cfg.h new file mode 100644 index 000000000000..27115e99fd86 --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_cfg/fsp_cfg/r_spi_cfg.h @@ -0,0 +1,18 @@ +/* generated configuration header file - do not edit */ +#ifndef R_SPI_CFG_H_ +#define R_SPI_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define SPI_DMA_SUPPORT_ENABLE (1) + #define SPI_TRANSMIT_FROM_RXI_ISR (0) + + /* DEPRECATED: Use SPI_DMA_SUPPORT_ENABLE instead. */ + #define SPI_DTC_SUPPORT_ENABLE (SPI_DMA_SUPPORT_ENABLE) + + #ifdef __cplusplus + } + #endif +#endif /* R_SPI_CFG_H_ */ diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/bsp_clock_cfg.h b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/bsp_clock_cfg.h new file mode 100644 index 000000000000..eb4e1a05e50e --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/bsp_clock_cfg.h @@ -0,0 +1,21 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (16000000) /* XTAL 16000000Hz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_HOCO_FREQUENCY (4) /* HOCO 48MHz */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(8U,0U) /* PLL Mul x8 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* Clock Src: HOCO */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* UCLK Src: HOCO */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/common_data.c b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/common_data.c new file mode 100644 index 000000000000..a248e545609b --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/common_data.c @@ -0,0 +1,50 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +icu_instance_ctrl_t g_external_irq0_ctrl; +const external_irq_cfg_t g_external_irq0_cfg = +{ + .channel = 0, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = &NULL, +#endif + .p_extend = NULL, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ0) + .irq = VECTOR_NUMBER_ICU_IRQ0, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq0 = +{ + .p_ctrl = &g_external_irq0_ctrl, + .p_cfg = &g_external_irq0_cfg, + .p_api = &g_external_irq_on_icu +}; +const cgc_cfg_t g_cgc0_cfg = +{ + .p_callback = NULL, +}; +cgc_instance_ctrl_t g_cgc0_ctrl; +const cgc_instance_t g_cgc0 = { + .p_api = &g_cgc_on_cgc, + .p_ctrl = &g_cgc0_ctrl, + .p_cfg = &g_cgc0_cfg, +}; +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = + { + .p_api = &g_ioport_on_ioport, + .p_ctrl = &g_ioport_ctrl, + .p_cfg = &g_bsp_pin_cfg, + }; +void g_common_init(void) { +} diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/common_data.h b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/common_data.h new file mode 100644 index 000000000000..459ce5a8fe74 --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/common_data.h @@ -0,0 +1,40 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include +#include "bsp_api.h" +#include "r_icu.h" +#include "r_external_irq_api.h" +#include "r_cgc.h" +#include "r_cgc_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq0; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq0_ctrl; +extern const external_irq_cfg_t g_external_irq0_cfg; + +#ifndef NULL +void NULL(external_irq_callback_args_t * p_args); +#endif +/** CGC Instance */ +extern const cgc_instance_t g_cgc0; + +/** Access the CGC instance using these structures when calling API functions directly (::p_api is not used). */ +extern cgc_instance_ctrl_t g_cgc0_ctrl; +extern const cgc_cfg_t g_cgc0_cfg; + +#ifndef NULL +void NULL(cgc_callback_args_t * p_args); +#endif +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/hal_data.c b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/hal_data.c new file mode 100644 index 000000000000..f3b2ab64cca7 --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/hal_data.c @@ -0,0 +1,560 @@ +/* generated HAL source file - do not edit */ +#include "hal_data.h" + +/* Macros to tie dynamic ELC links to ADC_TRIGGER_SYNC_ELC option in adc_trigger_t. */ +#define ADC_TRIGGER_ADC0 ADC_TRIGGER_SYNC_ELC +#define ADC_TRIGGER_ADC0_B ADC_TRIGGER_SYNC_ELC +#define ADC_TRIGGER_ADC1 ADC_TRIGGER_SYNC_ELC +#define ADC_TRIGGER_ADC1_B ADC_TRIGGER_SYNC_ELC +lpm_instance_ctrl_t g_lpm0_ctrl; + +const lpm_cfg_t g_lpm0_cfg = +{ + .low_power_mode = LPM_MODE_SLEEP, + .standby_wake_sources = (lpm_standby_wake_source_t) 0, +#if BSP_FEATURE_LPM_HAS_SNOOZE + .snooze_cancel_sources = LPM_SNOOZE_CANCEL_SOURCE_NONE, + .snooze_request_source = LPM_SNOOZE_REQUEST_RXD0_FALLING, + .snooze_end_sources = (lpm_snooze_end_t) 0, + .dtc_state_in_snooze = LPM_SNOOZE_DTC_DISABLE, +#endif +#if BSP_FEATURE_LPM_HAS_SBYCR_OPE + .output_port_enable = 0, +#endif +#if BSP_FEATURE_LPM_HAS_DEEP_STANDBY + .io_port_state = 0, + .power_supply_state = 0, + .deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t) 0, + .deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t) 0, +#endif +#if BSP_FEATURE_LPM_HAS_PDRAMSCR + .ram_retention_cfg.ram_retention = (uint8_t) ( 0), + .ram_retention_cfg.tcm_retention = false, +#endif +#if BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP + .ram_retention_cfg.standby_ram_retention = false, +#endif +#if BSP_FEATURE_LPM_HAS_LDO_CONTROL + .ldo_standby_cfg.pll1_ldo = false, + .ldo_standby_cfg.pll2_ldo = false, + .ldo_standby_cfg.hoco_ldo = false, +#endif + .p_extend = NULL, +}; + +const lpm_instance_t g_lpm0 = +{ + .p_api = &g_lpm_on_lpm, + .p_ctrl = &g_lpm0_ctrl, + .p_cfg = &g_lpm0_cfg +}; +gpt_instance_ctrl_t g_timer0_ctrl; +#if 0 +const gpt_extended_pwm_cfg_t g_timer0_pwm_extend = +{ + .trough_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT0_COUNTER_UNDERFLOW) + .trough_irq = VECTOR_NUMBER_GPT0_COUNTER_UNDERFLOW, +#else + .trough_irq = FSP_INVALID_VECTOR, +#endif + .poeg_link = GPT_POEG_LINK_POEG0, + .output_disable = (gpt_output_disable_t) ( GPT_OUTPUT_DISABLE_NONE), + .adc_trigger = (gpt_adc_trigger_t) ( GPT_ADC_TRIGGER_NONE), + .dead_time_count_up = 0, + .dead_time_count_down = 0, + .adc_a_compare_match = 0, + .adc_b_compare_match = 0, + .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE, + .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0, + .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE, + .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, + .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, +}; +#endif +const gpt_extended_cfg_t g_timer0_extend = +{ + .gtioca = { .output_enabled = false, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .gtiocb = { .output_enabled = false, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .start_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .stop_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .clear_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_ipl = (BSP_IRQ_DISABLED), + .capture_b_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT0_CAPTURE_COMPARE_A) + .capture_a_irq = VECTOR_NUMBER_GPT0_CAPTURE_COMPARE_A, +#else + .capture_a_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT0_CAPTURE_COMPARE_B) + .capture_b_irq = VECTOR_NUMBER_GPT0_CAPTURE_COMPARE_B, +#else + .capture_b_irq = FSP_INVALID_VECTOR, +#endif + .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, + .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, +#if 0 + .p_pwm_cfg = &g_timer0_pwm_extend, +#else + .p_pwm_cfg = NULL, +#endif +#if 0 + .gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.oahld = 0U, + .gtior_setting.gtior_b.oae = (uint32_t) false, + .gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), + .gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.obhld = 0U, + .gtior_setting.gtior_b.obe = (uint32_t) false, + .gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), +#else + .gtior_setting.gtior = 0U, +#endif +}; +const timer_cfg_t g_timer0_cfg = +{ + .mode = TIMER_MODE_PERIODIC, + /* Actual period: 89.47848533333334 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x100000000, .duty_cycle_counts = 0x80000000, .source_div = (timer_source_div_t)0, + .channel = 0, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = &NULL, +#endif + .p_extend = &g_timer0_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT0_COUNTER_OVERFLOW) + .cycle_end_irq = VECTOR_NUMBER_GPT0_COUNTER_OVERFLOW, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer0 = +{ + .p_ctrl = &g_timer0_ctrl, + .p_cfg = &g_timer0_cfg, + .p_api = &g_timer_on_gpt +}; +sci_uart_instance_ctrl_t g_uart9_ctrl; + + baud_setting_t g_uart9_baud_setting = + { + /* Baud rate calculated with 0.160% error. */ .semr_baudrate_bits_b.abcse = 0, .semr_baudrate_bits_b.abcs = 0, .semr_baudrate_bits_b.bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t) 256, .semr_baudrate_bits_b.brme = false + }; + + /** UART extended configuration for UARTonSCI HAL driver */ + const sci_uart_extended_cfg_t g_uart9_cfg_extend = + { + .clock = SCI_UART_CLOCK_INT, + .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart9_baud_setting, + .flow_control = SCI_UART_FLOW_CONTROL_RTS, + #if 0xFF != 0xFF + .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX, + #endif + .rs485_setting = { + .enable = SCI_UART_RS485_DISABLE, + .polarity = SCI_UART_RS485_DE_POLARITY_HIGH, + #if 0xFF != 0xFF + .de_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .de_control_pin = (bsp_io_port_pin_t) UINT16_MAX, + #endif + }, + }; + + /** UART interface configuration */ + const uart_cfg_t g_uart9_cfg = + { + .channel = 9, + .data_bits = UART_DATA_BITS_8, + .parity = UART_PARITY_OFF, + .stop_bits = UART_STOP_BITS_1, + .p_callback = NULL, + .p_context = NULL, + .p_extend = &g_uart9_cfg_extend, +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, +#else + .p_transfer_tx = &RA_NOT_DEFINED, +#endif +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, +#else + .p_transfer_rx = &RA_NOT_DEFINED, +#endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), + .tei_ipl = (12), + .eri_ipl = (12), +#if defined(VECTOR_NUMBER_SCI9_RXI) + .rxi_irq = VECTOR_NUMBER_SCI9_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI9_TXI) + .txi_irq = VECTOR_NUMBER_SCI9_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI9_TEI) + .tei_irq = VECTOR_NUMBER_SCI9_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI9_ERI) + .eri_irq = VECTOR_NUMBER_SCI9_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + }; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart9 = +{ + .p_ctrl = &g_uart9_ctrl, + .p_cfg = &g_uart9_cfg, + .p_api = &g_uart_on_sci +}; +adc_instance_ctrl_t g_adc0_ctrl; +const adc_extended_cfg_t g_adc0_cfg_extend = +{ + .add_average_count = ADC_ADD_OFF, + .clearing = ADC_CLEAR_AFTER_READ_ON, + .trigger_group_b = ADC_TRIGGER_SYNC_ELC, + .double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED, + .adc_vref_control = ADC_VREF_CONTROL_AVCC0_AVSS0, + .enable_adbuf = 0, +#if defined(VECTOR_NUMBER_ADC0_WINDOW_A) + .window_a_irq = VECTOR_NUMBER_ADC0_WINDOW_A, +#else + .window_a_irq = FSP_INVALID_VECTOR, +#endif + .window_a_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_ADC0_WINDOW_B) + .window_b_irq = VECTOR_NUMBER_ADC0_WINDOW_B, +#else + .window_b_irq = FSP_INVALID_VECTOR, +#endif + .window_b_ipl = (BSP_IRQ_DISABLED), +}; +const adc_cfg_t g_adc0_cfg = +{ + .unit = 0, + .mode = ADC_MODE_SINGLE_SCAN, + .resolution = ADC_RESOLUTION_14_BIT, + .alignment = (adc_alignment_t) ADC_ALIGNMENT_RIGHT, + .trigger = ADC_TRIGGER_SOFTWARE, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = &NULL, +#endif + .p_extend = &g_adc0_cfg_extend, +#if defined(VECTOR_NUMBER_ADC0_SCAN_END) + .scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END, +#else + .scan_end_irq = FSP_INVALID_VECTOR, +#endif + .scan_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_ADC0_SCAN_END_B) + .scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B, +#else + .scan_end_b_irq = FSP_INVALID_VECTOR, +#endif + .scan_end_b_ipl = (BSP_IRQ_DISABLED), +}; +#if ((0) | (0)) +const adc_window_cfg_t g_adc0_window_cfg = +{ + .compare_mask = 0, + .compare_mode_mask = 0, + .compare_cfg = (0) | (0) | (0) | (ADC_COMPARE_CFG_EVENT_OUTPUT_OR), + .compare_ref_low = 0, + .compare_ref_high = 0, + .compare_b_channel = (ADC_WINDOW_B_CHANNEL_0), + .compare_b_mode = (ADC_WINDOW_B_MODE_LESS_THAN_OR_OUTSIDE), + .compare_b_ref_low = 0, + .compare_b_ref_high = 0, +}; +#endif +const adc_channel_cfg_t g_adc0_channel_cfg = +{ + .scan_mask = 0, + .scan_mask_group_b = 0, + .priority_group_a = ADC_GROUP_A_PRIORITY_OFF, + .add_mask = 0, + .sample_hold_mask = 0, + .sample_hold_states = 24, +#if ((0) | (0)) + .p_window_cfg = (adc_window_cfg_t *) &g_adc0_window_cfg, +#else + .p_window_cfg = NULL, +#endif +}; +/* Instance structure to use this module. */ +const adc_instance_t g_adc0 = +{ + .p_ctrl = &g_adc0_ctrl, + .p_cfg = &g_adc0_cfg, + .p_channel_cfg = &g_adc0_channel_cfg, + .p_api = &g_adc_on_adc +}; +dtc_instance_ctrl_t g_transfer1_ctrl; + +transfer_info_t g_transfer1_info = +{ + .transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, + .transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_DESTINATION, + .transfer_settings_word_b.irq = TRANSFER_IRQ_END, + .transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_DISABLED, + .transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_FIXED, + .transfer_settings_word_b.size = TRANSFER_SIZE_2_BYTE, + .transfer_settings_word_b.mode = TRANSFER_MODE_NORMAL, + .p_dest = (void *) NULL, + .p_src = (void const *) NULL, + .num_blocks = 0, + .length = 0, +}; + +const dtc_extended_cfg_t g_transfer1_cfg_extend = +{ + .activation_source = VECTOR_NUMBER_SPI0_RXI, +}; +const transfer_cfg_t g_transfer1_cfg = +{ + .p_info = &g_transfer1_info, + .p_extend = &g_transfer1_cfg_extend, +}; + +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer1 = +{ + .p_ctrl = &g_transfer1_ctrl, + .p_cfg = &g_transfer1_cfg, + .p_api = &g_transfer_on_dtc +}; +dtc_instance_ctrl_t g_transfer0_ctrl; + +transfer_info_t g_transfer0_info = +{ + .transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_FIXED, + .transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_SOURCE, + .transfer_settings_word_b.irq = TRANSFER_IRQ_END, + .transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_DISABLED, + .transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, + .transfer_settings_word_b.size = TRANSFER_SIZE_2_BYTE, + .transfer_settings_word_b.mode = TRANSFER_MODE_NORMAL, + .p_dest = (void *) NULL, + .p_src = (void const *) NULL, + .num_blocks = 0, + .length = 0, +}; + +const dtc_extended_cfg_t g_transfer0_cfg_extend = +{ + .activation_source = VECTOR_NUMBER_SPI0_TXI, +}; +const transfer_cfg_t g_transfer0_cfg = +{ + .p_info = &g_transfer0_info, + .p_extend = &g_transfer0_cfg_extend, +}; + +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer0 = +{ + .p_ctrl = &g_transfer0_ctrl, + .p_cfg = &g_transfer0_cfg, + .p_api = &g_transfer_on_dtc +}; +#define RA_NOT_DEFINED (UINT32_MAX) +#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + +/* If the transfer module is DMAC, define a DMAC transfer callback. */ +#include "r_dmac.h" +extern void spi_tx_dmac_callback(spi_instance_ctrl_t const * const p_ctrl); + +void g_spi0_tx_transfer_callback (dmac_callback_args_t * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); + spi_tx_dmac_callback(&g_spi0_ctrl); +} +#endif + +#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + +/* If the transfer module is DMAC, define a DMAC transfer callback. */ +#include "r_dmac.h" +extern void spi_rx_dmac_callback(spi_instance_ctrl_t const * const p_ctrl); + +void g_spi0_rx_transfer_callback (dmac_callback_args_t * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); + spi_rx_dmac_callback(&g_spi0_ctrl); +} +#endif +#undef RA_NOT_DEFINED + +spi_instance_ctrl_t g_spi0_ctrl; + +/** SPI extended configuration for SPI HAL driver */ +const spi_extended_cfg_t g_spi0_ext_cfg = +{ + .spi_clksyn = SPI_SSL_MODE_CLK_SYN, + .spi_comm = SPI_COMMUNICATION_FULL_DUPLEX, + .ssl_polarity = SPI_SSLP_LOW, + .ssl_select = SPI_SSL_SELECT_SSL0, + .mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE, + .parity = SPI_PARITY_MODE_DISABLE, + .byte_swap = SPI_BYTE_SWAP_DISABLE, + .spck_div = { + /* Actual calculated bitrate: 12000000. */ .spbr = 1, .brdv = 0 + }, + .spck_delay = SPI_DELAY_COUNT_1, + .ssl_negation_delay = SPI_DELAY_COUNT_1, + .next_access_delay = SPI_DELAY_COUNT_1 + }; + +/** SPI configuration for SPI HAL driver */ +const spi_cfg_t g_spi0_cfg = +{ + .channel = 0, + +#if defined(VECTOR_NUMBER_SPI0_RXI) + .rxi_irq = VECTOR_NUMBER_SPI0_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SPI0_TXI) + .txi_irq = VECTOR_NUMBER_SPI0_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SPI0_TEI) + .tei_irq = VECTOR_NUMBER_SPI0_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SPI0_ERI) + .eri_irq = VECTOR_NUMBER_SPI0_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + + .rxi_ipl = (12), + .txi_ipl = (12), + .tei_ipl = (12), + .eri_ipl = (12), + + .operating_mode = SPI_MODE_MASTER, + + .clk_phase = SPI_CLK_PHASE_EDGE_ODD, + .clk_polarity = SPI_CLK_POLARITY_LOW, + + .mode_fault = SPI_MODE_FAULT_ERROR_DISABLE, + .bit_order = SPI_BIT_ORDER_MSB_FIRST, + .p_transfer_tx = g_spi0_P_TRANSFER_TX, + .p_transfer_rx = g_spi0_P_TRANSFER_RX, + .p_callback = spi_callback, + + .p_context = NULL, + .p_extend = (void *)&g_spi0_ext_cfg, +}; + +/* Instance structure to use this module. */ +const spi_instance_t g_spi0 = +{ + .p_ctrl = &g_spi0_ctrl, + .p_cfg = &g_spi0_cfg, + .p_api = &g_spi_on_spi +}; +flash_lp_instance_ctrl_t g_flash0_ctrl; +const flash_cfg_t g_flash0_cfg = +{ + .data_flash_bgo = false, + .p_callback = NULL, + .p_context = NULL, + .ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_FCU_FRDYI) + .irq = VECTOR_NUMBER_FCU_FRDYI, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const flash_instance_t g_flash0 = +{ + .p_ctrl = &g_flash0_ctrl, + .p_cfg = &g_flash0_cfg, + .p_api = &g_flash_on_flash_lp +}; +rtc_instance_ctrl_t g_rtc0_ctrl; +const rtc_error_adjustment_cfg_t g_rtc0_err_cfg = +{ + .adjustment_mode = RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC, + .adjustment_period = RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND, + .adjustment_type = RTC_ERROR_ADJUSTMENT_NONE, + .adjustment_value = 0, +}; +const rtc_cfg_t g_rtc0_cfg = +{ + .clock_source = RTC_CLOCK_SOURCE_LOCO, + .freq_compare_value_loco = 255, + .p_err_cfg = &g_rtc0_err_cfg, + .p_callback = NULL, + .p_context = NULL, + .alarm_ipl = (14), + .periodic_ipl = (14), + .carry_ipl = (14), +#if defined(VECTOR_NUMBER_RTC_ALARM) + .alarm_irq = VECTOR_NUMBER_RTC_ALARM, +#else + .alarm_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_RTC_PERIOD) + .periodic_irq = VECTOR_NUMBER_RTC_PERIOD, +#else + .periodic_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_RTC_CARRY) + .carry_irq = VECTOR_NUMBER_RTC_CARRY, +#else + .carry_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const rtc_instance_t g_rtc0 = +{ + .p_ctrl = &g_rtc0_ctrl, + .p_cfg = &g_rtc0_cfg, + .p_api = &g_rtc_on_rtc +}; +void g_hal_init(void) { +g_common_init(); +} diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/hal_data.h b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/hal_data.h new file mode 100644 index 000000000000..696872b426b9 --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/hal_data.h @@ -0,0 +1,125 @@ +/* generated HAL header file - do not edit */ +#ifndef HAL_DATA_H_ +#define HAL_DATA_H_ +#include +#include "bsp_api.h" +#include "common_data.h" +#include "r_lpm.h" +#include "r_lpm_api.h" +#include "r_gpt.h" +#include "r_timer_api.h" +#include "r_sci_uart.h" + #include "r_uart_api.h" +#include "r_adc.h" +#include "r_adc_api.h" +#include "r_dtc.h" +#include "r_transfer_api.h" +#include "r_spi.h" +#include "r_flash_lp.h" +#include "r_flash_api.h" +#include "r_rtc.h" +#include "r_rtc_api.h" +FSP_HEADER +/** lpm Instance */ +extern const lpm_instance_t g_lpm0; + +/** Access the LPM instance using these structures when calling API functions directly (::p_api is not used). */ +extern lpm_instance_ctrl_t g_lpm0_ctrl; +extern const lpm_cfg_t g_lpm0_cfg; +/** Timer on GPT Instance. */ +extern const timer_instance_t g_timer0; + +/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */ +extern gpt_instance_ctrl_t g_timer0_ctrl; +extern const timer_cfg_t g_timer0_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/** UART on SCI Instance. */ + extern const uart_instance_t g_uart9; + + /** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ + extern sci_uart_instance_ctrl_t g_uart9_ctrl; + extern const uart_cfg_t g_uart9_cfg; + extern const sci_uart_extended_cfg_t g_uart9_cfg_extend; + + #ifndef NULL + void NULL(uart_callback_args_t * p_args); + #endif +/** ADC on ADC Instance. */ +extern const adc_instance_t g_adc0; + +/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */ +extern adc_instance_ctrl_t g_adc0_ctrl; +extern const adc_cfg_t g_adc0_cfg; +extern const adc_channel_cfg_t g_adc0_channel_cfg; + +#ifndef NULL +void NULL(adc_callback_args_t * p_args); +#endif + +#ifndef NULL +#define ADC_DMAC_CHANNELS_PER_BLOCK_NULL 0 +#endif +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer1; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer1_ctrl; +extern const transfer_cfg_t g_transfer1_cfg; +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer0; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer0_ctrl; +extern const transfer_cfg_t g_transfer0_cfg; +/** SPI on SPI Instance. */ +extern const spi_instance_t g_spi0; + +/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */ +extern spi_instance_ctrl_t g_spi0_ctrl; +extern const spi_cfg_t g_spi0_cfg; + +/** Callback used by SPI Instance. */ +#ifndef spi_callback +void spi_callback(spi_callback_args_t * p_args); +#endif + + +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == g_transfer0) + #define g_spi0_P_TRANSFER_TX (NULL) +#else + #define g_spi0_P_TRANSFER_TX (&g_transfer0) +#endif +#if (RA_NOT_DEFINED == g_transfer1) + #define g_spi0_P_TRANSFER_RX (NULL) +#else + #define g_spi0_P_TRANSFER_RX (&g_transfer1) +#endif +#undef RA_NOT_DEFINED +/* Flash on Flash LP Instance. */ +extern const flash_instance_t g_flash0; + +/** Access the Flash LP instance using these structures when calling API functions directly (::p_api is not used). */ +extern flash_lp_instance_ctrl_t g_flash0_ctrl; +extern const flash_cfg_t g_flash0_cfg; + +#ifndef NULL +void NULL(flash_callback_args_t * p_args); +#endif +/* RTC Instance. */ +extern const rtc_instance_t g_rtc0; + +/** Access the RTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern rtc_instance_ctrl_t g_rtc0_ctrl; +extern const rtc_cfg_t g_rtc0_cfg; + +#ifndef NULL +void NULL(rtc_callback_args_t * p_args); +#endif +void hal_entry(void); +void g_hal_init(void); +FSP_FOOTER +#endif /* HAL_DATA_H_ */ diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/main.c b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/main.c new file mode 100644 index 000000000000..42c5904834c9 --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/main.c @@ -0,0 +1,6 @@ +/* generated main source file - do not edit */ +#include "hal_data.h" + int main(void) { + hal_entry(); + return 0; + } diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/pin_data.c b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/pin_data.c new file mode 100644 index 000000000000..720c02ab268c --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/pin_data.c @@ -0,0 +1,115 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport_api.h" + + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { + { + .pin = BSP_IO_PORT_00_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_01_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_01_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_01_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_01_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) + }, + { + .pin = BSP_IO_PORT_01_PIN_10, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) + }, + { + .pin = BSP_IO_PORT_02_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CLKOUT_COMP_RTC) + }, + { + .pin = BSP_IO_PORT_02_PIN_12, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CLKOUT_COMP_RTC) + }, + { + .pin = BSP_IO_PORT_02_PIN_13, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CLKOUT_COMP_RTC) + }, + { + .pin = BSP_IO_PORT_02_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CLKOUT_COMP_RTC) + }, + { + .pin = BSP_IO_PORT_02_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CLKOUT_COMP_RTC) + }, + { + .pin = BSP_IO_PORT_03_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_04_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_04_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_04_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_09_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_09_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, +}; + +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], +}; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) +{ + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/vector_data.c b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/vector_data.c new file mode 100644 index 000000000000..80e1d0073845 --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/vector_data.c @@ -0,0 +1,43 @@ +/* generated vector source file - do not edit */ + #include "bsp_api.h" + /* Do not build these data structures if no interrupts are currently allocated because IAR will have build errors. */ + #if VECTOR_DATA_IRQ_COUNT > 0 + BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = + { + [0] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */ + [1] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */ + [2] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */ + [3] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */ + [4] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */ + [5] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */ + [6] = spi_eri_isr, /* SPI0 ERI (Error) */ + [7] = sci_uart_rxi_isr, /* SCI9 RXI (Received data full) */ + [8] = sci_uart_txi_isr, /* SCI9 TXI (Transmit data empty) */ + [9] = sci_uart_tei_isr, /* SCI9 TEI (Transmit end) */ + [10] = sci_uart_eri_isr, /* SCI9 ERI (Receive error) */ + [11] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */ + [12] = usbfs_d0fifo_handler, /* USBFS FIFO 0 (DMA transfer request 0) */ + [13] = usbfs_d1fifo_handler, /* USBFS FIFO 1 (DMA transfer request 1) */ + [14] = usbfs_resume_handler, /* USBFS RESUME (USBFS resume interrupt) */ + [15] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */ + }; + const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = + { + [0] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */ + [1] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */ + [2] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */ + [3] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */ + [4] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */ + [5] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */ + [6] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */ + [7] = BSP_PRV_IELS_ENUM(EVENT_SCI9_RXI), /* SCI9 RXI (Received data full) */ + [8] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TXI), /* SCI9 TXI (Transmit data empty) */ + [9] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TEI), /* SCI9 TEI (Transmit end) */ + [10] = BSP_PRV_IELS_ENUM(EVENT_SCI9_ERI), /* SCI9 ERI (Receive error) */ + [11] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0), /* ICU IRQ0 (External pin interrupt 0) */ + [12] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */ + [13] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1), /* USBFS FIFO 1 (DMA transfer request 1) */ + [14] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */ + [15] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT), /* USBFS INT (USBFS interrupt) */ + }; + #endif \ No newline at end of file diff --git a/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/vector_data.h b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/vector_data.h new file mode 100644 index 000000000000..df331254e7d5 --- /dev/null +++ b/ports/renesas-ra/boards/WEACT_RA4M1_CORE/ra_gen/vector_data.h @@ -0,0 +1,64 @@ +/* generated vector header file - do not edit */ + #ifndef VECTOR_DATA_H + #define VECTOR_DATA_H + #ifdef __cplusplus + extern "C" { + #endif + /* Number of interrupts allocated */ + #ifndef VECTOR_DATA_IRQ_COUNT + #define VECTOR_DATA_IRQ_COUNT (16) + #endif + /* ISR prototypes */ + void rtc_alarm_periodic_isr(void); + void rtc_carry_isr(void); + void spi_rxi_isr(void); + void spi_txi_isr(void); + void spi_tei_isr(void); + void spi_eri_isr(void); + void sci_uart_rxi_isr(void); + void sci_uart_txi_isr(void); + void sci_uart_tei_isr(void); + void sci_uart_eri_isr(void); + void r_icu_isr(void); + void usbfs_d0fifo_handler(void); + void usbfs_d1fifo_handler(void); + void usbfs_resume_handler(void); + void usbfs_interrupt_handler(void); + + /* Vector table allocations */ + #define VECTOR_NUMBER_RTC_ALARM ((IRQn_Type) 0) /* RTC ALARM (Alarm interrupt) */ + #define RTC_ALARM_IRQn ((IRQn_Type) 0) /* RTC ALARM (Alarm interrupt) */ + #define VECTOR_NUMBER_RTC_PERIOD ((IRQn_Type) 1) /* RTC PERIOD (Periodic interrupt) */ + #define RTC_PERIOD_IRQn ((IRQn_Type) 1) /* RTC PERIOD (Periodic interrupt) */ + #define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type) 2) /* RTC CARRY (Carry interrupt) */ + #define RTC_CARRY_IRQn ((IRQn_Type) 2) /* RTC CARRY (Carry interrupt) */ + #define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type) 3) /* SPI0 RXI (Receive buffer full) */ + #define SPI0_RXI_IRQn ((IRQn_Type) 3) /* SPI0 RXI (Receive buffer full) */ + #define VECTOR_NUMBER_SPI0_TXI ((IRQn_Type) 4) /* SPI0 TXI (Transmit buffer empty) */ + #define SPI0_TXI_IRQn ((IRQn_Type) 4) /* SPI0 TXI (Transmit buffer empty) */ + #define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type) 5) /* SPI0 TEI (Transmission complete event) */ + #define SPI0_TEI_IRQn ((IRQn_Type) 5) /* SPI0 TEI (Transmission complete event) */ + #define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type) 6) /* SPI0 ERI (Error) */ + #define SPI0_ERI_IRQn ((IRQn_Type) 6) /* SPI0 ERI (Error) */ + #define VECTOR_NUMBER_SCI9_RXI ((IRQn_Type) 7) /* SCI9 RXI (Received data full) */ + #define SCI9_RXI_IRQn ((IRQn_Type) 7) /* SCI9 RXI (Received data full) */ + #define VECTOR_NUMBER_SCI9_TXI ((IRQn_Type) 8) /* SCI9 TXI (Transmit data empty) */ + #define SCI9_TXI_IRQn ((IRQn_Type) 8) /* SCI9 TXI (Transmit data empty) */ + #define VECTOR_NUMBER_SCI9_TEI ((IRQn_Type) 9) /* SCI9 TEI (Transmit end) */ + #define SCI9_TEI_IRQn ((IRQn_Type) 9) /* SCI9 TEI (Transmit end) */ + #define VECTOR_NUMBER_SCI9_ERI ((IRQn_Type) 10) /* SCI9 ERI (Receive error) */ + #define SCI9_ERI_IRQn ((IRQn_Type) 10) /* SCI9 ERI (Receive error) */ + #define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type) 11) /* ICU IRQ0 (External pin interrupt 0) */ + #define ICU_IRQ0_IRQn ((IRQn_Type) 11) /* ICU IRQ0 (External pin interrupt 0) */ + #define VECTOR_NUMBER_USBFS_FIFO_0 ((IRQn_Type) 12) /* USBFS FIFO 0 (DMA transfer request 0) */ + #define USBFS_FIFO_0_IRQn ((IRQn_Type) 12) /* USBFS FIFO 0 (DMA transfer request 0) */ + #define VECTOR_NUMBER_USBFS_FIFO_1 ((IRQn_Type) 13) /* USBFS FIFO 1 (DMA transfer request 1) */ + #define USBFS_FIFO_1_IRQn ((IRQn_Type) 13) /* USBFS FIFO 1 (DMA transfer request 1) */ + #define VECTOR_NUMBER_USBFS_RESUME ((IRQn_Type) 14) /* USBFS RESUME (USBFS resume interrupt) */ + #define USBFS_RESUME_IRQn ((IRQn_Type) 14) /* USBFS RESUME (USBFS resume interrupt) */ + #define VECTOR_NUMBER_USBFS_INT ((IRQn_Type) 15) /* USBFS INT (USBFS interrupt) */ + #define USBFS_INT_IRQn ((IRQn_Type) 15) /* USBFS INT (USBFS interrupt) */ + #ifdef __cplusplus + } + #endif + #endif /* VECTOR_DATA_H */ \ No newline at end of file